JP2576191B2 - Recording and playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus for simultaneously recording two types of asynchronous signals such as a video signal and a digital audio signal.

[Conventional technology]

An example of a recording / reproducing apparatus for simultaneously recording two asynchronous signals is disclosed in Japanese Patent Application No. 61-174126. An example of signal processing at the time of recording in this apparatus is shown in FIG. 4 as a block diagram.

First, at the time of recording, an analog audio input signal is input from an analog audio signal input terminal (10) and is subjected to analog / digital conversion (hereinafter referred to as A / D conversion). The digital audio input signal is a digital audio signal input terminal (21). After passing through an interface circuit (22), the digital audio signal processing circuit (12) adds an error correcting code (in this device, a double Reed-Solomon code) and performs interleaving. For example, a digital signal of a predetermined recording format is encoded, modulated by a modulation circuit (13), passed through a recording amplifier-I (14), and a magnetic tape (20) by a magnetic head-I (15). Will be recorded. On the other hand, the video input signal is connected to the video signal input terminal (1
6) input by the video signal processing circuit (17),
After signal processing such as modulation, recording amplifier-II (18)
And the same magnetic tape (2
0) is recorded.

This device has a digital audio signal sample number N per field and per channel. If the maximum number of samples that can be recorded in one field does not reach the maximum number of samples that can be recorded in the field Nmax, the dummy sample for the difference (Nmax−N)
After recording the data and converting the dummy data into a continuous data string, the dummy data is arranged together with the digital audio signal, and a certain number of data such as the digital audio signal to be recorded in one field and its error correction code are included. When the digital audio signal consists of And the field An identification signal for the field is recorded for each data block.

FIG. 3A shows the spectrum of a video signal recorded in a VHS VTR in the NTSC system, and FIG.
The spectrum of the i-Fi FM audio signal.
The M signal is deeply recorded in a lower layer on the magnetic tape of the recording video signal. Here, when the digital audio signal is recorded together with the video signal, as in the case of the FM audio signal, FIG.
It is assumed that deep recording is performed below a recording video signal in a band as shown in FIG.

Now, an example of this apparatus will be described with reference to the drawings.
In FIG. 6, (39) shows L and R channel input data (including dummy data), (35) shows a 3D block delay circuit, (34) shows a D block delay circuit, and (40) shows a D block delay circuit. ~
29D block delay circuit (36), C ₂ Paritei coding circuit (37), C ₁ Paritei-coding circuit, (38) the output data group. However, in this example, D = 4, and D indicates the delay amount corresponding to one block in FIG. 7, and when recording as serial data one block at a time as shown in FIG. It becomes equal to the repetition period. The numbers 0 to 37 assigned to the recording data shown at the right end of FIG. 1 are hereinafter referred to as word numbers.

FIG. 7 shows a recording data structure in the above recording / reproducing apparatus. The data in one field is the preamble,
It consists of a data area consisting of 134 blocks and a post ampoule. Furthermore, the data in one block is
Hetsuda (4Byte), the even-numbered PCM data (L, R2Byte by total 12 bytes = 6 samples) by sampling, C ₂ parity is an error-correcting code (in total 6 Bytes 3 Bytes), PCM data from the odd-numbered sampling error Correction code C ₂ parity (total 6
Remaining in Byte of 3 Bytes) and consisting of C ₁ Paritei (4Byte).

After the data having such a data structure is subjected to a predetermined modulation, it is recorded on the VTR track as shown in FIG.

Here, the maximum number of samples per channel recorded in one field is Nmax = 6 × 134 = 804 samples. Number of samples N _E =
For the 804 field, Nmax and N are equal, so
PCM data is recorded in the PCM data area in one field. On the other hand, for the field with the number of samples N _D = 798, data of (Nmax−N _D = 6 (samples) is used as dummy data.

A schematic diagram of the data structure of the field in the field each field and the number of samples N _E of the number of samples N _D shown in FIG. 9.

First, in the case of a field with the number of samples N _E = 804, each data L ₀ , R ₀ , L ₁ , R ₁ ,..., L ₈₀₃ , in the input data group (39)
Since no dummy data is recorded in the R ₈₀₃ , all input data is PCM data. Each data in the input data set _{^{(39) ▲ L '0 ▼}} , ▲ R' 0 ▼, ▲ L '1 ▼, ▲ R'
₁ ▼,..., L ^′ ₈₀₃ ▼, ▲ R ^′ ₈₀₃ ▼ are D-block (here, D = 4) delay circuits (34) and 3D-block delay circuits (35), respectively. delayed 3D block fraction, after C ₂ Paritei is generated by C ₂ Paritei encoding circuit (36), the sampled PCM data to the odd and the sampled PCM data to the even-numbered are separated, C ₂ by connexion interleaved D~29D block delay circuit for performing a delay of D~29D blocks each correspond (40) with Paritei is made, C ₁ Paritei coding circuit (3
After generating the C ₁ Paritei 7), is output from the output terminal group (38) as the output data group, is added to Hetsuda, the 1 block record data. In practice, the data sequence of the block No. (i + 1) next to the data sequence of the block No. i is modulated as serial data, respectively.
It is recorded as shown in FIG.

Next, the field number of samples N _D = 798, in succession from the first input data to be recorded on one field 6
Dummy data is input to the data of the samples, and thereafter, PCM data is recorded in the same manner as in the field of the number of samples N _E = 804.

[Problems to be solved by the invention]

Since the conventional recording / reproducing device is configured as described above, the number of samples is In the field, how to insert dummy data
There were problems such as the timing of inputting PCM data and dummy data was not clear.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is a recording / reproducing apparatus capable of reliably recording with a simple circuit configuration when two types of asynchronous signals are to be simultaneously recorded. The purpose is to obtain.

[Means for solving the problem]

The recording / reproducing apparatus according to the present invention, for example, when trying to simultaneously record two types of asynchronous video signals and PCM data on a VTR, reduces the number of samples of PCM data to be recorded in one field. A memory is used to set the value between the two values of the above. Writing data to the memory is performed using the clock related to fs, and reading data from the memory is performed using a clock equivalent to Nmax per field. together to perform, as written in the clock of the same rate as when writing the PCM data in advance dummy data prior to PCM data when writing the data, and the number of specimens N _E or N _D
In field is one in which the so skip the number corresponding the address of the write side to the number of samples Nmax-N _E or Nmax-N _D.

[Action]

In the present invention, the number of samples of PCM data recorded in one field is The digital audio signal processing circuit that adjusts the fraction of fs / fv to simulate the two signals by setting the value between the two types of values, and also processes PCM data inside the device. Using a memory at, writing data to the memory is done at the same rate clock related to fs,
Reading data from memory is Nm per field
The PCM data is converted into a recording format on a track by performing the processing with a clock corresponding to ax. At this time, since the number of samples per field is N _E or _{N D (NmaxN E> N D} ), since the direction of reading speed is increased with respect to writing speed, address side of the write address of the read side The phenomenon of catching up occurs. Therefore, skipping the number corresponding the address of the write side to the number of samples Nmax-N _E or Nmax-N _D, so as not caught up the read side address. In addition, when writing data to memory, dummy data is written at the same rate clock as PCM data ahead of the fixed address in the RCM data, so that writing of dummy data can be performed smoothly. When the address on the writing side is skipped, dummy data is surely written on the skipped address.

(Example of the invention)

As an embodiment of the present invention, a case will be described in which a digital audio signal of fs = 48 KHz is recorded in a TVR in which a video signal is an NTSC color television signal (field frequency fv = 59.94 Hz).

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a digital audio signal processing circuit according to this embodiment.

In FIG. 1, (12) is a digital audio signal processing circuit, (41) is a PCM data selector, (42) is a dummy data generation circuit, and (33) is a selector 1 for selecting PCM data and dummy data. 23) is a memory for writing and reading data, (24) is an encoder for error correction coding of data, (25) is a selector 2 for selecting an address to be supplied to the memory (23), and (26) is A / D side address generation circuit that generates an address for writing data to memory (23), (27) is a coded address generation circuit that generates an address for performing error correction coding, and (28) is a memory (2
3) A modulation (hereinafter abbreviated as MOD.) Side address generation circuit that generates an address from which data is read out, (29) a flag generation circuit, (30) a jump timing pulse generation circuit,
(31) is a header adding circuit for adding a header section to the encoded data, and (13) is a modulation circuit.

FIG. 3 shows a schematic diagram of a data structure in the memory (23) as a memory map. The numbers on the vertical and horizontal axes of the map represent the addresses of the memory. The addresses on the vertical axis (hereinafter referred to as x) are 0 to 255 (8 bits), and the addresses on the horizontal axis (hereinafter referred to as y) are 0 to 63 (6 bits). Among them, a number equal to the number of symbols of the data in one block excluding the header part,
That is, data is written in one symbol (= 8 bits) per address between 0 and 33. Hereinafter, the address is displayed in the form of (x, y).

What is shown here is the MOD. Side address, that is, the address to start reading is (0, y) (y = 0, 1,
..., 33), it is the relative position of the address where each data is written. For example, at this time,
The positions where data is written are indicated by “DD” at addresses (25, 0), (29.1),.
1, 26). The position where the PCM data is written is represented by an address (21,
0), (25, 1),..., (137, 26). That is,
In the position where the dummy data and the PCM data are written, the dummy data precedes the PCM data by four x addresses on the vertical axis. Furthermore, C ₂ code, C ₁ code at the address indicated by the respective data error-correction-coded "C ₂ ENc" (3,0), (7,1), ..., (11
9, 26) and “C ₁ ENc” (1, 0),
(1, 1), ..., (1, 26).

Reading and writing of data on the actual memory is "DD"
Are written in such a way as to move from top to bottom on the memory map shown in FIG. 3. When the address reaches x address 255, it returns to address 0 and goes around x address 0 to 255. Will be

On the circuit, first, the PCM data output from the PCM data selector (41) and the dummy data generated by the dummy data generation circuit (42) are input to the selector 1 (33). In the selector 1 (33), dummy data is stored in the memory (23).
Each data is sent to the memory (23) by controlling so that the data write position value precedes the PCM data write position by four x addresses. Writing of PCM data and dummy data to the memory (23) is performed by clocks of the same rate.

The data read from the memory (23) is encoded by the encoder (24)
After a predetermined recording format is encoded in step (1), a header section (4 bytes) is added in a header adding circuit (31) and sent to a modulator (13). At this time, the A / D side address generation circuit (26), the coded address generation circuit (27), and the MO are used in accordance with the processing of writing or reading data to or from the memory (23).
The address is generated in the D. side address generation circuit (28) and is selected by the selector (25).

Now, if you want to write 804 samples per field, Therefore, α = 4, and the dummy data is Nmax−N _E =
0.

Next, the number of samples When the beta = 2 becomes the dummy data is Nmax-N _D = 6. In this field, 79 written samples
Since the number of read samples is 804, while the number of read samples is 804, there arises a problem that the address on the read side gradually catches up with the address on the write side. So, in order not to catch up with the address on the reading side,
When the 798th sample PCM data has been written to the memory (23), the address of the memory is skipped by six samples of dummy data, that is, one block. In order to perform this processing, a flag generation circuit (29)
Also, a jump timing pulse generating circuit (30) for controlling the timing of skipping an address is provided.

Hereinafter, examples will be described in more detail. FIG. 2 corresponds to the part of the flag generation circuit (29) and the jump timing pulse generation circuit (30) in FIG.

In FIG. 2, (1) is a constant generator 1, (2) is a constant generator 2, (3) is a latch 1, (4) is a one's complement,
(5) is an adder 1, (6) is a comparator 1, (7) is an adder 2, (8) is a latch 2, (9) is a comparator 2, and (32) is an AND gate.

From FIG. 3, it can be seen that when writing or reading data to or from the memory is performed in a normal state, the address of the MOD becomes (0,
y), the end of the write address on the A / D side is (13
7, 26).

In FIG. 2, an address at which data is read from or written to the memory (23) is generated from each address generating circuit.
At this time, the MO generated by the MOD-side address generation circuit (28)
Record the x address of D. with a latch (13). Subsequently, the A / D x address is input to the 1's complementer (4), and the 1's complement of the A / D x address and the MOD. X address are output to the adder 1 (5) at the same timing. And take the difference between them. This address difference is usually 137, but MO
Since the progress speed of the x address of D. and the x address of A / D are different, it may be smaller than 137. Therefore,
This address difference is input to the comparator 1 (6), and a constant 137 is generated from the constant generator 1 (1) and input to the comparator (6), and is compared with the address difference. If the, sets a flag in its field, it sets the field number of samples N _D.

Now, assuming that one field of data has been written from the address (0, y) of the MOD., The head address of the next field is (134, 0). The A / D (write) address immediately before this address is detected. A
The number of x addresses required to write / D data is 116
Therefore, the x address is 134 + 116-1 = 249, that is, the address to be obtained is (249, 26).

Follow go-between, now, n field first number of samples is N _D (n =
Considering a case where data is written in (1, 2,...), (N
-1) Assuming that the address of MOD. In the field is m, the x-address at the end of the A / D in the n-th field is (m + 249), so a timing pulse is generated when this address (m + 249) is detected. The address is skipped at the timing of this pulse.

In the circuit shown in FIG. 2, first, the offset amount "249" is set in advance by the constant generator 2 (2), and is provided to the adder (7). From each address generating circuit, an address for reading / writing to the memory is sent. Among them, the x address of MOD. In the (n-1) th field is sent to the adder (7), and the offset amount "249" is added. Then, an address (m + 249) is generated. On the other hand, the x address at the end of the A / D in the nth field is latched in the latch 2 (8). The A / D terminal address and the above-mentioned address (m + 249) are sent to the comparator 2 (9) at the same timing, and the two are compared. Then, a jump pulse is generated as the output of the AND gate (32) only when both match and the flag is set by the flag generation circuit.

In the above embodiment, the case where the video signal and the digital audio signal are recorded on the VTR has been described. However, the present invention is not limited to this case. The same effects as in the embodiment are exhibited. Further, in the above-described embodiment, the case where the address skipping cycle is the field cycle has been described, but it is also possible to perform the address skipping at a certain fixed cycle. In this embodiment, the number of samples recorded in one field is Nmax.
= Is shown for the case where the N _E, also has the same effect as the present embodiment in the case of Nmax> N _E.

〔The invention's effect〕

As described above, according to the present invention, the digital audio signal processing circuit in the recording / reproducing apparatus is provided with a memory,
A means for writing data and a digital audio signal to a memory at a clock of the same rate related to fs (sampling frequency); and a means for reading data from the memory at a clock corresponding to Nmax per field. in the field, it means for setting the number of samples of the data to be recorded to a value between N _E and N _D, the number of samples in each field unit (Nmax
-N _E ) or (Nmax -N _D ) means for skipping the write address of the memory by the number corresponding to (Nmax)-(Nmax -ND). The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital audio signal processing circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a flag generating circuit and a timing pulse generating circuit in a recording / reproducing apparatus according to an embodiment of the present invention. FIG. 3 is a conceptual diagram showing the structure of data in a memory in one embodiment of the present invention, FIG. 4 is a block diagram of an example of signal processing at the time of signal recording in a conventional VTR, and FIG. FIG. 6 is a frequency spectrum diagram showing the frequency allocation of signal modulated waves and VHS Hi-Fi FM audio signals and video signals, FIG. 6 is a block diagram showing a configuration at the time of recording according to the conventional example, and FIG. FIG. 8 is a conceptual diagram showing the structure of data in one field, and FIG.
FIG. 9 is a conceptual diagram showing the relationship between the recording track and recording data of FIG.
Figure is a schematic diagram comparing the data structure in the interior of the sample size and field of N _E, the number of specimens and field of N _D. In the figure, (3) is a latch 1, (4) is a one's complementer, (5)
Is an adder 1, (6) is a comparator 1, (7) is an adder 2, (8) is a latch 2, (9) is a comparator 2, (3)
2) is an AND gate, and (12) is a digital signal processing circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

(57) [Claims] 1. A method for simultaneously recording two asynchronous signals such as a video signal and a digital audio signal, wherein the number of samples of data to be recorded in one field is: Set to a value between the maximum sample size Nmax of data can be recorded (Nmax the above N _E integer) and dummy data the number of data corresponding to the difference between the N _E or N _D 1 field A recording / reproducing apparatus, wherein a memory is provided in a digital audio signal processing circuit in the recording / reproducing apparatus, and dummy data and digital audio signals are
Means for writing into the memory at the same rate clock associated with, and means for reading data from the memory at a clock corresponding to per field Nmax, and, in each field, the number of samples of the data to be recorded and N _E means for setting to a value between N _D, the number of samples in each field unit (Nmax-N _E) or (Nmax-
And a means for skipping the write address of the memory by a number corresponding to _ND ). 2. A digital audio signal processing means for writing the clock of the same rates and dummy data and digital audio signals in a memory in the circuit, the number corresponding to at least the number of samples from the digital audio signal (Nmax-N _D) 2. The recording / reproducing apparatus according to claim 1, wherein dummy data is written in advance of the address. 3. A respective field, means for setting the sample data to be recorded to a value between N _E and N _D is, n (n = 1,
2, ...) at the beginning of the field,
Detecting the address of the memory data is read out at a clock corresponding to N _E per field, and the address of the memory that elaborate writing the next (n + 1) digital audio signal with a clock associated with fs in th field,
Taking the difference between the two, if it becomes smaller than the certain value the difference, of the claims, characterized in that as the field is a (n + 1) number of samples of data that th field is recorded N _D 2. The recording / reproducing apparatus according to claim 1, wherein: 4. In each field, the number of samples (Nmax-
N _E) or (means to skip only the address of the memory number corresponding to Nmax-N _D) from the address of the memory data is being read at the beginning of the n th field, (n +
1) means for calculating an address of a memory from which data is read at the head of a field, and writing of a digital audio signal to an address immediately before the calculated address at the time of writing data to the memory. 2. The recording / reproducing apparatus according to claim 1, further comprising means for skipping the address before writing the address.