JP2576606B2 - Output driver circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output driver circuit, and more particularly, to an output driver circuit provided with a sample and hold circuit at a preceding stage.

[Conventional technology]

Conventionally, as shown in FIG. 4, this type of output driver circuit uses an input signal V
_A sample-and-hold circuit _1A that samples and holds and outputs _IN , an amplifier 21 that inputs the output signal of this sample-and-hold circuit _1A to the non-inverting input terminal, and an output signal of the amplifier 21 that is input to the gate and the source is capacitance. constant current load circuit 23 _a which is connected between the output terminal T _O · ground terminal and the output transistor 22 sexual load circuit 10 receives an output terminal connected T _O to the connected power supply voltage V _DD to the drain flow a predetermined current preparative had been configured to have a buffer circuit 2 _a with the.

FIG. 5 shows the waveforms of the sample and hold control pulse SH and the output signal V _O ′ of this output driver circuit. Buffer circuit
When a level difference exists between the output signal of the sample-and-hold circuit _1A input to the amplifier 21 and the output signal V _O ′, 2 _A charges the capacitive load circuit 10 through the output transistor 22 or sets a constant current. was discharged capacitive load circuit 10 through the load circuit 23 _a, the levels of these output signals is operable to match. Therefore, the constant current load circuit 23 _A, upon discharge of the capacitive load circuit 10, the discharge current has a current capacity enough to supply enough, and electric current of the current capacity corresponding at all times.

[Problems to be solved by the invention]

In the conventional output driver circuit described above, the output signal of the amplifier 21 that inputs the output signal of the sample hold circuit _1A to the non-inverting input terminal and the output signal Vo ′ to the inverting input terminal is input to the gate of the output transistor 22, This transistor 22
Since the source has a structure to be connected to a capacitive load circuit 10 and the constant current load circuit 23 _A, in order to stabilize the fast predetermined value the output signal V _O 'is a large output current through the output transistor 22 must flow to the capacitive load circuit 10, also it is necessary to increase the discharge current from the capacitive load circuit 10 to the constant current load circuit 23 _a, thus a large idle the output transistor 22 and the constant current load circuit 23 _a There is a disadvantage that current flows for a long time and power consumption increases. In particular, when used for a source driver of an active matrix liquid crystal TV, the number of horizontal pixels (normally 200
(~ 1000 lines), this output driver circuit is required, and its power consumption becomes extremely large.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output driver circuit capable of reducing an idling current as much as possible to reduce power consumption and stabilizing an output signal to a predetermined value quickly.

[Means for solving the problem]

The output driver circuit of the present invention cancels the output signal already held at the leading edge of the hold control pulse, samples the input signal with a sampling pulse, holds the signal internally, and holds the internal signal at the trailing edge of the hold control pulse. A sample-and-hold circuit that newly holds and outputs the held signal, and an amplifier that inputs the output signal of the sample-and-hold circuit to a non-inverting input terminal.
An output transistor connected to an output terminal to which a capacitive load circuit is connected and an inverting input terminal of the amplifier; and a constant current load circuit connected between the output terminal and the ground potential terminal and flowing a predetermined current, A buffer circuit for amplifying an output signal of the hold circuit and transmitting the output signal to the output terminal; and a discharge control having a pulse width narrower than the hold control pulse and at a timing between a leading edge and a trailing edge of the hold control pulse. A switch circuit that is turned on by a pulse; and a discharge circuit that connects an input terminal and an output terminal of the buffer circuit to the ground potential terminal with a predetermined impedance.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

After releasing the output signal V _HO already held at the leading edge of the hold control pulse HD, the sample hold circuit 1 samples the input signal _VIN with the sampling pulse SP and internally holds the sampled input signal V _IN . The signal internally held at the trailing edge is newly held and output (V _HO ).

The buffer circuit 2 inputs an output signal V _HO of the sample-and-hold circuit 1 to a non-inverting input terminal, and inputs an output terminal T _O signal to which the capacitive load circuit 10 is connected to an inverting input terminal to an amplifier 21. An output transistor 22 having a source (or drain) connected to the output terminal T _O , a gate connected to the output terminal of the amplifier 21, and a drain (or source) receiving the power supply voltage _VDD.
And a constant current load circuit 23 connected between the output terminal T _O and the ground potential terminal for flowing a predetermined current, amplifies the output signal V _HO of the sample and hold circuit 1 and transmits the amplified signal to the output terminal T _O.

The discharge circuit 3 includes switch circuits 31 connected between the output terminal T _O and the ground potential terminal and between the input terminal (the non-inverting input terminal of the amplifier 21) and the ground potential terminal of the buffer circuit 2, respectively. The switch circuit 31 is provided by a discharge control pulse DC having a narrower pulse width and having a timing between the leading edge and the trailing edge of the hold control pulse HD.
, Respectively, to short-circuit between the output terminal T _O and the ground potential terminal and between the input terminal of the buffer circuit 2 and the ground potential terminal.

FIG. 2 is a waveform chart of signals at various parts for explaining the operation of this embodiment.

After the output signal _VHO of the sample hold circuit 1 is released by the leading edge of the hold control pulse HD, the discharge control pulse D
The switch circuit 31 is closed by C, the input terminal of the buffer circuit 2 is at the ground potential level, while the discharge current of the capacitive load circuit 10 connected to the output terminal T _O flows through the switch circuit 31, and the output signal V _O is It quickly reaches the ground potential level,
Further, the current capacity of the constant current load circuit 23 can be reduced.

The newly sampled signal is held and output to the output of the sample and hold circuit 1 by the trailing edge of the hold control pulse HD. At this time, the switch circuit 31 is opened by the discharge control pulse DC, and thus the buffer circuit is opened. 2 is a normal operation through the output transistor 22 causes rise of the output signal V _O electric current to the capacitive load circuit 10. By increasing the current driving capability of the output transistor 22, the output voltage V _O rapidly rises and can be quickly stabilized at a predetermined value.

Accordingly, since the discharging of the capacitive load circuit 10 is performed by the discharging circuit 3 and the charging is performed via the output transistor 22, the idling current flowing through the output transistor 22 in a steady state other than the charging period of the capacitive load circuit 10 is The idling current flowing through the constant current load circuit 23 at all times can be set to an extremely small value (1/10 to 1/100 of the conventional value).

 FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

This embodiment is provided with a discharge circuit 3 _A output terminal T _O · ground potential terminal between the circuit to the constant current load circuit 23 than can flow sufficiently large current constant current load circuit 32 of the.

When a field effect transistor is used as the switch circuit 31, the constant current load circuit 32 can include the function of the constant current load circuit 32 in the switch circuit 31 by switching its gate bias voltage. This has the effect of limiting the discharge current flowing through the circuit 31 and preventing the occurrence of noise.

〔The invention's effect〕

As described above, according to the present invention, the sample and hold circuit is a circuit that releases the output signal during the sampling period of the input signal, and the input terminal and the output terminal of the buffer circuit are short-circuited to the ground potential terminal during the release period of the output signal. Alternatively, a discharge circuit connected with low impedance is provided, and the capacitive load circuit is discharged through the discharge circuit during the release period of the output signal of the sample and hold circuit, and output according to the output signal of the sample and hold circuit during periods other than this release period By charging the capacitive load circuit through the transistor, the current drive capability of the output transistor can be increased to increase the charge current of the capacitive load circuit, and the discharge of the capacitive load circuit can be performed through the discharge circuit. Therefore, the output signal to the capacitive load circuit can be quickly stabilized at a predetermined value, One, it is possible to significantly reduce the idling current flowing through the idling current and always the constant current load circuit flowing through the output transistor during the steady state, there is an effect that can greatly reduce power consumption. In particular, the effect is remarkable when a large number of output driver circuits are used as in an active matrix liquid crystal driver.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram of each signal for explaining the operation of the embodiment shown in FIG. 3, FIG. 3 is a circuit diagram showing a second embodiment of the present invention,
FIG. 4 is a circuit diagram showing an example of a conventional output driver circuit,
FIG. 5 is a waveform chart of signals at various parts for explaining the operation of the output driver circuit shown in FIG. 1,1 _A …… Sample hold circuit, 2,2 _A …… Buffer circuit, 3,3 _A …… Discharge circuit, 10 …… Capacitive load circuit, 21 ……
Amplifier, 22: Output transistor, 23, 23 _A: Constant current load circuit, 31: Switch circuit, 32: Constant current load circuit.

Claims (1)

(57) [Claims] An output signal which is already held at a leading edge of a hold control pulse is released, an input signal is sampled by a sampling pulse and internally held,
A sample and hold circuit for newly holding and outputting a signal internally held at the trailing edge of the hold control pulse, an amplifier for inputting an output signal of the sample and hold circuit to a non-inverting input terminal, and an output signal of the amplifier. An output transistor connected to the gate and a source (or drain) connected to an output terminal to which a capacitive load circuit is connected, and an inverting input terminal of the amplifier, and a constant current flowing between the output terminal and the ground potential terminal. And a current load circuit,
A buffer circuit for amplifying an output signal of the sample and hold circuit and transmitting the amplified signal to the output terminal; and a buffer circuit having a pulse width narrower than the hold control pulse and a timing between a leading edge and a trailing edge of the hold control pulse. An output driver circuit, comprising: a switch circuit that is turned on by a discharge control pulse; and a discharge circuit that connects an input terminal and an output terminal of the buffer circuit to the ground potential terminal with a predetermined impedance.