JP2579346B2 - Semiconductor nonvolatile storage element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used as a storage element for holding program data incorporated in a programmable logic device, etc., and converts a LOW and HIGH level digital signal into a small area. The present invention relates to a semiconductor nonvolatile memory element that can be held by a non-volatile memory device.

[Prior art] Conventionally, PLDs have been used as integrated circuits (ICs) that allow a user to realize a desired circuit at a high integration level by programming.
(Programmable logic devices) and the like are known. Since these programmable integrated circuits need to hold program data, etc., EPROM (erasable programmable
A circuit using read-only memory is built in. An example is IEEE JOURNAL OF SOLID-STAT
E CIRCUITS, VOL.SC-21, NO.5, OCTOBER1986 P766 ~ P77
3 stated.

FIG. 5 is a circuit diagram of a conventional example of an EPROM holding data for programming a selector used in the PLD. In the selector 1, the input 4a is selected as the output 3 when the program terminal 2 is at the low level, and the input 4b is selected as the output 3 when the program terminal 2 is at the high level. The field effect transistor 13 having a floating gate and a control gate, which is a cell of the EPROM, becomes inactive when a high voltage of 12 V or more is applied to the word line 5 and the bit line 6 (hereinafter referred to as writing). Therefore, when the field effect transistor 13 is written, even if the word line 5 goes high, the node 16 goes low due to the circular connection of the inverter 14a with the enhanced pull-down capability and the inverter 14b with the enhanced pull-up capability. Is held as data. The above written state can be returned to the state before writing by irradiating the field effect transistor 13 with ultraviolet rays (this is hereinafter referred to as erasing). Field effect transistor
If 13 is not written or erased, word line 5 goes high.
Then, since the node 15 is pulled down by the field-effect transistor 13, the node 16 holds a HIGH-level signal as data. Since the node 16 is connected to the program terminal 2 of the selector 1, the selector can be programmed depending on whether or not the field effect transistor 13 is written.

[Problem to be Solved by the Invention] However, the program / program in the above-described conventional technique is
Since the data holding circuit uses two inverters composed of multiple elements in addition to the EPROM cell transistor, it requires a large area for it, and the storage element and the integrated PLD etc. that contain it There is a problem that the degree is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a nonvolatile memory element which can be realized with a small number of elements and therefore with a small area on a chip.

[Means for Solving the Problems] To achieve the above object, a nonvolatile memory element according to the present invention comprises a programmable logic device having a floating gate and a control gate connected to a first word line. A first field-effect transistor having a source grounded, a control gate connected to a floating gate and a second word line, and having a source grounded for data writing and a power supply voltage switchable for data reading. A second field-effect transistor of the same type as the first field-effect transistor connected to the drain of the first field-effect transistor and having a drain connected to a drain of the first field-effect transistor; It is connected between the bit line and the node connecting the cell drains, A circuit serving as a switch that is turned on when data is written, wherein the node is a node from which the 1-bit data is read and connected to a programming element of a programmable logic device.

[Operation] According to the present invention, a first field effect transistor (hereinafter referred to as an FET) constituting a memory cell is used as a pull-down FET and a second FET is used as a pull-up FET. Or one of them according to the instruction of the second word line.
Write to the FET to cause it to remain inactive. At this time, if the pull-down first FET is set to the inactive state, when an instruction is given to both the first and second word lines for reading, the pull-up of the active second FET is performed. When the HIGH level signal is read out by the action and the second FET for pull-up is made inactive,
Similarly, a LOW level signal can be read by the pull-down operation of the first FET. That is, the memory cell holds 1-bit data by the writing. The circuit serving as a switch separates the bit line for writing and the output line from the node, and individually outputs the output of the memory cell to the PL.
Output to the D programming element. As described above, the number of constituent elements of the PLD nonvolatile storage element is minimized, and the area required for element isolation when forming each FET is minimized by using the same type of the first FET and the second FET. By doing so, high integration of the PLD is enabled.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. This embodiment shows an example of a circuit including one memory cell holding data for a user to program a programmable selector used in a PLD. The user-programmable selector 1 is configured such that when the program terminal 2 is at the low level, the input 4a is selected as the output 3 and when the program terminal 2 is at the high level, the input 4b is selected as the output 3. I have. 5a is the first word line,
5b is a second word line, 6 is a bit line, 7 is a power supply voltage when reading data written to the ground side when writing data, an output enable line connected to a switchable circuit, and 8 is a writing voltage when writing data. A write enable line 9 for applying a write voltage to a memory cell at the time of data writing and a node for normally reading out the written data; and 10, a drain having a gate connected to the write enable line 8 and a source connected to the bit line 6 for a source. Is a switch composed of an N-channel MOSFET connected to the node 9. An N-type MOSFET 11a has a floating gate and a control gate connected to the first word line 5a, and has a source grounded (hereinafter referred to as FAMOSFET).
The first FAMOSFET 11b has a floating gate and a control gate connected to the second word line 5b, has a source connected to the output enable line 7, and has a drain connected to the first enable line.
A second N-type FAMOSFET connected to the drain of the FAMOSFET. The two first and second FAMOSFETs constitute a memory cell 12 for holding 1-bit data, and a node connecting the two drains. Is the node 9 described above.

 The operation of the embodiment configured as described above will be described.

FIG. 2 is a timing chart of signals necessary for writing high-level data to a memory cell. When writing high-level data to the memory cell 12 in FIG. 1,
First, a write voltage Vpp is applied to the write enable line 8, and a switch (N-channel MOSFET) 10 is turned on.
Next, the write voltage is applied to the first word line 5a and the bit line 6.
When Vpp is applied, hot electrons are injected into the floating gate of the first FAMOSFET 11a, the hot electrons are retained, and the first FAMOSFET 11a becomes inactive. Needless to say, before writing, it is necessary to remove the charge of the floating gates of the first and second FAMOSFETs 11a and 11b as a photocurrent by irradiating ultraviolet rays or the like and keep the active state (erase). In this case, the write voltage is not applied to the second word line 5b, and the output enable line 7 is set to the ground side (OV). Therefore, the second FAMOSFET 11b remains in an active state even after the writing.

FIG. 3 is a timing chart of signals necessary for writing a LOW level to a memory cell. To write LOW level data in the memory cell 12 of FIG. 1 in the opposite manner, first, a write voltage Vpp is applied to the write enable line 8, and the switch (N-channel MOSFET) 10 is turned on. Next, the write voltage Vpp is applied to the second word line 5b and the bit line 6, and OV on the ground side is applied to the output enable line 7 to make the FAMOSFET 11b inactive. At this time, no write voltage is applied to the first word line 5a. Therefore, the first FAMOSFET 11a remains in the active state even after the writing.

FIG. 4 is a timing chart of reading data written in the memory cell as described above. In FIG. 1, OV (ground side) is applied to a write enable line 8 to turn off a switch (N-channel MOSFET) 10, and a first word line 5a, a second word line 5b, and an output enable line 7 are applied to each of the first and second word lines 5a, 5b. When the power supply voltage Vdd is applied, the memory cell 12
If high level data is written to
Since ET11a is inactive and FAMOSFET11b is active,
Node 9 is pulled up by FAMOSFET 11b to provide a high level signal to program terminal 2 of programmable selector 1. If the LOW level data is written in the memory cell 12, the FAMOSFET 11b is inactive and the FAMOSFET 11a is active. Therefore, the node 9 is pulled down by the FAMOSFET 11a and the LOW is applied to the program terminal 2 of the programmable selector 1. Give a level signal.

As described above, the memory cell of this embodiment can hold high-level data or low-level data, that is, 1-bit data. Moreover, the circuit can be composed of two FAMOSFETs and one switching MOSFET, which constitute a memory cell, and an extremely small number of elements. Is possible. Here, in this embodiment, since two FAMOSFETs constituting the memory cell are of the same type, an extra area required for element isolation when forming different types (N-type and P-type) of FAMOSFETs on the same substrate. Becomes unnecessary, and higher integration is possible.

In the above-described embodiment, an N-type FAMOSFET is used in order to make the voltage of the control gate and the like positive and easy to configure. However, it is obvious that a P-type FAMOSFET can also be used. In addition, a plurality of memory cells are provided, and a plurality of memory cells are connected to each of a plurality of bit lines via a switch, and a plurality of memory cells are also connected to a plurality of first and second word lines, respectively. It is also possible to form an array. As described above, the present invention can be applied variously according to the gist thereof and can take various embodiments.

[Effects of the Invention] As is apparent from the above description, according to the nonvolatile memory element of the present invention, the nonvolatile memory element has the same function as the nonvolatile memory element used in the conventional PLD and the like, without using an inverter. A memory cell composed of two FAMOSFETs and a circuit serving as a switch can constitute one non-volatile memory element, so that the area can be saved by that much.
Since the two FAMOSFETs are of the same type, the area required for element isolation can be reduced, and high integration can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a nonvolatile memory element according to the present invention, FIG. 2 is a timing chart for writing high-level data, FIG. 3 is a timing chart for writing low-level data, FIG. 4 is a timing diagram of data reading, and FIG. 5 is a circuit diagram of an EPROM which is a conventional nonvolatile memory element. 5a ... first word line, 5b ... second word line, 6 ...
Bit line, 7 ... output enable line, 8 ... write enable line, 9 ... node, 10 ... switch, 11a ... first FAMOSFET, 11b ... second FAMOSFET, 12 ... memory cell.

Claims (1)

(57) [Claims] 1. A programmable logic device, comprising: a first field-effect transistor having a floating gate and a control gate connected to a first word line and having a source grounded; and a floating gate and a second word line connected to a first word line. A first field-effect transistor having a control gate connected thereto, a source connected to a circuit which can be switched to a ground when writing data, and a power supply voltage when reading data, and a drain connected to a drain of the first field-effect transistor; A second field-effect transistor of the same type as the transistor; and a memory cell that holds 1-bit data. The memory cell is connected between a node connecting the drains of the memory cell and a bit line, and is turned on when writing data. A circuit serving as a switch; The semiconductor nonvolatile memory device characterized by connecting the programming device of a programmable logic device as bits of data read out node.