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JP2579498B2 - Wafer processing equipment - Google Patents
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JP2579498B2 - Wafer processing equipment - Google Patents

Wafer processing equipment

Info

Publication number
JP2579498B2
JP2579498B2 JP23233187A JP23233187A JP2579498B2 JP 2579498 B2 JP2579498 B2 JP 2579498B2 JP 23233187 A JP23233187 A JP 23233187A JP 23233187 A JP23233187 A JP 23233187A JP 2579498 B2 JP2579498 B2 JP 2579498B2
Authority
JP
Japan
Prior art keywords
wafer
chip
plate
cut
cutting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23233187A
Other languages
Japanese (ja)
Other versions
JPS6475207A (en
Inventor
勝則 蓬田
佳郎 古矢
輝幸 岩田
年光 向坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Fujitsu Miyagi Electronics Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Fujitsu Miyagi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd, Fujitsu Miyagi Electronics Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP23233187A priority Critical patent/JP2579498B2/en
Publication of JPS6475207A publication Critical patent/JPS6475207A/en
Application granted granted Critical
Publication of JP2579498B2 publication Critical patent/JP2579498B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Dicing (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)

Description

【発明の詳細な説明】 〔概要〕 ウエハからチップを損傷することなく切り分けるウエ
ハ処理方法に関し、 ウエハ上に形成された半導体チップを正確に切り分け
ると共に、各チップを傷つけることなく確実に取り分け
ることを目的とし、 ウエハを矩形のチップに切り分けるウエハ処理方法に
おいて、ウエハを上下方向から上面板と下面板で挟んで
固定する工程と、前記上面板を介してウエハを格子状に
切り分ける工程と、前記下面板を介して先に切り分けた
方向と直交する方向に更にウエハを格子状に切り分ける
工程とを含み構成する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] A wafer processing method for separating chips from a wafer without damaging the semiconductor chip formed on the wafer accurately and separating each chip without damage. In a wafer processing method for cutting a wafer into rectangular chips, a step of fixing the wafer by vertically sandwiching the wafer between an upper plate and a lower plate, a step of cutting the wafer into a lattice via the upper plate, and a process of cutting the lower plate And a step of further dividing the wafer into a lattice in a direction perpendicular to the direction previously divided through the wafer.

〔産業上の利用分野〕[Industrial applications]

本発明はウエハからチップを損傷することなく切り分
けるウエハ処理方法に関する。
The present invention relates to a wafer processing method for separating chips from a wafer without damaging the chips.

〔従来の技術〕[Conventional technology]

第5図の(a)(b)は従来のウエハ処理方法説明図
である。図中、31はウエハ、32はチップ、33は台、34は
粘着テープである。
FIGS. 5A and 5B are explanatory views of a conventional wafer processing method. In the figure, 31 is a wafer, 32 is a chip, 33 is a table, and 34 is an adhesive tape.

従来のウエハ処理方法は、第5図(a)に示す如く、
台33上に粘着テープ34を固定し、その上にウエハ31を矢
印D方向へ移動させてウエハ31を固定する。そして同図
(b)の如く、各チップ32ごとにフルカットされて切り
分けられていた。切り分けた後のウエハ断面を次の第6
図各図に示す。
The conventional wafer processing method, as shown in FIG.
An adhesive tape 34 is fixed on the table 33, and the wafer 31 is moved thereon in the direction of arrow D to fix the wafer 31 thereon. Then, as shown in FIG. 3B, each chip 32 was cut by full cutting. The cross-section of the wafer after the cutting is described in the following sixth section.
It is shown in the figures.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

第6図の(a)(b)(c)は従来の問題点を示すウ
エハ断面図である。図中、32はチップ、34は粘着テー
プ、35はピン、36はエアピンユニット、37は切溝であ
る。
(A), (b) and (c) of FIG. 6 are cross-sectional views of a wafer showing a conventional problem. In the figure, 32 is a chip, 34 is an adhesive tape, 35 is a pin, 36 is an air pin unit, and 37 is a cut groove.

しかし上記粘着テープを使った従来の方法は、第6図
(a)に示す如く、フルカットされた後のウエハ断面状
態から各チップ32がウエハから切り離される。その際、
第6図(b)の如く、ピン35で下からチップ32が突き上
げられるが、粘着テープ34の粘着度にバラツキがあるた
め弱い部分が先に剥がれてチップ32が傾いて持ち上げら
れ、図中Eで示す部分でカケが発生するという問題があ
る。
However, in the conventional method using the above-mentioned adhesive tape, as shown in FIG. 6A, each chip 32 is separated from the wafer from the cross-sectional state of the wafer after full cutting. that time,
As shown in FIG. 6 (b), the chip 32 is pushed up from below by the pin 35. However, since the adhesiveness of the adhesive tape 34 varies, the weak portion is peeled off first and the chip 32 is tilted and lifted. There is a problem that chipping occurs in the portion indicated by.

また同図(c)の如く、エアピンユニット36で吸い上
げる際に、チップ32が粘着テープ34から完全に剥がれき
っていないとチップ32が斜めに吸い上げられ、エアピン
ユニット36と図中Gの部分で接触したり、隣のチップ32
と図中Fの部分で接触して傷がつくという問題があっ
た。
As shown in FIG. 3C, when the chip 32 is not completely peeled off from the adhesive tape 34 when sucked by the air pin unit 36, the chip 32 is sucked obliquely, and the air pin unit 36 and the portion G in the figure are drawn. Or touch with the next chip 32
And contact at the portion F in FIG.

さらに粘着テープ34は、ウエハの背面に使われた金を
短時間で変色させたり、チップ32を持ち上げる際の突き
上げのタイミングが悪いとチップが飛んだり、コレット
内での位置ずれが生じるなどの問題があった。
In addition, the adhesive tape 34 may cause problems such as discoloring of the gold used on the back of the wafer in a short time, chip flying, and misalignment within the collet if the timing of lifting the chip 32 is poor. was there.

そこで本発明は、ウエハ上に形成された半導体チップ
を正確に切り分けると共に、各チップを傷つけることな
く確実に取り分けることを目的とする。
Accordingly, it is an object of the present invention to accurately cut a semiconductor chip formed on a wafer and to surely separate each chip without damaging it.

〔問題点を解決するための手段〕[Means for solving the problem]

上記問題点は、ウエハを矩形のチップに切り分けるウ
エハ処理方法において、ウエハを上下方向から上面板と
下面板で挟んで固定する工程と、前記上面板を介してウ
エハを格子状に切り分ける工程と、前記下面板を介して
先に切り分けた方向と直交する方向に更にウエハを格子
状に切り分ける工程とを含むことを特徴とするウエハ処
理方法によって達成される。
The above problem is that, in a wafer processing method for cutting a wafer into rectangular chips, a step of fixing the wafer by sandwiching the wafer between upper and lower plates from above and below, and a step of cutting the wafer into a lattice via the upper surface plate, A step of further cutting the wafer into a lattice in a direction orthogonal to the direction of the first cut through the lower surface plate.

〔作用〕[Action]

すなわち本発明は、ウエハを上下方向から上面板と下
面板で挟んで固定し、上面板を介してウエハを格子状に
切り分け、更に下面板を介して先に切り分けた方向と直
交する方向にウエハを格子状に切り分けることによっ
て、粘着テープを使わずにウエハを固定して切り分けら
れ、また切り離しも容易に行うことができる。
That is, according to the present invention, the wafer is fixed by sandwiching the wafer from above and below with the upper plate and the lower plate, the wafer is cut into a lattice shape through the upper plate, and further, the wafer is cut in a direction orthogonal to the previously cut direction through the lower plate. Is cut in a lattice shape, the wafer can be fixed and cut without using an adhesive tape, and the separation can be easily performed.

これによってウエハからチップを正確に切り分けるこ
とができ、また各チップを傷つけることなく確実に取り
分けることができるため、信頼性の高い半導体チップの
供給が可能になった。
As a result, chips can be accurately separated from the wafer, and each chip can be reliably separated without damaging the chips, so that highly reliable supply of semiconductor chips has become possible.

〔実施例〕〔Example〕

以下、本発明を図示の一実施例により具体的に説明す
る。
Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the drawings.

先ず第1図の(a)〜(e)は本発明の実施例1の処
理工程説明図、第2図は実施例2を説明する斜視図で、
その(a)は使用状態図、(b)は持ち運び状態図、第
3図は実施例2の上面板の図で、その(a)は斜視図、
(b)は(a)のB部分拡大図、(c)は(b)のC部
分拡大図、第4図は実施例3の下面板の斜視図である。
First, (a) to (e) of FIG. 1 are explanatory views of the processing steps of Embodiment 1 of the present invention, and FIG. 2 is a perspective view for explaining Embodiment 2.
(A) is a use state diagram, (b) is a carry state diagram, FIG. 3 is a diagram of the top plate of the second embodiment, (a) is a perspective view,
(B) is an enlarged view of a part B of (a), (c) is an enlarged view of a part C of (b), and FIG. 4 is a perspective view of a lower plate of the third embodiment.

図において、11はウエハ、12はチップ、13aは上面
板、13bは下面板、14は切溝、15は止め金、16は凹部、1
7は凸部、18a,18bは位置合わせ部、19はゴムシート(チ
ップの押さえ部)、20は突き上げ部である。
In the figure, 11 is a wafer, 12 is a chip, 13a is an upper surface plate, 13b is a lower surface plate, 14 is a kerf, 15 is a stopper, 16 is a recess, 1
7 is a convex portion, 18a and 18b are alignment portions, 19 is a rubber sheet (a pressing portion for a chip), and 20 is a push-up portion.

実施例1 第1図(a)に示す如く、ウエハ11を上下方向からウ
エハより大きい透明なアクリル樹脂板または厚紙などで
できた上面板13aと下面板13bで挟み込み、第1図(b)
の状態で固定する。次に第1図(c)に示すように、正
確に位置合わせをした後、上面板13aを介してウエハを
図示省略の専用のカッターを使いチップ幅で格子状に切
り分ける。上面板13aは全部切らないで端を残すが、中
のウエハは全て切り離された状態にする。更に第1図
(d)の如く、ウエハを固定した状態で上下を逆にし、
下面板13bを介して先に切り分けた方向と直交する方向
にウエハを格子状に切り分ける。下面板13bの場合も全
部切らないで端は残し、中のウエハは全て切り離された
状態にする。続いて第1図(e)の如く、板を外してチ
ップ12を取り分ける。
Example 1 As shown in FIG. 1 (a), a wafer 11 is sandwiched from above and below by an upper plate 13a and a lower plate 13b made of a transparent acrylic resin plate or cardboard which is larger than the wafer.
Fix in the state of. Next, as shown in FIG. 1 (c), after accurate positioning, the wafer is cut into a lattice shape with a chip width using a dedicated cutter (not shown) via the upper plate 13a. The upper surface plate 13a is not cut off but leaves an edge, but the wafers inside are all cut off. Further, as shown in FIG. 1 (d), the wafer is fixed upside down with the wafer fixed.
The wafer is cut into a lattice shape in a direction perpendicular to the direction cut earlier through the lower plate 13b. Also in the case of the lower surface plate 13b, the edges are left without cutting all, and the wafers inside are all cut off. Subsequently, as shown in FIG. 1 (e), the plate is removed and chips 12 are separated.

このようにすると上面板13aと下面板13bは切り分けら
れることなく、間に挟まれたウエハ11のみを矩形のチッ
プ12に確実に切り分けることができる。ウエハ11は上下
方向から板(13a,13b)で挟まれて固定されているの
で、ウエハ11の切り分け時にずれることがなく、またチ
ップ12の取り分け時には上下の板を離すだけで容易に取
り出しが可能になる。また従来のように粘着テープを使
わずにウエハを固定してフルカットができるので、粘着
テープによる種々の問題が生じない。
In this way, the upper plate 13a and the lower plate 13b are not cut, and only the wafer 11 sandwiched therebetween can be cut into rectangular chips 12 without fail. Since the wafer 11 is sandwiched and fixed from above and below by the plates (13a, 13b), it does not shift when the wafer 11 is cut, and when the chips 12 are separated, it can be easily taken out just by separating the upper and lower plates. become. Further, since the wafer can be fixed and full cut can be performed without using an adhesive tape as in the related art, various problems due to the adhesive tape do not occur.

実施例2 実施例2では、第2図各図に示す如く、上面板13aと
下面板13bにはウエハを切り分けるための切溝14が予め
切ってあるものを使用した。この切溝14はチップの位置
および大きさに合わせて正確に切ってあるので、カッタ
ーを切溝14に合わせるだけで位置決めができる。
Example 2 In Example 2, as shown in each of FIGS. 2A and 2B, the upper surface plate 13a and the lower surface plate 13b used had a cutting groove 14 for cutting a wafer in advance. Since the incision 14 is accurately cut in accordance with the position and size of the chip, positioning can be performed only by aligning the cutter with the incision 14.

第2図(a)の如く、下面板13bにはウエハ形状に合
わせた凹部16が形成され、ここに矢印Aで示す如くウエ
ハを挿入し、下面板13bの凹部16の形状に対応した上面
板13aの凸部17を挿入することによってウエハを固定す
る。上面板13aと下面板13bおよびウエハとの位置合わせ
は位置合わせ部18a,18bで行う。第2図(b)はこの上
面板13a、下面板13bを一緒にして持ち運ぶ際の状態を図
示したもので、両方の板を4ヵ所程度の止め金15で固定
することによって安全かつ容易に持ち運びができるよう
にしたものである。
As shown in FIG. 2 (a), a concave portion 16 is formed in the lower surface plate 13b so as to conform to the shape of the wafer. The wafer is fixed by inserting the convex portion 17 of 13a. The upper plate 13a, the lower plate 13b, and the wafer are aligned by the alignment units 18a, 18b. FIG. 2 (b) shows a state in which the upper plate 13a and the lower plate 13b are carried together, and the two plates are securely and easily carried by fixing them with the stoppers 15 at about four places. Is made possible.

第3図各図は、ウエハの素子形成面に直接板を押し付
けると表面に傷をつける恐れがあるので、ウエハ表面に
接する板(ここでは上面板13a)側に柔軟性のあるゴム
シート19などを挟んで保護したものである。第3図
(a)の上面板13aのB部分を拡大したのが同図(b)
である。チップの幅に合わせて切溝14が切られている様
子が分かる。さらにこの図中のC部分を拡大したのが同
図(c)である。各チップの押さえ部に該当する板部分
の周囲は矩形にゴムシート19が貼りつけてある。このた
めチップの表面が保護されて傷の発生が防止できると共
に、ゴムシートの摩擦によってウエハのずれを防止する
こともできる。
FIG. 3 shows that, if a plate is pressed directly against the element forming surface of the wafer, the surface may be damaged. Therefore, a flexible rubber sheet 19 or the like is provided on the plate (here, the upper plate 13a) in contact with the wafer surface. It is protected by sandwiching it. FIG. 3B is an enlarged view of a portion B of the upper surface plate 13a in FIG. 3A.
It is. It can be seen that the kerf 14 is cut according to the width of the chip. FIG. 3C is an enlarged view of a portion C in FIG. A rubber sheet 19 is adhered in a rectangular shape around a plate portion corresponding to a holding portion of each chip. For this reason, the surface of the chip is protected, so that scratches can be prevented from occurring, and the wafer can be prevented from being displaced by friction of the rubber sheet.

実施例3 第4図に示す如く、ウエハ11を各チップ12に切り分け
て図示省略の上面板を外す際に、上面板にチップ12が付
着する可能性も考えられるため、下面板13bの各チップ
に該当する部分に吸引用の穴を開けておき、真空で引い
てから上面板を外すようにすることもできる。
Third Embodiment As shown in FIG. 4, when the wafer 11 is cut into chips 12 and the upper plate (not shown) is removed, the chips 12 may adhere to the upper plate. A hole for suction may be formed in a portion corresponding to the above, and the upper plate may be removed after vacuuming.

〔発明の効果〕〔The invention's effect〕

以上のように本発明によれば、ウエハ上に形成された
半導体チップを正確に切り分けることができると共に、
各チップを傷つけることなく確実に取り分けることが可
能となった。
As described above, according to the present invention, semiconductor chips formed on a wafer can be accurately separated,
The chips can be reliably separated without damaging each chip.

【図面の簡単な説明】[Brief description of the drawings]

第1図の(a)〜(e)は本発明の実施例1の処理工程
説明図、 第2図は実施例2を説明する斜視図で、その(a)は使
用状態図、(b)は持ち運び状態図、 第3図は実施例2の上面板の図で、その(a)は斜視
図、(b)は(a)のB部分拡大図、(c)は(b)の
C部分拡大図、 第4図は実施例3の下面板の斜視図 第5図の(a)(b)は従来のウエハ処理方法説明図、 第6図の(a)(b)(c)は従来の問題点を示すウエ
ハ断面図である。 図において、 11はウエハ、12はチップ、13aは上面板、13bは下面板、
14は切溝、15は止め金、16は凹部、17は凸部、18a,18b
は位置合わせ部、19はゴムシート(チップの押さえ
部)、20は突き上げ部である。
1 (a) to 1 (e) are explanatory views of processing steps according to Embodiment 1 of the present invention, FIG. 2 is a perspective view illustrating Embodiment 2, and FIG. FIG. 3 is a diagram of the top plate of the second embodiment, FIG. 3 (a) is a perspective view, FIG. 3 (b) is an enlarged view of a portion B of FIG. 3 (a), and FIG. 3 (c) is a portion C of FIG. 4 is an enlarged view, FIG. 4 is a perspective view of a lower plate of the third embodiment, FIGS. 5 (a) and (b) are explanatory views of a conventional wafer processing method, and FIGS. 6 (a), (b) and (c) are conventional. FIG. 4 is a cross-sectional view of a wafer showing a problem of (1). In the figure, 11 is a wafer, 12 is a chip, 13a is an upper plate, 13b is a lower plate,
14 is a kerf, 15 is a stopper, 16 is a concave, 17 is a convex, 18a, 18b
Denotes a positioning portion, 19 denotes a rubber sheet (a pressing portion for a chip), and 20 denotes a push-up portion.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 古矢 佳郎 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 岩田 輝幸 鹿児島県薩摩郡入来町副田5950番地 株 式会社九州富士通エレクトロニクス内 (72)発明者 向坂 年光 宮城県柴田郡村田町大字村田字西ケ丘1 番地の1 株式会社富士通宮城エレクト ロニクス内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshiro Koya 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Teruyuki Iwata 5950 Fueda, Iriki-cho, Satsuma-gun, Kagoshima Kyushu Fujitsu Limited Inside the electronics (72) Inventor Toshimitsu Kosaka 1-2-1 Nishigaoka, Murata-cho, Murata-cho, Shibata-gun, Miyagi 1 Fujitsu Miyagi Electronics Co., Ltd.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ウエハ(11)を矩形のチップ(12)に切り
分けるウエハ処理方法において、 ウエハ(11)を上下方向から上面板(13a)と下面板(1
3b)で挟んで固定する工程と、 前記上面板(13a)を介してウエハを格子状に切り分け
る工程と、 前記下面板(13b)を介して先に切り分けた方向と直交
する方向に更にウエハを格子状に切り分ける工程とを含
むことを特徴とするウエハ処理方法。
1. A wafer processing method for cutting a wafer (11) into rectangular chips (12), wherein the wafer (11) is vertically cut from an upper plate (13a) and a lower plate (1).
3b) sandwiching and fixing the wafer; cutting the wafer into a grid via the upper plate (13a); further cutting the wafer in a direction orthogonal to the direction previously cut via the lower plate (13b). Cutting the wafer into a lattice.
JP23233187A 1987-09-18 1987-09-18 Wafer processing equipment Expired - Fee Related JP2579498B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23233187A JP2579498B2 (en) 1987-09-18 1987-09-18 Wafer processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23233187A JP2579498B2 (en) 1987-09-18 1987-09-18 Wafer processing equipment

Publications (2)

Publication Number Publication Date
JPS6475207A JPS6475207A (en) 1989-03-20
JP2579498B2 true JP2579498B2 (en) 1997-02-05

Family

ID=16937524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23233187A Expired - Fee Related JP2579498B2 (en) 1987-09-18 1987-09-18 Wafer processing equipment

Country Status (1)

Country Link
JP (1) JP2579498B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2707831B2 (en) * 1990-11-22 1998-02-04 富士電機株式会社 Method for manufacturing semiconductor device
GB2390262B (en) * 2002-06-24 2005-11-16 Motorola Inc Method and apparatus for fault detection in a radio transceiver

Also Published As

Publication number Publication date
JPS6475207A (en) 1989-03-20

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