JP2579999B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a technique which is particularly effective when applied to the formation of a semiconductor integrated circuit. More specifically, the present invention relates to a technique which is effective when used for manufacturing a high-speed bipolar transistor. It is about technology.

[Conventional technology] SEPT (Selective Etching of Polysilicon Technog)
y) SST (Super Self-aligned Process Te)
chnology).
MIS (Metal Insulator Semiconduct
or) A capacitor having a structure is formed. Such an SST bipolar transistor was published in April 1986 by IEEE.
`` TRNSACTIONS ON ELECTRON DEVICES '' Vol.ED-33, No4
p526 to p531 and JP-B-55-27469. The outline is as follows.

FIG. 4 shows a bipolar transistor manufactured by SEPT, where E is the emitter, B is the base, C
Represents a collector, respectively.

In this bipolar transistor, a base contact hole is formed inside the element region, and a base extraction electrode 2 that contacts a graft base 1a constituting a part of the base region 1 is formed of an SiO ₂ film 3 and a Si ₃ N ₄ film. 4 faces the collector region 5. As a result, as shown in FIG. 5, the base extraction electrode 2 and the insulating film (SiO ₂ film 3, Si ₃ N ₄ film 4)
A capacitor having an MIS structure is formed between the capacitor and the collector region 5. In FIG. 4, reference numeral 6 denotes an emitter region.

[Problem to be Solved by the Invention] Meanwhile, the collector-base capacitance (Cjc) in the bipolar transistor as described above is represented by the sum of the intrinsic base capacitance and the MIS capacitance of the graft base capacitance,
Of these, the graft-base capacitance and the MIS capacitance occupy the majority of the collector-base capacitance, which hinders the speeding up of the bipolar transistor. Therefore,
For example, it is desired to reduce the MIS capacitance and increase the speed of the bipolar transistor. However, in the MIS capacitor, the thickness of the depletion layer formed immediately below the insulating film greatly depends on the thickness of the insulating film. It was difficult to reduce the capacity.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the collector-base capacitance and increase the speed of a bipolar transistor.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows. In the method for manufacturing a semiconductor device according to the present invention, each element region on the main surface of the semiconductor substrate of the first conductivity type is separated by an insulating film for element isolation, and a silicon oxide film, a silicon nitride film, A crystalline silicon film, a silicon oxide film, and a silicon nitride film are sequentially formed, and a photoresist and a film patterned thereon are selectively used as a mask to selectively etch a silicon nitride film thereunder.
Using the photoresist film and the silicon nitride film immediately below the mask as a mask, ion implantation of a second conductivity type impurity is performed on the polycrystalline silicon film and the main surface of the semiconductor substrate, and the silicon nitride film is again used as a mask, The silicon oxide film is isotropically etched, the silicon oxide film is side-etched, then the silicon nitride film used as a mask is removed, and the side-etched silicon oxide film is used as a mask to form non-doped polycrystalline silicon. An etching for selectively removing the film is performed on the polycrystalline silicon film immediately below, leaving the doped polycrystalline silicon film and the non-doped polycrystalline silicon film immediately below the mask, and removing the non-doped polycrystalline silicon film and the doped polycrystalline silicon film. After etching the silicon nitride film immediately below as a mask, the remaining non-doped polycrystalline silicon film is selectively removed, and Using the silicon nitride film as a mask, the silicon oxide film underneath is selectively etched away to partially expose the main surface of the semiconductor substrate, a non-doped polycrystalline silicon film is deposited over the entire surface, and annealing is performed. A non-doped polycrystalline silicon film excluding the central portion of the silicon nitride film which is masked by the non-doped polycrystalline silicon film and becomes the opening of the emitter hole remaining by masking the non-doped polycrystalline silicon film is formed as a doped polycrystalline silicon film. Forming a graft base region with impurities diffused from the exposed main surface of the semiconductor substrate, selectively removing the non-doped polycrystalline silicon film which becomes the emitter hole opening, performing surface oxidation of the doped polycrystalline silicon film, After removing the portions of the silicon nitride film and the silicon oxide film that will become the emitter hole openings, a polycrystalline silicon film to be the emitter electrode is deposited. It is those that were.

[Operation] According to the present invention described above, the base and the emitter can be formed by self-alignment using side etching, and the base extraction electrode and the base region can be formed through the silicon oxide film and the silicon nitride film. Therefore, no MIS capacitor is formed, and the above-described object of reducing the collector-base capacitance and increasing the speed of the bipolar transistor is achieved.

Example An example of a semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a bipolar transistor according to the embodiment.

The bipolar transistor shown in the figure is a bipolar transistor manufactured by SEPT, where E is an emitter,
B represents a base and C represents a collector. In this bipolar transistor, the element region and the emitter region 11 are formed in a non-self-aligned manner. And
In this bipolar transistor, all or a part of the base contact hole is formed inside the element region, and
The base region 12 extends to the element isolation region. In other words, immediately below the SiO ₂ film 13 and the Si ₃ N ₄ film 14 constituting the insulating film of the MIS structure is the low-concentration semiconductor region 12 a constituting a part of the base region 12.
2a is connected to the graft base 12b. In the figure, reference numeral 24 represents a base extraction electrode.

Next, a method of manufacturing the bipolar transistor will be described with reference to FIGS. 1 and 2A to 2F.

First, an SiO ₂ film is formed on a P ^- type Si substrate 15 and then this Si
A hole of a pattern for a buried diffusion layer is formed at an appropriate position of the O film, and an N-type impurity such as arsenic (AS) or antimony (Sb) is thermally diffused using the SiO ₂ film as a mask to form an N ⁺ type buried layer. Layer
Form 16. Then, after removing the SiO ₂ film used as a mask, the N-type epitaxial layer 17 is entirely grown by an epitaxial growth method. Then, after oxidizing the surface of the epitaxial layer 17, Si ₃ N ₄ is CVD (Chemical Vap).
formed by or Deposition) method performs photoresist processing for isolation patterning, SiO ₂
/ Si ₃ N ₄ film is etched. And the remaining Si ₃ N ₄
The epitaxial layer 17 is etched using the film as a mask. Next, a P ⁺ type channel stopper for channel prevention
18 is formed through boron ion implantation annealing. After that, selective oxidation is performed to form an SiO ₂ film 13 for isolation. Here, although the SiO film 13 is formed by using the isoplanar method, it goes without saying that the SiO ₂ film 13 such as a CVD film may be formed by using a groove filling method or the like.

Hereinafter, description will be made focusing on the manufacture of the active region of the bipolar transistor.

After forming the isolation SiO ₂ film 13 as described above, the Si ₃ N ₄ film 14 and the non-doped polycrystalline Si ₁
9. An SiO ₂ film 20 and a Si ₃ N ₄ film 21 are sequentially formed, a photoresist is applied, and a photoresist film 22 having emitter information is formed on a portion to be an element region by a photolithography method.

Next, using the photoresist 22 as a mask, the Si ₃ N ₄ film 21 thereunder is selectively etched, and using the photoresist film 22 and the remaining Si ₃ N ₄ 21 as a mask, boron (B) is ion-implanted. And resist coating
After removing 22, annealing is performed. As a result, the outer portion of the mask is boron-doped polycrystalline Si19a (non-doped polycrystalline S19a).
The symbol 19a is used to distinguish it from i19), while the non-doped polycrystalline Si19 remains on the lower side of the mask. At the same time, a P ^- type semiconductor region 12a constituting a part of the base region 12 is formed in the epitaxial layer 17 by self-alignment at the same time, and the state shown in FIG. 2A is obtained.
In this case, the formation of the P ⁻ -type semiconductor region 12a is performed at a time in consideration of the energy of boron ion implantation, or by changing the energy and performing a plurality of steps.

Then, Si ₃ N ₄ of 21 the lower side by the wet etching of isotropic dry etching or hydrofluoric acid as a mask Si
The O ₂ film 20 is etched. At this time, side etching is performed as shown in FIG. Therefore, the self-aligned SiO ₂ film 20 slightly smaller than the Si ₃ N ₄ 21 used as the mask remains below the Si ₂ N ₄ film 21.

Then removed the Si ₃ N ₄ film 21 as a mask, by performing selective etching of the non-doped polycrystalline Si19 by hydrazine SiO ₂ film 20 of the remaining parts located thereunder as a mask, the lower Si ₃ some of the N ₄ film 14 is exposed,
The state shown in FIG.

Then, after removing the SiO ₂ film 20 used as a mask,
After etching the exposed Si ₃ N ₄ film 14 using the non-doped polycrystalline Si19 and the boron-doped polycrystalline Si19a as masks,
The non-doped polycrystalline Si19 used as a mask is removed with hydrazine or the like, and the state shown in FIG. 2D is obtained.

Next, the SiO ₂ film 13 is etched using the Si ₃ N ₄ film 14 as a mask, non-doped polycrystalline Si 23 is deposited, and annealing is performed. Then, diffusion from the boron-doped polycrystalline Si19a occurs, and the non-doped polycrystalline Si23 is changed to boron-doped Si23a except for the opening of the emitter hole. Then, after etching the non-doped polycrystalline Si23 using hydrazine, the boron-doped polycrystalline to become the base extraction electrode 24 (FIG. 1).
The Si19 and 23a are etched (FIG. 2 (E)).

After the surface oxidation of the boron-doped polycrystalline Si 23a, 19a, the Si ₃ N ₄ film 14 and the SiO film 13
Is etched. Thereafter, non-doped polycrystalline Si for an emitter electrode is deposited, and boron is ion-implanted to perform annealing. Thereby, base diffusion is performed, and base region 12 is formed. Next, arsenic is ion-implanted and annealed. As a result, the emitter is diffused, and a semiconductor region serving as the emitter region 11 is formed.

Thereafter, the emitter electrode 24 is formed by etching the polycrystalline Si.

In the above embodiment, the manufacturing process of the active region of the bipolar transistor is mainly described, and the process of forming the collector outlet connected to the N ⁺ type buried layer as the collector region is omitted. The N ⁺ semiconductor region serving as the mouth is located at an appropriate position in the process of the above embodiment,
SiO ₂ film 13 on the side of the device region by ion implantation etc.
It is formed so as to reach the N ⁺ type buried layer 16 with a space therebetween.

According to the bipolar transistor having the above structure, Si
Since the base extraction electrode 24 and the base region 12 face each other via the O ₂ film 13 and the Si ₃ N ₄ film 14, no MIS capacitor is formed, and an increase in the collector-base capacitance caused by the presence of the MIS capacitor On the other hand, a depletion layer is newly formed at the junction between the base region 12 and the epitaxial layer 17 (collector region) located below the insulating film constituting the MIS structure. Because,
When a reverse bias is applied to the low-concentration semiconductor region 12a, a depletion layer extends above and below the junction surface as shown by a broken line in FIG. 3, and the depletion layer is expanded as compared with the conventional MIS capacitor. , The capacitance is reduced, resulting in an overall reduction in the collector-base capacitance.

Further, according to the bipolar transistor having the above structure, since the low-concentration semiconductor region 12a is located outside the base contact hole, the low-concentration semiconductor region 12a does not affect the shallow junction of the intrinsic base, and the increase in the base resistance can be avoided.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor.

In the above, the base region 12 under the SiO ₂ film 13 and the Si ₃ N ₄ film 14 constituting the MIS structure is extended, but the surface concentration of the epitaxial layer 17 as the collector layer is reduced. Is also good. In this case, a similar effect can be obtained. The formation may be performed, for example, in the same manner as the above method.

FIGS. 6A, 6B, 6C, and 6D show an example of a transistor that can implement the present device structure. However, various planar layouts such as limiting the length of the base contact hole are also possible within the scope of the present invention.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the method of manufacturing a semiconductor device according to the present invention, the base is formed by self-alignment using side etching,
Since an emitter can be formed and the base extraction electrode and the base region face each other via the silicon oxide film and the silicon nitride film, no MIS capacitor is formed and the collector-base capacitance is reduced. As a result, the speed of the element can be increased.

Further, in the present invention, the base region may be limited to all or a part of the MIS region, or may be limited to a part of the element isolation.

[Brief description of the drawings]

1 is a longitudinal sectional view of an embodiment of a semiconductor device according to the present invention, FIGS. 2 (A) to 2 (F) are views showing a manufacturing process of the semiconductor device of FIG. 1, and FIG. 3 is a view of FIG. FIG. 4 is a longitudinal sectional view of a conventional semiconductor device, FIG. 5 is a diagram illustrating the operation of the semiconductor device of FIG. 4, and FIGS. 6 (a), (b), (c), and FIG. (D) is a layout diagram to which the present invention can be applied. 12: Base region, 12a: Low-concentration semiconductor region, 13: S
iO ₂ film, 14 ...... Si ₃ N ₄ film, 24 ...... base electrode.

Claims (1)

(57) [Claims] An element isolation insulating film is provided on a main surface of a semiconductor substrate of a first conductivity type to isolate each element region, and a silicon oxide film, a silicon nitride film, and a polycrystalline silicon are formed on a surface of the element region. A step of sequentially forming a film, a silicon oxide film, and a silicon nitride film; a step of patterning a photoresist film on the upper silicon nitride film; and masking the photoresist film to form a silicon nitride film immediately therebelow. Selectively etching; and ion-implanting a second conductivity type impurity into the polycrystalline silicon film and the semiconductor substrate main surface using the photoresist film and a silicon nitride film immediately below the photoresist film as a mask; Using the silicon nitride film again as a mask, isotropic etching is performed on the silicon oxide film immediately below, and after the silicon oxide film is side-etched, the silicon nitride film used as the mask is removed. Using the silicon oxide film on which the side etching has been performed as a mask, and performing etching for selectively removing the non-doped polycrystalline silicon film from the polycrystalline silicon film immediately below, so that the doped polycrystalline silicon film and the mask immediately below the mask are removed. After the step of leaving the non-doped polycrystalline silicon film, and etching the silicon nitride film immediately below using the non-doped polycrystalline silicon film and the doped polycrystalline silicon film as a mask, and selectively removing the remaining non-doped polycrystalline silicon film. Removing the silicon oxide film directly below using the silicon nitride film as a mask to partially expose the main surface of the semiconductor substrate; and depositing a non-doped polycrystalline silicon film over the entire surface. Annealing is performed, and by diffusion from the doped polycrystalline silicon film,
A non-doped polycrystalline silicon film excluding a central portion of the silicon nitride film which becomes an opening portion of the emitter hole remaining by being masked by the non-doped polycrystalline silicon film is used as a doped polycrystalline silicon film, and the partially exposed semiconductor substrate main surface is formed. Forming a graft base region with impurities diffused from the substrate, selectively removing a non-doped polycrystalline silicon film to be the opening portion of the emitter hole, and performing a surface oxidation of the doped polycrystalline silicon film; A method of manufacturing a semiconductor device, comprising: a step of etching and removing a portion of a silicon nitride film and a silicon oxide film that becomes an emitter hole opening; and a step of depositing a polycrystalline silicon film to be an emitter electrode.