JP2580014B2 - Traffic detection circuit in packet communication - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a traffic detection circuit in packet communication for detecting traffic of a packet to be transmitted and performing traffic regulation and charging processing, and detects a data amount of a packet of each logical channel number at high speed. A temporary storage means for holding a variable length packet including a logical channel number passing through a transmission path, and a temporary storage means for providing a traffic detection circuit in packet communication capable of generating a traffic regulation signal. A logical channel number holding means for selecting and holding a logical channel number of a packet; a byte counting means for counting the number of bytes of each packet passing through the temporary storage means; A first memory for storing the number of packets for each channel number, A second memory for storing the number of bytes of the packet for each channel number, a third memory for storing the number of bytes and the number of packets preset as a regulation value for each logical channel number, and a comparing means; The first memory, the second memory, and the third memory are accessed by the logical channel number every time a packet passes, the content read from the first memory is added by 1 by the arithmetic means, and the content read from the second memory is the byte count. The output of the means and the addition means are added to each other, and each calculation result is written to the original memory. The limit value and the byte count limit value are sequentially compared,
When it is detected that one of the addition results exceeds a corresponding regulation value, a regulation signal corresponding to the logical channel number is generated.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a traffic detection circuit in packet communication that performs traffic regulation and charging processing by detecting the amount of packet transmission transmitted by packet communication.

2. Description of the Related Art In recent years, packet communication in which data is transmitted over a network in a unit of a variable amount of data called a packet and each packet reaches a desired destination via an arbitrary route has become widespread. In this case, a logical channel number area is provided in each packet header to identify a plurality of calls, and traffic regulation is controlled by the logical channel number. That is, when a packet with the same logical channel number is congested at a certain node, traffic control such as restricting transmission to a terminal or a transmission line on the side generating data of the logical channel number is performed.

Conventional techniques for performing such traffic control have been performed by software processing using a processor. However, software processing can cope with a case where the packet transmission speed is low, but it is difficult to keep up with the recent increase in packet transmission speed, and a solution is desired.

[Prior Art] FIG. 4 is an explanatory diagram of a conventional example, in which A. shows a packet frame format, B. shows an example of a network configuration of packet communication, and C. shows an example of the configuration of a packet communication device.

The frame format of the packet is as shown in A.
Flag section (indicated by F), address control section (A /
C), a packet data part, a frame check sequence part (displayed as FCS), and a flag part (F). A logical channel number (Logic Channel Number: LCN) is included in the first packet header of the packet data part. (Abbreviated) is included. In this LCN, the same number is assigned to a plurality of packets transmitted by one call, and different LCNs are used between different calls.

In the packet communication network, terminals and transmission lines are connected to communication devices such as nodes A to C as shown in B. There are various connection configurations of transmission lines between nodes such as a network type, a star type, and a ring type. There are things. In packet communication, communication between a plurality of terminals can be simultaneously performed on one transmission path,
The above-described LCN (logical channel number) is used to identify the plurality of calls.

The configuration of the packet communication device provided in the node will be described with reference to C. Packets received via the terminal interface 41 or the transmission line interfaces 42 and 43 are stored in the memory 4
4, stored in the communication control device (node control processor (N
The data is read out from the memory through the process of (CP) 45 and transmitted to the transmission line interface or the terminal interface to perform storage and exchange.

When performing traffic control within a packet communication network,
Since each LCN is independent, traffic control corresponding to the LCN is performed. For the control, a method of transmitting a transmission stop packet to a packet generation source before the reception becomes impossible due to packet congestion or the like is used.

By the way, a guideline for traffic control is to detect how many packets of the same LCN are flowing on the transmission path, and if the flow rate is high according to the detected value, restrict the output. ing. In order to detect the number of packets, it is conceivable to provide a counter for each LCN.
When the number of (logical channel numbers) increases (in some cases, thousands of LCNs are used), the scale of hardware including counters to be realized increases accordingly. Therefore, normally, from the detection of the LCN of the packet to the regulation control is performed by the software of the communication control device 45 of C in FIG. That is, the LCN of the packet is
Is detected, the auxiliary storage device 46 is executed by software processing.
The amount of packets corresponding to each LCN stored in is updated. Note that the detection of the packet amount is not only used for traffic control (flow rate control), but is also data necessary for charging for packet communication.

[Problem to be Solved by the Invention] In the above-mentioned conventional method, there is a problem that the processing speed is slow because traffic detection control is performed by software processing. It is also expected that the speed of packets will be increased in the future, and it is difficult to realize the real-time constantly the amount of packets being transmitted in real time for traffic regulation and charging of high-speed packets. is there.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a traffic detection circuit in packet communication capable of detecting a data amount of a packet of each logical channel number at a high speed and generating a traffic regulation signal.

[Means for Solving the Problems] FIG. 1 shows a basic configuration diagram of the present invention.

10 is a temporary storage unit, 11 is a byte counting unit, 12 is a logical channel number (LCN) holding unit, 13 is a first memory for storing the number of packets for each LCN, and 14 is an operation for performing +1 operation on the input numerical value. Means, 15 a comparing means for comparing the regulation value with the output of the calculating means 14, and 16 a second means for storing the number of bytes for each LCN.
The memory 17 represents an adding means for adding the output of the second memory and the output of the byte number counting means 11.

When packets use variable-length data (though some are fixed-length), it is not possible to determine the exact amount of data simply by detecting the number of packets. It is used as basic data for billing processing determined according to the traffic regulation or data amount.

The present invention is directed to a first memory for detecting a logical channel number of each packet header when a packet passes through temporary storage means in a packet communication device, and storing the number of packets and the number of bytes using the logical channel number as an address. And the contents of the second memory are read out and updated, and it is simultaneously detected that the traffic regulation is exceeded, and the processing is realized by hardware.

[Operation] The temporary storage means 10 shown in FIG. 1 is provided at a position on the input side (before being stored) or the output side (before outputting to the transmission path) of the exchange in the packet communication apparatus, and the input contents are kept as they are. Is output. When the logical channel number LCN is detected when the packet header is input to the temporary storage means 10,
It is stored in the CN holding means 12. Thereby, reading is performed from the first memory 13 and the second memory 16 using the output of the LCN holding means 12 as an address.

From the first memory 13, the number of packets Pn up to the previous time corresponding to the LCN is output and supplied to the arithmetic means 14. When the arithmetic means 14 performs a plus one operation, the output is stored in the first memory 13. The data is supplied as a data input. In the first memory 13, writing is performed at the original position using the output of the LCN holding means 12 as an address.

On the other hand, when one packet passes through the temporary storage means 10, the number of bytes (1 byte = 8 bits) included in the packet is counted by the byte counting means 11, and when one packet ends, the counted number of bytes is counted. The number of bytes output from the second memory 16 to the addition means 17 and held in the addition means or in another buffer (not shown) is added to the addition means 17 (integrated value of the number of bytes up to the previous time). The result is supplied as input data of the second memory 16, and the input data is written using the output of the LCN holding means 12 as an address.

When the output of the arithmetic unit 14 of +1 of the above-mentioned number of packets is generated, the output is supplied to the comparing unit 15, and at this time, the traffic regulation value of the preset number of packets is supplied to the other input side. When the number of packets input from the calculating means 14 reaches the traffic regulation value, the traffic control unit 14 outputs a regulation signal. Also, the addition result of the above-mentioned byte number adding means 17 is supplied to the comparing means 15 at a timing different from that of the arithmetic means 14, and at that time, the traffic regulation value based on the byte number is supplied to the other input side, so that the comparison is performed. When the traffic regulation value is reached as described above, a regulation signal is output.

The count value of each LCN packet stored in the first memory 13 and the count value of each LCN byte stored in the second memory 16 are used as billing information for each user (corresponding to the LCN). I do.

Embodiment FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 (a) is a block diagram of a packet communication device to which the present invention is applied, and FIG. 3 (b) is a part of the packet communication device. FIG.

In FIG. 2, reference numeral 20 denotes a shift register, 21 denotes an LCN latch circuit, 22 denotes a first memory that stores the number of packets corresponding to each LCN, 23 denotes a second memory that stores the number of bytes corresponding to each LCN, and 24 denotes the number of bytes. A counter, 25-1 is an arithmetic circuit for performing addition, 25-2 is an arithmetic circuit for performing +1 operation on an input value, 26 is a comparator, 27 is a third memory for storing a traffic regulation value corresponding to each LCN, and 28 is a register , 29 represent a decoder.

The operation of the embodiment of the traffic detection circuit shown in FIG. 2 will be described. Packets flowing on the line are passed to the shift register 20. Here, the timing is measured, and the LCN portion of the packet header is held in the LCN latch circuit 21. This LCN
Are read from the first memory 22 and the second memory 23, and the number of packets and the number of bytes corresponding to the LCN are read. The number of packets from the first memory 22 is input from the output data bus 221 to the arithmetic circuit 25-2.
1 is performed, and the resulting output is supplied to the input data bus 220 of the first memory 22, and is written to the first memory 22 using the output of the same LCN latch circuit 2 as an address.

The number of bytes (packet size value) is
Is counted by the byte number counter 24 at the position of, and the numerical value is supplied to the arithmetic circuit 25-1 and the second memory
23 is added to the integrated value of the number of bytes so far, which is the read output of 23, and the addition result is input data bus 23 of the second memory 23.
It is given to 0 and stored again with the same LCN as the address.

The third memory 27 stores in advance the threshold value of the traffic amount (threshold value of the number of packets and the number of bytes) for each LCN, and performs the calculation by the arithmetic circuit 25-1 or the arithmetic circuit 25-.
2, the comparator 26 compares the value of each operation result with each value of the third memory 27. In this case, since the calculation of the number of packets is performed first, the output of the arithmetic circuit 25-2 is compared with the threshold value of the number of packets in the third memory 27, and when the packet passes, the output is obtained from the arithmetic circuit 25-1. The result of addition of the number of bytes to be obtained is compared with a threshold value of the number of bytes in the third memory 27. At this time, if the calculation result in each of the calculation circuits 25-1 and 2 exceeds the threshold value correspondingly input, a regulation signal notifying the fact is output, and a packet exceeding the allowable value flows on the transmission path. Notify that. Thereby, the timing of packet regulation can be detected.

The data bus 280 and the address bus 290 are connected to a communication control device (not shown) to perform control and monitoring operations. That is, when an address is input to the address bus 290 and supplied to the decoder 29, part of the address is transferred to the register 28.
To generate an output for selecting either the first memory 22 or the second memory 23. The selection output is provided by a three-state gate circuit (22) provided in each address and data bus.
a, 22b,...), is controlled to be on and off, and can read a numerical value stored at an arbitrary address (corresponding to LCN) of the selected memory and output it to the data bus 280.

Thereby, the two memories 22 and 23 are received from the communication control device side.
It is possible to perform initialization setting and read the value of the LCN required during the count operation of the number of packets and bytes from the communication control device and monitor it. The third memory 27
By specifying an address from the communication control device and inputting and writing a regulation threshold value to the data bus 280, traffic regulation for each LCN can be performed.

The configuration of the packet communication device to which the embodiment of the present invention is applied will be outlined with reference to FIGS. 3 (a) and 3 (b).

The packet communication device shown in FIG. 3 (a) exchanges high-speed packets, and 30 is a transmission line / terminal accommodating unit.
It contains a plurality of transmission lines from other nodes and connection lines to terminals, from which the input-side transmission line interface 3
1,... Are input to the terminal interface 32 and connected to the respective input terminals of the packet switch switching unit 33.

The packets stored and switched in the packet switch switching unit 33 are transmitted through a transmission line interface 35 provided for a transmission line connected to another node or a line to a terminal.
Output through the terminal interface 36. The control of the packet switch exchange unit 33 is performed by a communication control unit (NCP) 34.
By monitoring the control information of each input side packet and the state of the output side, an optimum transmission path is selected and switching control is performed.

The traffic detection circuit of the present invention shown in the embodiment of FIG. 2 is used in the transmission line interface 31,..., The terminal interface 32 before input to the packet switch switching unit 33 of FIG. Each of the transmission line interfaces 35 output from the switching unit 33,...

FIG. 3 (b) shows a configuration example in which the traffic detection circuit of the present invention is provided in the transmission line interface 35 of FIG. 3 (a), and the packet switch switching unit 33 (FIG. 3 ( The packet output from a)) is input to the transmission line interface 35 shown in FIG.
Signal processing for transmission to the transmission path is performed in the transmission path processing circuit 352 through 351, and the signal is transmitted from the interface circuit 354 to the transmission path. The output from the interface circuit 351 is branched and input to the traffic detection circuit 353, where the number of packets and the number of bytes are counted by the configuration shown in FIG. The traffic detection circuit is controlled by the communication control device 34 as described with reference to FIG. 2, and the traffic control device 37 gives a traffic control value and, when the control value is exceeded, sends a control packet to the packet source. It performs traffic control such as occurrence. Further, the number of bytes of the packet is collected by the accounting processing device 38 and accounting is performed.

[Effects of the Invention] According to the present invention, it is possible to speed up packet detection by processing the traffic by hardware,
It can also be applied to high-speed packet communication. In addition, an increase in the logical channel number (LCN) can be dealt with by expanding the memory capacity. Further, since the traffic capacity can be detected at arbitrary time intervals, a wide range of traffic regulation can be achieved.

[Brief description of the drawings]

FIG. 1 is a basic block diagram of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 (a) is a block diagram of a packet communication apparatus to which the present invention is applied, and FIG. FIG. 4 is a diagram showing a configuration of a part of a packet communication device, and FIG. 4 is an explanatory diagram of a conventional example. In FIG. 1, 10: temporary storage means 11: byte counting means 12: logical channel number (LCN) holding means 13: first memory 14: arithmetic means 15: comparing means 16: second memory 17: adding means

Continuation of the front page (56) References JP-A-61-252731 (JP, A) JP-A-63-107249 (JP, A) JP-A-1-183939 (JP, A) JP-A-63-280542 (JP) , A)

Claims (1)

(57) [Claims] In a traffic detection circuit for packet communication, a temporary storage means for holding a variable-length packet including a logical channel number passing through a transmission path, and a logical channel number of a packet selected and held from the temporary storage means. A logical channel number holding unit that performs counting, a byte counting unit that counts the number of bytes of each packet passing through the temporary storage unit, and stores the number of packets for each logical channel number using an output of the logical channel number holding unit as an address. First
A memory, a second memory for storing the number of bytes of a packet for each logical channel number, a third memory for storing a predetermined number of bytes and a number of packets for each logical channel number as a regulation value, The first memory, the second memory, and the third memory are accessed by the logical channel number every time a packet passes,
The content read from the first memory is 1
Is added to the output of the byte counting means, which is the content read from the second memory, and is added by the adding means. Each addition result is written to the original memory, and the comparison means calculates the addition result of the number of packets. And the result of addition of the number of bytes is sequentially compared with the regulation value of the number of packets and the regulation value of the number of bytes read from the third memory, and when it is detected that one of the addition results exceeds the corresponding regulation value, A traffic detection circuit in packet communication, which generates a regulation signal corresponding to a logical channel number.