JP2586571B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Photodiode section, transfer gate section and CC
Regarding the interline type solid-state imaging device consisting of a D register section, all charges accumulated in the photodiode are transferred to the CCD register even with a small
In order to improve the / N ratio, in an interline type solid-state imaging device, when the channel dose is applied to the transfer gate between the photodiode and the CCD register, the channel dose is implanted only into the center of the transfer gate by ion implantation. , A non-injection region is provided on both sides of the photodiode and the CCD register.

[Industrial applications]

The present invention relates to an interline solid-state imaging device, and more particularly to an improvement in an S / N ratio.

In recent years, with respect to semiconductors and solid-state imaging devices, high integration has progressed, and reductions in the area of pixels and CCD registers have been required.

Therefore, the efficiency of the charge stored in the photodiode is high.
The transfer to the CCD register and the efficiency of the CCD register need to be increased.

[Conventional technology]

2A and 2B are views for explaining a conventional example, FIG. 2A is a cross-sectional view of the conventional example, and FIG.

In the figure, 1 is a photodiode section, 2 is a transfer gate section, 3 is a CCD register section, 4 is a CCD storage electrode, 5 is a CCD barrier electrode, 6 is a CCD storage electrode, and zero bias is applied to the barrier electrode. In this case, 7 indicates the potential when the transfer gate is turned on, 8 indicates the potential barrier height, and 9 indicates the residual charge amount.

In a conventional interline type solid-state imaging device,
Under the transfer gate between the photodiode and the CCD register, it is necessary to be a P-type having a certain density to prevent smear. Therefore, impurities have been implanted into the transfer gate using the selectively formed resist as a mask.

However, these impurities diffuse in the lateral direction due to the heat treatment during the process step. That is, with the photodiode
It will diffuse into the formation area of the CCD register.

That is, even if the transfer gate 2 is turned on, the P-type impurity from the transfer gate 2 is diffused in the region of the photodiode 1 in the lateral direction.
There is a problem that 100% of the charges are not erased and transferred due to a polar barrier between the photodiode part and the transfer gate part. Reference numeral 8 denotes a potential barrier height remaining when the transistor is turned on, and reference numeral 9 denotes a residual charge amount that is not transferred.

[Problems to be solved by the invention]

Therefore, there is a drawback that a sufficient output is not obtained when the usage is insufficient. Further, when the area of the photodiode is reduced, the area for photoelectric conversion is reduced, which also causes a problem that a sufficient output cannot be obtained.

The present invention adjusts the lateral diffusion of the P-type impurity in the transfer gate section 2 so that the transfer gate section 2 is formed.
The purpose is to reduce the potential barrier height generated between the photodiode portion and the transfer gate portion when the transistor is turned on, so that untransferred charges do not remain.

[Means for solving the problem]

FIG. 1 is a diagram showing the basic principle of the present invention, in which (a) is a sectional view and (b) is a diagram showing potential. In this case, the transfer gate portion 2 is configured to implant a P-type impurity using a resist selectively formed inside the region where the transfer gate portion 2 is formed as a mask in consideration of lateral diffusion.

[Action]

In the present invention, the potential distribution as shown in FIG. 1 (b) is realized, and the charges accumulated in the photodiode when the transfer gate is turned on are all reduced.
It is transferred to the CCD register. Therefore,
Heretofore, there has been a case where a CCD register does not output even if a small amount of light is incident and charges are accumulated in a photodiode. However, this enables output even when the light amount is small.

〔Example〕

3 (a) to 3 (d) are process diagrams showing one embodiment of the present invention.

 In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals.

First, an oxide film is formed on the semiconductor substrate 11 to form an element formation region.
After the growth, the oxidation-resistant film 13 is grown by CVD and patterned by using the selectively formed resist as a mask. (Third
(FIG. 2A) Next, the entire surface is oxidized, and the oxidation resistant film 13 is etched to form the field insulating film 12. (FIG. 3B) Using the selectively formed resist I as a mask, a P-type impurity is implanted into the transfer gate formation region.
(FIG. 3C) An n-type impurity is implanted into the CCD register using the newly selectively formed resist II as a mask. (FIG. 3D) Poysi grown by the CCD method is patterned by using a selectively formed resist as a mask to form a storage electrode 4 and a barrier electrode 5 of the CCD register. Further, using the newly selectively formed resist III or storage electrode 4 and resist III as a mask,
An n-type impurity is implanted in the diode. (FIG. 3E) That is, in the present invention, a resist mask is selectively formed on both sides of the transfer gate portion on the photodiode side and the CCD register side such that the width of the non-implanted region is about 0.1 to 2.0 μm. Implant impurities.

In this case, since the P-type impurity formed under the transfer gate formed by the resist I is sufficiently on the CCD register side as compared with the storage electrode 4, a barrier is generated between the photodiode and the transfer gate even when the transfer gate is turned on. Without any charge
Injected into the CCD register.

In the above embodiment, the transfer gate is formed by the storage electrode 4, but this may be formed by the electrode 5. Also, the CCD register is not limited to the embedded type.

〔The invention's effect〕

According to the present invention, in a solid-state imaging device, since the photoelectrons of the photodiode are sufficiently transferred, the output is increased, and the S / N ratio is improved.

[Brief description of the drawings]

1A and 1B are principle diagrams for explaining the present invention, in which FIG. 1A is a sectional view, FIG. 1B is a diagram showing potential, FIG. 2 is a diagram for explaining a conventional example, and FIG. FIG. 3B is a diagram showing a potential, and FIGS. 3A to 3E are diagrams showing a manufacturing process of an embodiment according to the present invention. In the drawing, 1: photodiode section 2: transfer gate section 3: CCD register section 4: CCD storage electrode 5: CCD barrier electrode

Claims (1)

(57) [Claims] In an interline type solid-state imaging device, when a channel dose is applied to a transfer gate portion between a photodiode and a CCD register, a channel dose is applied only to a central portion of the transfer gate portion by ion implantation, and a photodiode side and a CCD are provided. A solid-state imaging device having non-injection regions on both sides of a register.