JP2586591B2 - Operational amplifier - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier comprising a control circuit for reducing current consumption when not in use, and comprising a complementary MOS transistor (hereinafter referred to as a CMOS transistor). It is.

2. Description of the Related Art In recent years, analog circuits have been constructed using CMOS transistors that have been widely used in digital circuits, and semiconductor integrated circuits in which analog circuits and digital circuits are mixed have been produced. One of the important analog circuits formed of CMOS transistors is an operational amplifier.

Hereinafter, an operational amplifier (hereinafter, referred to as a CMOS operational amplifier) including a conventional CMOS transistor will be described.
Description will be made with reference to the circuit diagram shown in the figure.

This circuit includes a bias circuit 1, a differential circuit 2, a level shift circuit 3, and an output circuit 4.

The connection relation of the circuit is shown below. The bias circuit 1
P-type transistor (hereinafter, referred to as P transistor)
5 and N-type transistors (hereinafter referred to as N-transistors) 6 and 7. A source electrode (hereinafter, referred to as a source) of the P transistor 5 is connected to a positive power supply terminal 8, and a gate electrode (hereinafter, referred to as a gate) is connected to a drain electrode (hereinafter, referred to as a drain) of the P transistor 5 and an N transistor. 6 is connected to the drain and gate. The source of the N transistor 6 is connected to the drain / gate of the N transistor 7, and the source of the N transistor 7 is connected to the negative or ground power supply terminal 9. The gate of the transistor 7 is connected to the output terminal 10 of the bias circuit 1.

Next, the differential circuit 2 includes P transistors 11 and 12 and N
It is composed of transistors 13, 14, and 15. The source of the P transistor 11 is connected to the power supply terminal 8, and the gate and the drain are commonly connected to the gate of the P transistor 12 and the drain of the N transistor 13. The source of the P transistor 12 is connected to the power supply terminal 8, and the drain is connected to the drain of the N transistor 14 and the output terminal 16 of the differential circuit 2. The gate of the N transistor 13 is connected to the negative input terminal 17 of the CMOS operational amplifier, and the source is connected to the source of the N transistor 14 and the drain of the N transistor 15. N transistor
The gate of 14 is connected to the positive input terminal 18 of this CMOS operational amplifier. The gate of the N transistor 15 is connected to the output terminal 10 of the bias circuit, and the source is connected to the power supply terminal 9.

Next, the level shift circuit 3 includes N transistors 19 and 20
It is composed of The drain of the N transistor 19 is connected to the power supply terminal 8, the gate is connected to the output terminal 16 of the differential circuit, and the source is connected to the drain of the N transistor 20 and the output terminal 21 of the level shift circuit. The gate of the N transistor 20 is connected to the output terminal 10 of the bias circuit, and the source is connected to the power supply terminal 9.

Next, the output circuit 4 includes P transistors 22 and 23, an N transistor 24, and a phase compensation capacitor 25. The source of the P transistor 22 is at the power supply terminal 8, the gate is at the output terminal 16 of the differential circuit, and the drain is the N transistor.
The drain 24 is connected to the phase compensation capacitor 25 and the output terminal 26 of the CMOS operational amplifier. N transistor 24
Is connected to the output terminal 21 of the level shift circuit, and the source is connected to the power supply terminal 9. The source of the P transistor 23 is connected to the output terminal 16 of the differential circuit, the gate is connected to the power supply terminal 9,
The drain is connected to the phase compensation capacitor 25.

The operation of the conventional CMOS operational amplifier configured as described above will be described below.

In the bias circuit 1, a bias voltage determined at the size of the constituent transistor and generated at the output terminal 10 of the bias circuit is supplied to the differential circuit 2 and the level shift circuit 3.
The differential circuit 2 and the level shift circuit 3 operate by flowing a current into the circuit by the bias voltage. In the differential circuit 2, the voltage difference between the signals applied to the positive input terminal 18 and the negative input terminal 17 is amplified by the gain of the differential circuit 2 and output from the output terminal 16 of the differential circuit. . The level shift circuit 3 subtracts the signal input from the output terminal 16 of the differential circuit by a voltage value determined by the size of the constituent transistor, and outputs the result from the output terminal 21 of the level shift circuit. The purpose of the level shift circuit 3 is to increase the voltage applied to the gate of the N-transistor 24 of the output circuit 4 from the output voltage of the differential circuit 2 by a fixed value, to increase the gain of the output circuit 4, This is to increase the total gain of the CMOS operational amplifier. The output circuit 4 outputs to the output terminal 26 a signal obtained by amplifying the output of the differential circuit by the gain of the output circuit 4 from the output of the differential circuit 2 and the output of the level shift circuit 3.

Now, _let the gain of the differential circuit 2 be A _d and the gain of the output circuit 4 be A _d
o and the applied voltages to input terminals 18 and 17 are V _in ⁺ and V
_in ^- if that, the output signal V _out of _the output terminal 26 is expressed by the following equation.

_{V out = A d · A o} · (V in + -V in -) ...... (1) to be Solved by the Invention above problems, CMOS operational amplifier is used as an ordinary semiconductor integrated circuit. In some semiconductor integrated circuits, it is often necessary to stop the operation and reduce the current consumption depending on the application. For example, in a semiconductor integrated circuit for communication or the like, it is necessary to reduce current consumption during a communication waiting time. Therefore, it is necessary to reduce the current consumption when the CMOS operational amplifier is not used.

However, in the above-described conventional configuration, there is no circuit for reducing the current consumption of the CMOS operational amplifier, so that the current consumption is always constant and has a drawback that it continues to flow.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a CMOS operational amplifier capable of stopping the circuit operation when not in use and reducing current consumption when not in use.

Means for Solving the Problems In order to achieve this object, an operational amplifier of the present invention comprises:
A bias circuit having a bias control circuit for generating or eliminating a bias voltage according to a signal from the first control terminal, a differential circuit having two input terminals, and level shifting the output of the differential circuit Level shift circuit and P
An operation of the P-type MOS transistor is controlled by a signal from the first control terminal to an output stage in which a N-type MOS transistor and an N-type MOS transistor are connected in series, and the N-type MOS transistor is controlled by a signal from a second control terminal. An output circuit including an output control circuit for controlling the operation of the MOS transistor.

According to the operational amplifier of the present invention, the circuit can be operated normally during operation, the current can be cut off when not in use, and the turning operation can be stopped, and the sink current and the discharge current in the output circuit can be stopped. it can.

Embodiment An embodiment of an operational amplifier according to the present invention will be described below with reference to the circuit diagram shown in FIG.

This circuit includes a bias circuit 27, a differential circuit 2, a level shift circuit 3, and an output circuit 28.

First, the bias circuit 27 includes a bias section including the P transistor 5 and the N transistors 6 and 7 and the P transistor 29.
And a bias control circuit comprising an N-transistor 30. The source of the P transistor 5 is the power terminal 8
The gate is connected to the drain of the P transistor 29 and the drain of the N transistor 30, and the drain is connected to the drain and gate 13 of the N transistor 6 and the source of the N transistor 30. The source of N transistor 6 is the drain and gate of N transistor 7 and the output terminal of bias circuit 27.
Connected to 10. The source of the N transistor 7 is connected to the power supply terminal 9. The source of the P transistor 29 is connected to the power supply terminal 8, and the gate and the gate of the N transistor 30 are connected to the first control terminal 31.

Next, the differential circuit 2 and the level shift circuit 3 have the same configuration as the conventional example described with reference to FIG.

Next, the output circuit 28 has a gate connected to the output terminal of the differential circuit 2.
16 which is connected to 16 and controls and outputs the voltage of the power supply terminal 8
The P-transistor 22 and the P-transistor 23, which are the MOS transistors, have their gates connected to the output terminal 21 of the level shift circuit 3 and control the voltage of the power supply terminal 9 for output.
And a phase compensation capacitor 25. Further, when the bias circuit 27 eliminates the bias voltage, the output circuit 28 fixes the first gate to prevent the through current from flowing.
, A P-transistor 32 as a switch means, an N-transistor 35 as a second switch means, and a P-transistor 33 and an N-transistor 34 as a third switch means. The source of the P transistor 22 is connected to the power supply terminal 8, the gate is connected to the output terminal 16 of the differential circuit 2, and the drain is connected to the drain of the N transistor 24 and the output terminal 28 of the phase compensation capacitor and the CMOS operational amplifier. The gate of the N transistor 24 is connected to the drain of the P transistor 33, the source of the N transistor 34 and the drain of the N transistor 35, and the source is connected to the power supply terminal 9. The source of the P transistor 23 is connected to the output terminal 16 of the differential circuit 2, the gate is connected to the power supply terminal 9, and the drain is connected to the phase compensation capacitor 25. The source of the P transistor 32 is the power supply terminal 8
The gate is connected to the first control terminal 31 and the drain is connected to the output terminal 16 of the differential circuit 2. The drain of the N transistor 34 is connected to the output terminal 21 of the level shift circuit 3, and the gate is connected to the first control terminal 31. P transistor
The source of 33 is connected to the output terminal 21 of the level shift circuit 3, and the gate is connected to the second control terminal 36 of the CMOS operational amplifier. The gate of the N transistor 35 is connected to the second control terminal 36,
The source is connected to the power supply terminal 9.

The operation of the CMOS operational amplifier of the present invention configured as described above will be described below.

The operation will be described by dividing the operation into a normal operation state and a low current consumption state. The normal operation state and the low current consumption state are selected by signals input to the first control terminal 31 and the second control terminal 36. Now, assume that the voltage value of the power supply terminal 8 is positive V _DD and the voltage value of the power supply terminal 9 is negative V _SS . To enter the normal operation state, the voltage input to the first control terminal 31 is set to V _DD , and the voltage input to the second control terminal 36 is set to V _SS . To achieve the low current consumption state, the voltage input to the first control terminal 31 is set to V _SS , and the voltage input to the second control terminal 36 is set to V _DD . The relationship between the operating state described above and the voltage value of the control terminal is summarized in the following table.

First, the operation in the normal operation state will be described.

First, the operation of the bias circuit 27 will be described. Since it is in the normal operation state, the first control terminal 31 is fixed to _VDD . Since the first control terminal 31 is connected to the gate of the P transistor 29,
Source voltage (hereinafter, referred to as V _GS.) Since there are at 0V, which shuts off the P transistor 29. Further, since the first control terminal 31 is connected to the gate of the N transistor 30, the V _GS of the N transistor 30 exceeds the threshold voltage of the N transistor, and the N transistor 30 is in a conductive state. Since the P transistor 29 is cut off, no current flows between the drain and source of the N transistor 30. Therefore, the drain and source of the N transistor 30 have the same potential due to the characteristics of the MOS transistor. With this circuit connection, the gate and drain of P transistor 5 and N
The drain and the gate of the transistor 6 are all at the same potential and have the same connection as the conventional bias circuit. The current determined by the P transistor 5 and the N transistor 6 flows through the N transistor 7, and the current value and the bias voltage determined by the gate size of the N transistor 7 are output from the output terminal 10 of the bias circuit 27. .

Next, in the differential circuit 2, by applying a bias voltage to the gate of the N transistor 15, the P transistor
A current flows through a differential section composed of 11 and 12, and N transistors 13 and 14. This current is distributed by a signal voltage applied to a positive input terminal 18 and a negative input terminal 17, thereby forming a load transistor. The voltage between the source and the drain of the P transistor 12 is changed, and the voltage difference between the positive input terminal 18 and the negative input terminal 17 is
The signal amplified by the gain of the differential circuit 2 is output from the output terminal 16 of the differential circuit 2.

In the level shift circuit 3, a signal from the output terminal of the differential circuit 2 is subtracted by a voltage value determined by the size of the P transistor 19 and the N transistor 20, and a level shift output is obtained. Output.

Next, the operation of the output circuit 28 will be described. First control terminal
Since 31 is at the level of V _DD , the gate of the P transistor 32 is also at the level of V _DD and the P transistor 32 is shut off. Therefore, the drain of the P transistor 32 is in a high impedance state, and does not hinder the output operation of the differential circuit 2 at all. Similarly, since the second control terminal 36 is at the V _SS level, the gate of the N transistor 35 is also at the V _SS level, and the N transistor 35 is shut off. Therefore, the drain of the N transistor 35 is in a high impedance state, which is equivalent to the absence of the N transistor 35. The P transistor 33 and the N transistor 34 constitute an analog switch. Now, the first control terminal
Since 31 is at the V _DD level and the second control terminal 36 is at the _VSS level, both the P transistor 33 and the N transistor 34 are conducting. Further, the drain of the P transistor 33 and the source of the N transistor 34 are connected to the gate of the N transistor 24, and no current flows through the P transistor 33 and the N transistor 34. Therefore, the potential between the drain and source of the P transistor 33 and the potential between the drain and source of the N transistor 34 are equal. That is, the output terminal 21 of the level shift circuit 3 is connected to the gate of the N transistor 24,
The output circuit 28 amplifies the output of the differential circuit 2 with the gain of the output circuit 28 and outputs the same as in the conventional example.

From the above, it can be seen that the operation in the normal operation state is the same as the conventional example.

 Next, the operation in the low current consumption state will be described.

When the low current consumption state, that is, when the bias voltage is extinguished, the P transistor 22 and the N
The through current in the transistor 24 becomes a problem.

In order to prevent this through current, the gate of the N transistor 24 is cut off from the level shift circuit 3, and the gate is fixed at the power supply potential so that the P transistor 22 and the N transistor 24 are turned off.

First, the operation of the bias circuit 27 will be described. The first control terminal 31 is at the _VSS level, the first control terminal 31 is connected to the gate of the P-transistor 29, and the N-state is turned on.
Transistor 30 is off. No current flows through the P transistor 29 because the N transistor 30 is shut off. Therefore, the potentials of the drain and the source of the P transistor 29 are equal and are at the V _DD level. Therefore, the P transistor 5 is shut off. Since the P transistor 5 is shut off, no current flows through the N transistors 6 and 7.
Since the gate and the drain of the N transistor 7 are connected, V _GS when no current flows is equal to the threshold voltage of the N transistor. That is, the bias circuit 27
, No current flows, and the voltage output to the output terminal 10 of the bias circuit 27 is equal to the threshold voltage of the N transistor 7 + V
Equal to _SS .

Next, in the differential circuit 2, since the bias voltage output from the bias circuit 27 is the threshold voltage + _VSS , no current flows through the N transistor 15, and the P transistors 11 and 12 and the N transistors 13 and 14 All are shut off, the drain of the P transistor 12 and the drain of the N transistor 14 are in a high impedance state, and the output from the differential circuit 2 is not determined by the differential circuit 2.

The level shift circuit 3, since the bias voltage is the threshold voltage + V _SS, shuts off the N-transistor 20, a current does not flow. The voltage between the gate and the source of the N transistor 19 is equal to the threshold voltage of the N transistor 19, and the output voltage of the level shift circuit 3 is equal to the output voltage of the differential circuit minus the threshold voltage.

Next, in the output circuit 28, since the first control terminal 31 is at the V _SS level and the second control terminal 36 is at the V _DD level,
Transistor 32 and N-transistor 35 are conducting,
The P-transistor 33 and the N-transistor 34 constituting the analog switch are in a cut-off state. The drain of this transistor is equal to _VDD because P transistor 32 is conducting and no current flows through this transistor. Therefore, the output voltage of the differential circuit 2 becomes the _VDD level, the P transistor 22 is completely cut off, and the drain of the P transistor 22 is in a high impedance state. Next, the P transistor 33 and the N transistor 34 are cut off,
Since the transistor 35 is conducting, the potential of the gate of the N transistor 24 becomes V _SS ,
Is completely shut off, and the drain of the N transistor 24 enters a high impedance state. Therefore, no current flows in the output circuit 28, and no current flows into and out of the output terminal 26 of the CMOS operational amplifier.

As described above, according to the present embodiment, the bias circuit that supplies the bias voltage to the differential circuit 2 and the level shift circuit 3
27, a P-type transistor 29 for controlling whether a bias current is supplied to generate a bias voltage or whether the bias current is stopped, the bias voltage is reduced, and the power consumption is reduced.
And an N-type transistor 30 for bias control. Further, the gate voltage of the output P-picture transistor 22 of the output circuit 28 is made to follow the output of the differential circuit 2 to perform a normal operation, or the gate voltage of the P-type transistor 22 is fixed to the power supply voltage. A gate voltage of a P-type transistor 32 for controlling whether or not a discharge current is generated, and a gate voltage of an N-type transistor 24 for output of an output circuit 28,
Connect to the level shift circuit 3 to perform a normal operation, or disconnect the gate voltage of the N-type transistor 24 from the level shift circuit 3 and output the N-type transistor.
A circuit 24 controls the output circuit 28 with a P-type transistor 33 and N-type transistors 34 and 35 for controlling whether the voltage is fixed to a low voltage that does not generate a sink current. This allows the CMOS operational amplifier to perform normal circuit operation, and also stops the circuit operation when not in use to reduce current consumption.
Further, the discharge current and the sink current of the output circuit 28 can be stopped.

As described above, according to the present invention, a bias control circuit configured by adding one P-type transistor and one N-type transistor to a bias circuit and the power supply terminals 8 and 9 are connected in series. P-type transistor for controlling the gate voltage of the output P-type transistor of the output circuit and the P-type transistor for output of the N-type transistor, two N-type transistors for controlling the gate voltage of the output N-type transistor of the output circuit, and P-type transistor By providing an output control circuit configured by adding a transistor, an operation of cutting off current when not in use and reducing current consumption of the CMOS operational amplifier can be realized.
Furthermore, the source current and sink current of the output of the CMOS operational amplifier can be stopped, and the current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a CMOS operational amplifier showing an embodiment of an arithmetic circuit according to the present invention, and FIG. 2 is a circuit diagram of a conventional CMOS operational amplifier. 2 ... Differential circuit, 3 ... Level shift circuit, 8 ... Positive power supply terminal, 9 ... Negative or ground power supply terminal, 5,11,12,22,2
3,29,32,33 …… P-type MOS transistor, 6,7,13,14,15,1
9, 20, 24, 30, 34, 35 ... N-type MOS transistor, 10 ... output terminal of bias circuit, 16 ... output terminal of differential circuit, 17
…… Negative input terminal, 18… Positive input terminal, 21 …… Output terminal of level shift circuit, 25 …… Phase compensation capacitor, 26
…… Output terminal of CMOS operational amplifier.

Claims (1)

(57) [Claims] A bias circuit for generating or extinguishing a bias voltage based on a control signal; a differential circuit having two input terminals, the current of which is controlled by the bias voltage; and an output of the differential circuit being level-shifted. A level shift circuit, a first MOS transistor having a control terminal connected to an output terminal of the differential circuit and controlling and outputting a first power supply voltage, and a control terminal connected to an output terminal of the level shift circuit And an output circuit having a second MOS transistor for controlling and outputting a second power supply voltage, wherein the first switch means operates when the bias circuit eliminates the bias voltage. , A second switch means and a third switch means, wherein the first switch means supplies a first power supply voltage to a control terminal of the first MOS transistor. Wherein the second switch means supplies a second power supply voltage to a control terminal of the second MOS transistor, and the third switch means outputs an output of the level shift circuit to the second MOS transistor. And a control terminal of the second MOS transistor and the output terminal of the level shift circuit and the second terminal.
An operational amplifier provided between the control terminal of the MOS transistor and the control terminal.