JP2587195B2 - Computer system and method for load balancing or asynchronous data movement - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method for controlling a plurality of queues while a subsystem including a processor continues to control the movement of data within and between electronic storage media without intervention from an operating system. It provides automatic load balancing between queue processors, automatic recovery from a failed queue processor, and automatic subsystem reconfiguration.

[0002]

2. Description of the Related Art In a conventional computer system, a plurality of input / output processors (IOPs) having dedicated work queues (WQs) are used to request data movement between input / output devices and computer memory. Was managing the request. Each IOP WQ uses a subset of the I / O devices and operates using the corresponding subchannel ID number. Each subchannel ID number is internally represented by a queuing element (QE) in protected system storage, and depending on the path associated with the device represented by that subchannel, one or more IOPs Assigned to use WQ. I / O devices are accessed via various physical paths, and some I / O devices can be accessed via multiple paths. Each path to an I / O device has one I / O channel and one control unit (CU)
And an input / output path switch can be included. Each I
OPs and their associated WQs have access to a subset of the routes, so that they can only service QEs with a particular route.

[0003] The IOP manages the input / output workload required by the CPU in the system. Each CPU executes a start subchannel (SSCH) instruction to execute a certain IOP.
Work requests can be placed in the WQ. Each CPU on WQ
Each request contains one queue element (QE).
QE is a control block that indicates an input / output device to be started and specifies data movement information. An I / O request cannot be fulfilled unless a physical path to the requested I / O device becomes available, including a different channel processor to control a different physical path. Thus, if any of the components included in the physical path are busy, the request will be on standby. If the control unit (CU) of the physical path to an I / O device is not available, a request (QE) is sent from the WQ to the control unit queue (CUQ).
And stop on this CUQ until the CU is available. When a CU becomes available, the request is returned to the original WQ assigned by the channel processor for that path, which controls I / O operations.

When an I / O operation is completed, the assigned IOP moves its QE to an interrupt queue (IQ) assigned to its subchannel and sends an interrupt signal to all CPUs in the system. , Generate an input / output pending interrupt. First CPU available for interrupts
Can monitor the IQ and handle one or more pending interrupts. Each QE is assigned to use the indicated IQ in its subchannel out of the eight IQs associated with an interrupt subclass. In the IOP subsystem, when a plurality of routes for accessing a certain device are defined in a subchannel, and a route on one WQ is used or unavailable, and a route on another WQ is available. Only redistribute work among some of its WQs. Conventional IOP subsystems do not move QEs between different WQs to utilize idle IOPs. In the conventional subsystem, QE is WQ
In order to process this QE, it was necessary to have the WQ and IOP assigned to the subchannel. If the assigned WQ-only IOP is busy or has failed, the I / O operation has not been started in the channel and unless there is an alternate path on another IOP, the QE's The QE could not be moved to another WQ to continue uninterrupted execution. IO
P could only be reconfigured as a group (when reconfiguring relevant parts of the computer system) by removing the entire group from the computer system. If no alternative route is available, the operation is aborted. Therefore, the prior art IOP WQ
And its IOP were not used for workload balancing, recovery or reconfiguration.

[0005] In conventional computer systems, if only one path is provided for a subchannel, the QE associated with that subchannel ID is assigned to it while the path assigned to it is in use. The I / O controller must be in the control unit queue (CUQ) while the I / O controller is busy. Since different sub-channels use different CUQs, CUQs cannot serve as a central point for balancing IOP queuing work. Therefore,
In the prior art, a QE work request could only use a WQ permanently assigned to a subchannel. If multiple start sub-channel instructions (work requests) from one or more CPUs are directed to a sub-channel assigned to a particular WQ, the other one or more WQs are empty and associated with it. Even if the processor is idle,
All of these work requests must use that WQ. Therefore, in a conventional IOP subsystem,
The workload can be very unbalanced between WQs.
Also, in the prior art, if any IOP fails, a catastrophic condition exists, the I / O requests for the IOP's WQ are placed in an abort queue, and an alternate route is unavailable or its channel Is aborted if the input / output operation has been started. To repeat the aborted I / O request on the newly assigned operational WQ, the CPU uses the new path to bypass the failed WQ and its associated IOP and re-route its subchannel. Human intervention is required to reassign to another operational WQ and re-execute the CPU software from the appropriate previous point in the interrupted application program so that CPU requests can be repeated. May be required.

[0006]

SUMMARY OF THE INVENTION It is a primary object of the present invention to provide a method for processing from a main processor of a computer system.
The provision of workload balancing, recovery and reconfiguration within a subsystem performing offload. This one
An example is ADM (asynchronous data movement). The present invention requires multiple processors in the offload subsystem of the computer system.

[0007]

SUMMARY OF THE INVENTION The present invention utilizes the processing and means of an ADM to provide a working sub-unit (e.g., a working sub-unit) between a source location in an electronic memory and a destination location in the same or another electronic memory. Manage the processes used by multiple processors to perform data page transfers efficiently and continuously. The CPU interface to the ADM has an S / 390 subchannel start (SSC
H) Use instructions. Request ADM operation using a special ADM subchannel. ADM subsystem is CP
While executing the U request to move any number of pages requested by the CPU from a source location in electronic memory to a destination location in the same or another electronic memory, the CPU may perform other tasks. it can. This subsystem includes multiple ADs
It has M processors, associated queues, common queues, and control logic. Multiple ADM processors, multiple CPUs requested via multiple ADM subchannels
Requests can be executed simultaneously. Any ADM subchannel and its associated QE can distribute ADM requests to the subsystem. Any ADM processor can be any CPU in a computer system (CEC)
Can perform the ADM subchannel request received from. GR1 (General Purpose Register 1) stores the implicit operand of the SSCH instruction, which is the SCH ID (subchannel identifier) number that identifies the subchannel and its associated queue element (QE). The Queue element is a microcoded control block that represents the subchannel ID at the internal microcode interface. The QE is used by the CPU as a "mail package" to send the CPU request to the subsystem that performs the CPU request.

[0008] Another operand of the SSCH instruction is
The first ADM of an ADM program consisting of one or more ADM CCWs (Channel Command Words)
Specify the location of the CCW. Each ADM CCW specifies a list of MSBs (move designation blocks) in the computer's memory. Each MSB specifies a sending side designation and a receiving side designation. The transmission side specification specifies the head address of the original position of an arbitrary number (specified by the page count field) of continuous pages (for example, 4 KB / page) of data in the memory. The receiving side designation includes the start address of the destination position in the memory for receiving the continuous page copied from the original position. While the ADM subsystem processes the CPU request information and controls the transfer of a potentially vast number of data pages within and between electronic memories, the CPU can perform other tasks. . AD
After the M subsystem has transferred all pages of the CPU request, it sends an I / O type interrupt to all CPUs to signal the completion of this CPU instruction. All CPUs
Receive this interrupt signal, one of which accepts it under existing ES / 390 architecture rules.

In accordance with the present invention, an ADM subsystem provides automatic ADM load balancing, automatic recovery from a failed processor without interrupt to ADM processing, and ADM subsystem.
The automatic reconfiguration of one or more processors in a subsystem can be used to handle a very large number of CPU requests continuously. The ADM load balancing, recovery, and reconfiguration functions are all transparent to CPU processing and operating system software.

Further, in accordance with the present invention, a computer system balances a workload using the same CPU interface currently used by a CPU to interface with an I / O subsystem having an IOP and a WQ. Interface with the ADM subsystem. The present invention uses this property of interface compatibility to combine the operation of the ADM subsystem and the I / O subsystem to perform both types of operations and share the same set of work queues.
Make it a single subsystem. Thus, in this combined subsystem, the queue can hold both ADM and I / O requests, and each queue offload processor (QOP) performs both ADM and I / O functions, respectively. . However, the common queue (CQ) in the combined subsystem is used only for ADM operation.

Within the combined subsystem, the queuing processor operates as a normal IOP when processing I / O requests and as an ADM processor when processing ADM requests.

However, the ADM function and the input / output function are performed by separate subsystems (A) in the same computer system.
DM subsystem and input / output subsystem). However, in general, in current systems,
Providing a combined subsystem in which ADM and I / O requests share a queue with the processor has been found to be cost effective.

Also, in the combined system, on each queue, I / O requests are given a higher processing priority than ADM requests. Because the I / O requests are not serviced by the processor associated with the queue (the I / O requests are serviced by a different processor, the channel processor controlling the I / O data movement operation), so the processing time is very short Because it only needs them. On the other hand, ADM requests are completely controlled by the processor associated with the queue and no other processor is used. Because ADM requests use this extra processor, the average ADM request requires much more processing time than any I / O request, and therefore has more ADM work, even when I / O traffic is high. Of processor time. However, I / O requests can be processed between ADM work subunits.

Thus, in the preferred embodiment herein, the ADM operation will be described as being processed by a QOP (queue offload processor).
It should be understood that P need not be dedicated to ADM operations, and that the QOP may perform normal I / O operations on the same queue.

The present invention provides a new method for managing CPU requests for ADM services that is managed differently than I / O requests handled by the same hardware processor. The same hardware processor performs different processing for ADM and I / O requests.

Accordingly, the present invention provides a data control subsystem that uses separate queues and queue processor sets for ADM and I / O requests, respectively.
Supports a data control subsystem that uses the same set of queues and queue processors for both M and I / O requests.

The ADM subchannel, unlike the input / output subchannel, has no path restrictions. Which AD
The M processor also has access to all paths within or between electronic storages, and between all ADM queues and the ADM processors, the AD from any CPU.
Full flexibility is provided for processing M requests, and all electronic storage can be made accessible to any request via any ADM subchannel. I / O subchannel routing, on the other hand, requires that the I / O processor pass I / O requests to I / O processors that have one of the available designated paths.
Thereafter, this request is given to the path processor (channel processor) to complete the input / output operation. When the path control for the ADM operation is removed, the ADM processor can complete the ADM operation without requiring a path processor.

The present invention provides a two-stage workload balancing. Initial workload balancing causes the ADM subsystem to evenly distribute CPU requests among ADM processors. The ADM subsystem controls the assignment of particular ADM requests to particular ADM processors. Final stage workload balancing is provided within the subsystem.
Because CPU requirements can vary from single data transfers to extremely large transfers, the subsystem execution time can vary significantly. As the workload execution progresses in the subsystem, the work is continuously moved from the ADM processor in use to the ADM processor in the idle state so that all A
By keeping the DM processor continuously in use, the actual workload variation is perfectly balanced. With a separate queue and processor and a shared queue and processor, if the processor associated with the queue is not busy when the queue receives an ADM request, that processor will immediately
Execute the DM request. If the processor associated with the queue is busy when the queue receives an ADM request, the present invention transfers the waiting ADM request to the busy processor to the queue of another processor that is not busy. By providing ADM workload balancing, the processor executes the ADM request immediately.
When all processors associated with a queue are in use and any queue receives an ADM request,
The associated processor pauses between the sub-units of work and moves its ADM request to a common queue (CQ). The CQ is processed by any of the processors associated with the queue as each processor associated with the queue completes the request and looks for a new work request to execute. The processor looks at the CQ header to see if the CQ is empty. If the CQ is not empty, the processor immediately moves the waiting ADM request from the CQ to the processor's queue and from this queue the ADM request.
Perform the request.

Thus, the present invention continually redistributes waiting ADM requests between its queue and the processors so that all ADM requests are quickly executed by the processor associated with the queue. . Thus, an ADM request can complete its execution long before the processor associated with the queue is available for its processing. That is, if the AMD request is executed immediately by any available processor, or while waiting for a minimum of time in the common queue, while all processors are busy, by the first available processor. Because it is good. This redistribution of work requests results in complete workload balancing for all ADM requests. There is little interference with I / O requests handled by the same queue and processor. This is because a queued I / O request is processed by the processor associated with the queue as soon as the current subunit of work is completed.

Further, the present invention provides that the QE
ADM for each QE when used as DM request
Provides a recovery function. The ADM recovery function is realized by a checkpoint processing field in the QE and a recovery process for using the checkpoint processing field. The checkpoint processing field stores the information in the QE to locate the last page successfully moved by the failed processor during execution of the ADM request. If any processor fails during the execution of a page move operation, this processor signals all other processors associated with the queue of their fault status and identifier. The processor associated with the queue that first detects this fault signal becomes the recovery processor by accepting the fault signal. The recovering processor resets the failed processor, adds one to the retry count in the associated queue header, compares the count to the maximum allowable retry count, and if less, returns the fault. Establish conditions that cause the generated processor to retry the operation from the last successfully completed work subunit. If not, the failed processor is halted and removed from the operational subsystem, and its work is redistributed to other processors via subsystem workload balancing.

In attempting to recover, the recovery processor accesses the checkpointing field of the QE being processed by the failed processor and uses the data in the checkpointing field to generate an incomplete ADM request. Reestablish execution of the request from the last successfully completed subunit of work until successful completion.
If the failed processor cannot recover,
The E element is placed in the associated queue of the recovery processor.
The recovery processor can then complete the work request or place the QE in the CQ and let the processor that completed the request in progress complete it first. In each case, the operation starts with a checkpointed state. This differs from I / O processing because any ADM QE on the associated queue or running can be executed to successful completion by any processor in the subsystem. When a processor is removed by the recovery process, to determine the queue assignment for new requests (by the CPU) for the queue remaining after recovery, and to change this if necessary,
The QE is searched.

With this recovery function, ADM operation can be fully recovered in a manner transparent to the rest of the computer system outside of this subsystem and without interrupting work being performed by this subsystem. . During periods of high demand, the subsystem may operate with fewer processors, and thus may slightly slow down subsystem operation.

The present invention can be used to remove any processor or add a new processor to a subsystem at any time as long as at least one ready processor remains in the subsystem.
It also provides an ADM dynamic reconfiguration function. Reconfiguration includes re-assignment of QEs to queues and their processors remaining after the reconfiguration. In the present invention, the respective headers of the queues (for processors to be removed) that are removed by the reconfiguration operation are marked by setting the ready field to a disabled state. All pending requests (QEs) on the disabled queue are moved to other queues that remain operational (including the common queue).
This QE move operation can be performed by a processor assigned as a reconfiguration processor that processes the command in the reconfiguration command. Also, in the present invention, the header of each queue (for the added processor) added by the reconfiguration operation is marked by setting the ready field to the disabled state.

In the reconfiguration process, the processor associated with the queue searches all QEs to determine a queue assignment to the queue remaining after the reconfiguration, and changes this if necessary. Need to do. When a processor is logically removed from a subsystem (a processor is removed), its queue is also removed and the reconfigured processor reassigns the deleted processor's QE to the remaining processor queue. In the case of adding processor queues, the subsystem may reassign a portion of the QE from the previous existing queue to each new processor queue. A workload balancing function that increments the associated Q (queue) ID and a function that allocates work to idle processors assigns the added processor a pending QE.

Thus, performing the workload balancing, recovery, and reconfiguration operations of the present invention does not require the involvement of other parts of the computer system or software within the computer system ( The ADM requests are redistributed into the ready queue and the common queue (including that no involvement by the software operating system is required).

[0026]

【Example】

CPU Operation (FIG. 1) FIG. 1 illustrates the offload of asynchronous data movement management operations from a plurality of CPUs 1 to N to a CPU offload subsystem 20 to transfer data to and from electronic memory 21 or electronic memory 23. CPU to move pages
FIG. 1 shows a computer system including an offload subsystem 20 and an input / output subsystem 22 including input / output channel paths, input / output switch units, input / output control units and devices. The electronic memory 21 is a system main storage device 21 (sometimes called MS), and the electronic memory 23 is an extended storage mechanism (sometimes called ES).

Each CPU uses the S / 390 Start Subchannel (SSCH) instruction to place the queue element (QE) assigned to the subchannel in the subsystem's queue. The SSCH instruction operates in a conventional manner for I / O and ADM requests.

In both cases of an I / O request and an ADM request, the CPU execution of the SSCH instruction accesses the ORB (operation request block) specified by the second operand. The sub-channel ID number is designated by the general-purpose register 1 (GR1). The SSCH instruction calls the microcode in that CPU to cause the CPU offload subsystem 2 assigned to each identified subchannel to
The queues assigned to the QEs are accessed using the priorities disclosed herein in each queue by accessing the queues in each of the queues in the respective queues.
Chain. The fields in the header of the queue are set to the address of the current bottom (last) QE of the queue and the address of the current top (first) QE of the queue.

Each QE in any queue represents a "unit of work" to CPU offload subsystem 20, which is the queue offload processor (QOP) associated with the queue containing that QE. Is a request to transfer the indicated number of pages between the source and destination addresses identified in the QE.

The execution of the SSCH instruction depends on the Q
E is chained as the last QE in the identified queue, and is complete after the CPU signals the associated QOP that a new queue element (QE) has been chained to that queue. If the QOP is not busy at the time, it immediately accesses the first QE in its associated queue (in the preferred embodiment),
Start its execution. If the new element is the only element in the queue, the signaled QOP accesses the new QE to get its next unit of work. If the QOP is busy, it discovers the new request by performing a test after completing each work subunit.

Subsystem Operation (FIGS. 1 and 2) The CPU offload subsystem 20 of FIG. 1 includes a set of queuing offload processors (QOPs) and a QOP.
(A "QOP queue" herein)
) And a common queue (CQ). CPU
Puts the requests in the QOP queue, and the QOP removes these requests from their respective QOP queues and executes them or moves them to other queues. Each CPU
Requests are enqueued in the form of queue elements (referred to as QEs) that are chained to (addressed in the queue). ADM or I / O requests from the CPU can be chained to the queue with the subchannel as a queue element (QE). Thus, the QOP is an offload subsystem processor that performs asynchronous data movement processing in response to queued CPU requests. The CPU request is an input / output request or an ADM request for moving N pages in or between the electronic memory 21 or the electronic memory 23. That is, each QOP performs one or more processes required by each received CPU request, whether for input / output processing or ADM processing. The ADM processing performed by the QOP includes ADM execution control, load balancing, recovery, and reconfiguration.

FIG. 2 shows the CPU offload subsystem 20 in more detail. Each queue element has a field set by initialization to indicate whether the requested subchannel operation represents an I / O request or an ADM request. The CPU places I / O or ADM requests at the bottom of each QOP queue. Each QOP finds the next unit of work by accessing the QE located by the address in the "Top Q PTR (Queue Top Pointer)" field of its associated queue header. A unit of work is represented by either an I / O QE or an ADM QE chained in the queue. If the "Top Q PTR" field contains the address of the header, the queue is empty. If not empty, the processor returns the Q at the head of the queue.
Access E and change the contents of the "Top Q PTR" field to the address of the next QE in the queue. If there is no next element, the processor writes the header address. The current unit of work is unchained from any queue when it tries to execute it.

When a QOP completes an I / O request or ADM work unit (in other words, completes an entire ADM request), it looks at the common queue (CQ) header to determine whether the CQ is empty. Find out. If the CQ is not empty, the QOP moves the first QE in the CQ to the top of the queue for that QOP and returns to queuing. When moving a QE, or when there is no QE in the CQ, the QOP looks at its queue header to see if it is empty. If the queue is not empty, the QOP executes the QE at the head of the queue. All new CPU requests are placed at the bottom of the queue. Thus, by putting a QE in each queue and removing it from it,
Maintain the priority of QE execution on all queues,
Attempt to process the QEs as close as possible to the arrival order.

The input / output processing executed by the QOP includes:
It is a normal IOP process performed by a normal IOP (input / output processor) found on IBM mainframes, such as the IBM ES / 9000 M900 system and the earlier S / 3090 system.

The ADM processing performed by the QOP is as follows:
It is the subject of the present invention. The common queue (CQ) in the CPU offload subsystem 20 is used only for ADM processing and is available for all QOPs.

The QOP checks for pending ADM requests or pending I / O requests after completing a unit of work and after completing each unit of work during execution of the unit of work. The QOP checks the queue by looking at the header of the queue to see if a new request has been placed on the queue. If there is a new request in the queue, the QOP checks whether it is of the I / O type or of the ADM type. If it is of the input / output type, the QOP is
Process this by forwarding the PU request to the channel processor and return to ADM work on the subsystem queue.

If the new request is of the ADM type, the QOP attempts to pass the new request to an idle processor if one is found. This checks the QOP busy pointer in the CQ header,
This is performed by determining whether there is an idle QOP. The checked QOP then transfers a new ADM request (QE) from the head of the queue to the bottom of the idle QOP queue and signals the idle QOP. If the checking QOP cannot find an idle queue, it places its new ADM request in the CQ and returns to its processing. Thereafter, the inspected QOP continues its processing whatever it was processing at the time of pausing. Q
When the OP enters an idle state, it checks the CQ header for an empty state. If the CQ is not empty, the QOP fetches the head CQ request and moves to the head of the queue.
The CQ request is taken from the head of the queue as the next unit of work for this QOP. If the CQ is empty, the QOP then checks its own queue for work to do. If there is nothing, the QOP goes to a standby state.

QOP Operation Normally, a QOP removes the first subchannel QE from its associated queue and executes that QE to perform one unit of work. Execution of the QE transfers a specified number of data subunits between the two specified positions in the queue element. The two locations are addresses in the same electronic storage medium, or addresses in two different electronic storage media in the system. These operations are, for example, a "work unit" is the transfer of 10,000 pages of data between the MS and the ES, or the transfer of 38 pages of data between two locations in the MS. That is, the transfer of each page is an example of the “work subunit”. A work unit is equal to a work subunit only when the work unit specifies a single subunit transfer.

The QOP pauses each time it completes a work subunit. During this pause, the QOP looks at the queue head pointer in its queue header to see if there are any QEs waiting in that queue. A waiting
If there is a DM QE, the dormant QOP temporarily switches from the sub-unit transfer operation to look for an unused QOP in the subsystem. If an unused QOP is found, the dormant QOP moves the waiting QE to the unused QOP queue and places it in the unused QOP.
Signals that there is a QE in its associated queue. If all QOPs are found to be in use, the stopped QOP moves waiting QEs to the lower end of the common queue (CQ).

In normal operation, if there is no work in the CQ or associated queue, the QOP is
Stay idle until notified that the DM QE has been placed in the queue.

AD between the QOP queue and the common queue
By performing load balancing redistribution of the MQEs, all QOPs are kept continually in use as long as the CPU places the QE in any queue in the subsystem.
This method of operation provides the highest processing speed for all work supplied to the subsystem as compared to ADM request processing for subsystems with non-load balanced queues.

Queue Element (QE) (FIG. 3) FIG. 3 is a diagram representing a control block, QE, stored in a protected electronic memory mechanism associated with a subchannel.

The QE used by the present invention may be a control block associated with a particular subchannel (pointing to a subchannel) or a control block having a pointer field for chaining to various types of queues. The channel itself may be used.

In this embodiment, each QE is "lock (lock)", "subchannel ID (subchannel identifier)", "typ"
e (type) "," busy ID (busy identifier) "," Current
“Q ID (current queue identifier)”, “Current Q PTR (current queue pointer)”, “Current Qchain PTR (current queue chain pointer)”, “assigned Q ID (assigned queue identifier)”, “Checkpt Subunit Data (Checkpoint Subunit Data) "," Channel Program Addr
ess (channel program address) "and" statu
s (situation) "field.

The "lock" field is set on to alert other QOPs and the CPU when accessing the QE to change one or more fields.

The "subchannel ID" field stores the ID number of the associated subchannel.

The "type" field indicates that the QE is
Indicates whether it is E or ADM QE. If neither, it is not a request processed by the QOP subsystem.

The "busy ID" field identifies the QOP currently accessing this QE. The "current Q ID" field identifies the current queue containing this QE.

The “current Q PTR” field contains this QE
Address the queue header of the queue containing the. This field is cleared while this QE is not in any queue.

The "Current Q chain PTR" field addresses the next executed QE in this queue. This field has a special value if this QE is the last QE in the queue. This field is cleared while this subchannel is not in any queue.

The "assigned Q ID" field identifies the QOP queue to which the CPU will assign this QE.

In the "Checkpt Subunit Data" field,
1) Valid bit (V) subfield set to ON when all subfields in "Checkpt Subunit Data" are valid. 2) Access to current ADM CCW (channel command word) in current ADM program. CCW subfield containing address; 3) current ADM C
A MSB sub-field containing the address to the current move designation block (MSB) that specifies the sub-unit move parameters of the CW; Contains multiple subfields, including fields. The “Channel Program Address” field of the QE stores the address of the ADM channel program obtained from the ORB of the SSCH instruction call. For an I / O request, the address of the required I / O channel program is stored in this field. In the case of an ADM request, the address of the required ADM program is stored in this field. An “ADM program” is a list of ADM CCWs in the memory.

The "status" field stores status information about the ADM work unit that is reported to the requesting CPU when the work unit is completed and placed in the interrupt queue.

QOP Queue Header (FIG. 4) FIG. 4 shows the important fields used in the header of each queue associated with the QOP. Each queue has
Having a header to anchor the queue to an address known to all CPUs and QOPs, so whenever those CPUs and QOPs need to access the queue, access the header associated with it I can do it. Each header of the QOP queue has the fields used in this embodiment: a lock field, enable
Fields include a retry count field, a top Q PTR (top queue pointer) field, and a bottom Q PTR (bottom queue pointer) field. The lock field is set whenever you change a field in this header. The enable field may be a single bit field that is set on when the associated queue is enabled and off when the associated queue is disabled. In the retry count field, the relevant QO
Stores the current number of errors that P has encountered within a predefined time window. The top Q PTR field stores the address of the QE at the head of the associated QOP queue (the QE currently having the highest priority in that queue). This is the next QE to be performed on this queue. When the queue is empty (no QE), top
The address of the header is stored in the Q PTR field.

The bottom Q PTR field contains the Q which is at the bottom of the queue and has the lowest priority in that queue.
The address of E is stored. This is the last QE that is currently running in the queue. bott
The om Q PTR field is accessed to queue the next QE.

Common Queue Header (FIG. 5) FIG. 5 shows the fields in the common queue (CQ) header used by all QOPs in the subsystem. Only the ADM QE is placed in the CQ. The CQ header (CQH) contains the fields used in this embodiment, namely the lock field, the QOP0 busy PTR (QOP
0 in-use pointer) to QOPy busy PTR (QOPy in-use pointer) field, top Q PTR field, and bottom QPTR field.

The lock field is set whenever the CQH is changed. QOP0 busy PTR or QOPy busy P
Each TR field contains the ADM QE currently being executed (last removed) by the respective QOP.
Is stored. The QE address in this field indicates the busy state of each QOP. QOP0 bus
The contents of each of the yPTR or QOPy busy PTR fields are cleared (empty) if no QE has been processed by the respective QOP.

The top Q PTR field addresses the QE at the head of the CQ (the next QE to be executed in that queue), and addresses the CQH when the CQ is empty.

The bottom Q PTR field addresses the QE at the bottom of the queue. This is the last QE to be executed among the QEs currently in the CQ. This is C
This is a field that is accessed to put the next QE in Q.

CPU Request for Subsystem Services (FIG. 6) FIG. 6 illustrates the process used by the CPU to place a work unit in any of the QOP queues. In this process, the CPU chains the QE to the bottom of the QOP queue determined by the queue assignment in the "current Q ID" field of the QE. A CPU request can request both an input / output work unit and an ADM work unit.

In the first step 50 of FIG. 6, any one of the CPUs
H) "instruction to make a request for a unit of work to the QOP subsystem. The first of this SSCH instruction
The operand is a sub-channel ID number specified by the general-purpose register 1 (GR1). The processing shown in FIG.
It is similar to the usual process used to start an I / O device on the M company mainframe. In the latter case, the CPU
A signal that chains the subchannels specified in the IOP queue specified by E as a queue element (QE) and instructs the IOP (input / output processor) associated with the queue to process the new queue element. Send.

Next, at step 51, a normal SSCH instruction is executed, including the running exception test as performed in the prior art. The QE is tested by the microcode early in the execution process for validity and operability. If these tests indicate that the QE is not valid or not operational, then go through the "exception" path to step 52 and end the process. If these tests indicate that the QE is valid and operational, then proceed to step 53, where the CPU chains the QE to the bottom of the queue specified in the QE's "assigned Q ID" field. I do.

Next, at step 54, the CPU microcode provides a signal to the QOP associated with the assigned queue indicating that a new QE has been placed on that queue. This signal allows the QOP to immediately process this QE if it is not busy performing other work. The subchannel operand of this SSCH instruction is
At this time, it is represented by the QE on the assigned QOP queue.

The CPU execution of the SSCH instruction is performed in step 5
A condition code of 0 is set at 5 (CC = 0), and the process is terminated by indicating to the CPU program that this instruction has been successfully completed. The CPU program is now free to execute the next instruction, and the next instruction need not have a relationship with this SSCH instruction.

Processing of Queue Elements (FIG. 7) The processing of FIG. 7 is started for each QOP when the QOP first receives a QE signal from the CPU indicating that the work unit has been queued. By the QE signal, Q
The OP's bistable latch is set on, indicating that the QE signal has been received (this latch remains on until the QOP finds its queue empty and sets the latch off). First, the process proceeds to step 61A to access the queue header and test whether or not the address of the header is stored in the "top Q PTR" field, thereby performing a test on the queue empty state. If empty, in step 61B, the QE signal receiving latch is reset to indicate the QE signal non-receiving state. The "top Q PTR" field in the header of each queue stores the address of the QE currently at the head of the associated queue. If the content of the "top Q PTR" field is equal to the address of the queue header, the queue is empty (QE
No).

If it is determined in step 61A that the queue is not empty, then the NO path proceeds to step 61, where Q is addressed by the "top Q PTR" field.
Remove the E subchannel. When removing a QE subchannel from a queue, write its "Current Q Chain PTR" field (which points to the next subchannel in the queue) to the "Top Q PTR" field of the queue header,
Overwrite the previous content. The new "Top Q PTR" field points to the next subchannel in the queue currently at the top of the queue. If the next subchannel is not in the queue, this field points to the queue header. Next, in step 62, it is determined whether the removed QE subchannel is an ADM QE or an input / output QE. If it is not an ADM QE, the process proceeds to step 63, where the input / output QE is processed, and normal input / output processing is executed. If it is determined in step 62 that the removed QE is an ADM QE, the YES path proceeds to step 65, in which the Busy PTR field of the QOP in the CQH is set, and the Busy ID field of this QE subchannel is set. Set to the identifier of this QOP. This QOP is currently processing the ADM subchannel and is in use.

Next, at step 66, "EXECUTE" in FIG.
(Execution) The process branches to the process, and the work unit is executed one subunit at a time. After the execution of the work unit is completed, the process proceeds to block 67.

Block 67 includes a set of housekeeping steps performed upon completion of a unit of work. These housekeeping steps include CQH's "QOP
Busy PTR "is cleared (set off). Also, since the subunit does not need to be checkpointed after the unit of work is completed, either clear the" Checkpt Subunit Data "field for this subchannel, or Either set its V bit off, or both, and in step 67 the QO for this subchannel
Also clear P Busy ID. It also increments the assigned Q ID to the next available QOP. As a result, the next S
On the SCH, the QEs will be placed in different QOP queues.

In step 67, the subsystem (AD
CP as input / output type interrupt indicating M subchannel
An ADM interrupt signal (presented to U) is generated and sent to indicate to the CPU that the requested ADM data transfer operation has been completed.

Thereafter, at block 67, "G" shown in FIG.
ETWORK "process, which causes the current QOP to check the common queue for the next unit of work if the CQ has a waiting QE subchannel. The processing of 7 is ended.

Process EXECUTE (FIG. 8) In FIG. 7, when the “execution of EXECUTE” of step 66 is reached,
The process branches to the EXECUTE process in FIG. This EXECUTE process will execute the current AD represented by the QE currently being removed.
Controls the execution of M work units (eg, moving pages of data). In the EXECUTE process, checkpoint processing data is stored in the "Checkpt Subunit Data" field of the subchannel, and this is set effectively for each subunit of work that has been successfully completed.

The EXECUTE process starts by proceeding to step 70, and first checks the state of the valid bit (V) of "Checkpt Subunit Data". If the valid bit is set off, the current QE
ta is indicated to be a new request without previous checkpointing data, the NO path proceeds to step 72, where Checkpt Subunit Data is set to represent the first subunit of the work, Initialize the contents of

If it is determined in step 71 that the valid bit is on, the subunit to be performed next is not the first subunit but proceeds to step 73 from the YES path. At step 73, the next sub-unit of work (eg, moving the next page requested by the current QE request defined in Checkpt Subunit Data) is completed.

Thereafter, in step 74, after the execution of the subunit is completed, a checkpoint process for the subunit is executed. This is 1) Step 73
Total number of sub-units of work performed so far on the current MSB, including the sub-unit completed in 2), 2) the address of the MSB specifying the currently completed sub-unit, and 3) the ADM specifying this MSB. This is performed by storing the address of the CCW in "Checkpt Subunit Data" and 4) setting the valid bit to the ON state.

Next, at step 75, a test is made to see if there are more work subunits to be performed on the current work unit. If step 75 detects that the last completed subunit is not the last subunit to perform for the current QE request, there are still subunits to perform. Therefore, from the YES route, step 75
Proceed to A to check for other QEs by executing the CHECKQUEUE process (FIG. 9). When the QOP queue has been examined and all QEs have been processed, the process returns to step 73 of FIG. 8 to execute the next work subunit for the current QE, and then step 74
Stores the checkpoint processing data when it has been successfully completed. The repetition of returning to the step 73 includes the MSB of the ADM program for this QE subchannel.
Until all of the ADM programs (representing one CPU request for the ADM) have been executed, this involves having the ADM program retrieve the next MSB and the next ADM CCW of the ADM program associated with the current QE. When it is detected in step 75 that the last sub-unit for this work unit has been completed, the NO path proceeds to step 76. In step 76, the stat of the currently running ADM QE
Set the us field. This stat of the current ADM QE
The us field is set to indicate successful completion. In step 77, the process returns to the process in FIG. 7 in which the "EXECUTE" process in FIG. 8 is called. The processing in FIG.
Proceed to.

CHECKQUEUE Process (FIG. 9) The "CHECKQUEUE" process of FIG. 9 enters point 78A from the "YES" path from step 75 of FIG. 8 to check for other pending work. At step 78K, a test is made for holding the recovery signal, and if this processor becomes the recovery processor, branch to step 78M to process the recovery action. If no recovery signal is pending,
The NO "path proceeds to step 78L, where a test is performed on the pending reconfiguration signal.
If the pending reconfiguration signal is active and this processor becomes the reconfiguration processor, the "YES" path proceeds to step 78N to process the reconfiguration request. If no reconfiguration signals are active, then the "NO" path proceeds to step 78B.

If either signal is picked up by the processor, that signal is tested in one operation and set off so that the other processor does not respond to this signal. At step 78M, the recovery process (FIG. 12) is called, and when this process is completed, the process proceeds to step 7 of FIG.
Return to 8B. At step 78N, the reconstruction processing (FIG. 11)
And thereafter, when this process is completed, the process returns to step 78B of FIG.

Next, step 78B tests whether the queue for this QOP is empty. If empty, "
YES "Proceed to step 78H from the route, and
Terminate the process. If it is not empty, the process proceeds from the "NO" route to step 78C, and removes (removes) the head QE from the queue. Next, step 78D tests whether the removed QE is an ADM QE. Otherwise, this is an input / output QE, and the process proceeds from the NO path to step 78P to execute a normal input / output process.

If this is an ADM QE, "YES"
Proceeding to the step 78E from the route, and the QE
Find another QOP that can fulfill the request. Note that the current QOP is executing an incomplete unit of work and is currently in use when it paused at the end of the last subunit to perform the "CHECKQUEUE" process while the unit of work was executing. I want to. Therefore, the current QOP cannot execute this dequeued QE at this time.

At step 78E, another QOP is (ADM
If you find that you are idle and have the queue enabled (because you are not doing any work), then "Y
From the "ES" path, go to step 78F to place the removed QE in the QOP queue of the idle QOP.
An E signal is sent to indicate to the idle QOP that the QE has been queued. Thereafter, the process returns to the EXECUTE process in FIG.

If no QOP enabled in the idle state is found in step 78E, the flow advances to step 78J. If the QE has valid Checkpt Subunit Data, the QE is put at the head of the CQ, and Checkpt
If it does not have Subunit Data, it is placed at the lower end of the CQ. Thereafter, the process returns to the process EXECUTE in FIG.

GETWORK Process from Common Queue (FIG. 10) When the “GETWORK execution” step in FIG. 7 is reached, a branch is made and the “GETWORK” process of step 80 in FIG. 10 is entered. In the "GETWORK" process, the common queue header (C
QH) and test its "Top Q PTR" field to determine if the CQ is empty. If the CQ is empty (not including the QE), the contents of the "Top Q PTR" field include the address of the CQ header. If a valid address is not included therein, step 83 returns to step 67 of FIG. However, if a valid address is included therein, at step 82, the address is used to remove the leading QE from the CQ and obtain the next QE following the CQ,
Put the QE at the head of the QOP queue.

Thereafter, in step 83, the process proceeds to step 67 in FIG.

Reconfiguration Process (FIG. 11) The ADM subsystem allows a human system operator to enter commands into a computer system to remove or add one or more QOPs, each having an associated queue. Thus, it can be reconfigured.
This can occur, for example, when subdividing a multi-processing system into multiple independent images or systems. Each QOP must remain part of the reconfigured system part where the QOP physically resides. Requests in progress and requests already waiting must be handled by the portion of the system where the operating system that started it resides after reconfiguration. Requests that are in progress on a QOP that leaves the system part where the currently executing operating system continues to execute must be reassigned to the remaining QOP in that part. The CQ is also left as part of the rest. If the reconstruction involves the addition of elements previously removed by the reconstruction, the additional QOP is
Become part of the P subsystem. The reconstructed QOP removes the QE from the CQ if a QE exists, and the added QOP
Send a signal to If there is no QE on the CQ, the added Q
The OP waits for a signal.

Each reconfiguration command is supplied to the ADM subsystem in the computer system from either the CPU or the service processor. The reconfiguration commands are referred to herein as the change QOP offline command and the change QOP online command, and may be entered by an operator to remove or add one or more QOPs of the subsystem. In this embodiment, one QO is changed by the QOP online change command.
P is added to the QOP subsystem, and a QOP offline change command removes one QOP from the QOP subsystem.

FIG. 13 is a diagram showing the QE signal / recovery / reconstruction bus 110 connected to all QOPs in the subsystem. The QE signal / recovery / reconfiguration bus 110 is also connected to the reconfiguration signal means 111, through which the operator can supply reconfiguration command signals to all QOPs.

The change QOP offline command and the change QOP online command are dynamic commands that can be issued and executed while the subsystem is in use, and the subsystem is in any operational state when the QOP receives the command. You may. That is, an off-line change command that removes a QOP can be performed while the QOP is performing QE, without revealing the destruction of the QOP subsystem to the rest of the computer system. Also, the command is which ADM QO
The result of the execution of the P work unit is not adversely affected.

If an off-line change command is issued for a QOP to delete it from a subsystem while the QOP is executing a unit of work, the "Checkpt Subunit Data" field of the QE will contain Used to properly control the switching of the execution of the QE from a deleted QOP to a QOP that remains an operational QOP for the same operating system after execution of the reconfigure command.

When a QOP is added or deleted by a reconfiguration command (as is done in this embodiment),
The operator uses a series of commands to create the desired number of QOPs.
Can be added or deleted. However, multiple QO
Obviously, by repeating the reconstruction process for one QOP a specified number of times to process a P command, the number of QOPs specified by a single reconfiguration command can be removed or added.

The QE signal / recovery / reconstruction bus 11 of FIG.
The command information sent on 0 indicates whether to perform an add operation or a delete operation, and the Q to be added or deleted.
Specify the OP identifier. The QOP that first finds the reconstructed signal performs the reconstruction process. This can be any QOP that remains operational after the completion of the reconstruction process.

This command information is detected from the QE signal / recovery / reconstruction bus 110 and stored in the identified QOP to be added or deleted (referred to as an added QOP or a deleted QOP) and the identified reconstructed QOP. Is done.

Thus, the change QOP offline command identifies and designates the QOP to be removed as a "delete QOP" and uses one of the remaining QOPs in the subsystem as a "reconstructed QOP".

Which Q in the queue associated with the delete QOP
E also rebuilds the QOP from the queue associated with the deleted QOP.
Is moved to the queue associated with. If the delete QOP queue is empty, the QE is not moved. But delete QOP
If the queue is not empty, the QE of the deleted QOP is moved to the reconfigured QOP queue. The QE move process is performed by a reconstructed QOP in the preferred embodiment.

In the QOP online change process, a QOP is added to a subsystem. The QOP to be added is physically added to the subsystem before executing the processing in FIG. The add command identifies and specifies the QOP to be added, and the reconfigured QOP performs the add process. This process sets up a new queue header associated with the QOP to be added. The ID of this added QOP is written in the header by the reconstructed QOP. The online change command is a QOP added from the CQ if the QE is pending in the CQ.
Move QE to queue. When the queue of the added QOP is enabled, "as" in step 67 of FIG.
The "signed Q ID increment" automatically starts allocating work to the queue of added QOPs.

FIG. 11 is a diagram showing processing performed by a QOP that accepts a reconstructed signal. Step 90 is entered after receiving a QOP change command to add or delete one QOP. Then, step 91
Then, it is determined from the command operation signal whether the command is an online change command or an offline change command.

"Delete" in the case of an offline change command
Proceed to step 92 by route. In step 92, delete QO
Set the enable field of P's queue header to the disabled state. At step 92, all subchannels in the queue for the deleted QOP are then moved to the queue for the reconstructed QOP, and if the reconstructed QOP returns to the idle state, a signal is sent to the reconstructed QOP. In step 92,
Finally, the deletion QOP is stopped. Next, step 93
Then, if the "QOP Busy PTR" field of the deleted QOP in the CQ is accessed, and the field contains the address of the "checkpointed sub-channel" that was being executed when the deleted QOP was stopped in step 92, Read this.

The checkpointed QE has been dequeued from the delete QOP queue to begin its execution and is therefore not part of the delete QOP queue. Therefore, in step 93, the reconstructed QOP is
The checkpointed QE is queued for the reconstructed QOP and signaled to the reconstructed QOP so that the QE can be re-established by the reconstructed QOP or later.
Will be continued at a later time by another QOP on another queue to which it will be moved. Then, reconstruction Q
The OP clears the "QOP Busy PTR" field of the deleted QOP in the CQ, resets the QE Busy ID in the QE, removes any association with the deleted QOP, and step 97.
Proceed to. In step 97, the process proceeds from the idle state to step 90.
When entering, it returns to the idle state. Otherwise, since step 91 was entered from step 78N of FIG. 9, the process returns from step 97 to step 78B of FIG.

In the QE that has undergone the checkpoint processing, it is determined whether or not the reconfiguration has occurred during the execution of the QE based on the valid bit included in the state of “Checkpt Subunit Data”. If the V bit indicates that valid checkpoint processing information is present in the QE, it has occurred. In that case, any operational QOP will later use this checkpointing information to continue from the last successful subunit indicated in the checkpointing data until its QE execution is successfully completed, The execution of the QE can be completed. Delete Q
The OP can turn off its power. Since the operation is no longer needed in the subsystem.
It is then exchanged within the QOP subsystem, or performs maintenance while it is in or out of the subsystem, or has a different QOP associated with other parts of the system consisting of the original system. Can be part of a subsystem. The QEs assigned to the associated queue of the deleted QOP will be able to route future work to the remaining QOPs in that subsystem,
Reassigned to the queue associated with the OP.

Finally, proceeding from step 93 to step 97, the reconfiguration processor can continue its normal operation by returning to the previous state. At this point, the reconfiguration processing for the deleted QOP ends.

As long as one operational QOP remains in the system, successive off-line change commands
Any number of OPs can be reconfigured offline.

In the QOP online change command for adding a QOP to the subsystem, the "add"
Proceed to the route. The added QOP is physically added to the subsystem before executing the processing in FIG.

Step 94 sets up a new QOP header for the new queue associated with the new QOP to be added. In step 94, the additional QOP is then started by turning on power, if necessary, and enabling its QOP queue. The new QOP is put in an idle state. A QOP in this state will have a signal from the CPU indicating that the QE has been placed in its associated queue,
Or another Q that moved the QE to its associated queue
Wait for signal from OP.

If it is determined in step 95 that QE is included in the CQ, the flow advances to step 96. If the CQ is empty, go to step 97. In step 96, the first QE is removed from the CQ, and this QE is put in the queue of the added QOP.
Signal the added QOP. In step 97, when the process proceeds from step 78N, the process returns to step 78B. If the process proceeds to step 97 due to receiving a reconfiguration signal in the idle state, the process returns to the idle state and waits for another signal. This subsystem automatically allocates sub-channels and causes new queues to be added to new QEs in the future.

By successive online change commands,
Any number of QOPs can be reconstructed online.

Another way to vary the QOP off-line is to simulate the permanent fault condition of the QOP and then simulate the fault using the recovery process described in the next section of this specification. To remove the QOP.

Recovery Process (FIG. 12) The recovery process of FIG. 12 relies on each QPO internally having error detection capabilities equivalent to the latest processors currently in commercial use. Upon detecting an error condition in a QOP, the QOP having the error condition sends a recovery signal to another QOP via the QE signal / recovery / reconfiguration bus 110 of FIG. When this recovery signal is sent,
The recovery process starts from step 100 in FIG. An error condition is detected, for example, if a temporary error exceeds a predetermined threshold number of times or if a permanent error is detected in the QOP.

The first QOP that is ready to receive a recovery request signal on the QE signal / recovery / reconstruction bus 110 detects this signal and
Respond with an acknowledgment signal indicating that the acknowledgment QOP acts as a “recovery QOP”. This acknowledgment signal sent by the recovery QOP is recognized by other QOPs as an indication that they can continue normal processing operations independent of the recovery operation.

At step 101, the recovery QOP resets the failed QOP (referred to as the error QOP) and retry cop in the QOP queue header of the error QOP.
The unt field can be incremented to indicate the number of errors that have occurred in the error QOP.

Thereafter, the recovery QOP proceeds to step 102 to determine whether the reset of the error QOP was unsuccessful or a retry count (in the QOP queue header).
Detects whether the error QOP has exceeded the predetermined maximum value (N). (The subsystem uses any method, including methods well known in the art, to determine if the error QOP Has been determined, i.e., whether the process in which the error condition occurred for the N retries needs to be repeated, and a temporary error will remain even after the Nth retry of the process Is considered a permanent error condition if N remains or a reset fails, where N is an experience value set by experience with processor operation (eg, 2
0), reset periodically). This retry behavior is
Initiated by microcode in the recovery QOP, which restarts the QE process for the error QOP, as shown in steps 103-104.

After step 102, step 103
Then, the recovery QOP accesses the header of the common queue and reads the "QOP Busy PTR" field of the error QOP. This field stores the address of the QE being processed by the error QOP when the error condition occurred. In step 103, then, the "busy ID" of the QE
Set the field to the identifier of the error QOP to indicate that the QE is currently in use in the error QOP. Thereafter, the recovery QOP is set to "T" in the error QOP queue header.
Put this QE in the error QOP queue by setting the op Q PTR "field to the address of this QE, which is chained to the head of the error QOP queue.

Thereafter, the error QOP is signaled, so that the routine proceeds to step 61A in FIG. 7 to continue the normal processing. In step 104, the recovery QOP returns to normal operation and returns to step 78B of FIG. 9 or returns to the idle state to wait for another signal.

If it is determined in step 102 that the state is a permanent error, the process proceeds to step 105, where the recovery QOP is
Remaining steps 105, 106 and 104 of the recovery process
Execute

In this case, steps 102 to 1
Proceeding to 05, the recovery QOP accesses the header of the error QOP queue and sets its enable field to indicate an inoperable state. Thereafter, the recovery QOP moves all QEs in the queue of error QOPs to the queue of recovery QOPs, stops the operation of the error QOP,
Allow maintenance to be performed on it. Error QO
The QE assigned to P's associated queue is reassigned to the queue associated with the operational QOP in the subsystem. Thereafter, in step 106, the recovery QOP accesses the "QOP Busy PTR" field of the error QOP in the common queue header to obtain the address of the QE that the error QOP was executing when the failure occurred. This QE
Is put at the head of the recovery QOP queue and the recovery QOP
Receive a signal after the "busy ID" field of this QE has been reset. Because this QE is not currently running.

Finally, the process proceeds to step 104, where the recovery QO
If P is idle when it receives the recovery signal, it returns to the idle state. If not, this recovery is
Therefore, the process returns to step 78B of FIG. 9 to continue the processing of the activity QE.

The checkpoint information in the QE waiting at step 106 is used by the recovery processing. This QE is determined by the recovery QOP and
By another QOP when moved to the OP queue,
It is executed step by step. This QE's "Checkpt Subunit D
Using the contents of the ata "field, the execution can be restarted from the next subunit after the last successfully completed subunit operation, continuing until the execution of that QE's work unit is completed. While numerous variations and modifications have been shown without departing from the scope and spirit of the invention, it will be apparent to those skilled in the art that the embodiments described above are provided by way of example and not limitation. Please understand that.

In the present invention, each work request item is an ADM.
(Asynchronous data movement) Each work request item has a work type instruction for indicating a work request or an input / output device work request, and each work request item specifies a parameter for the work unit requested to be executed, and A work unit includes one or more ADM work subunits controlled by a queue processor for moving one or more data pages between locations in or between electronic memories, and the input / output work unit A plurality of processor queues respectively associated with a plurality of queue processors in a subsystem of the data processing system, wherein the plurality of queues are transferred to the input / output processor by the queue processor to control requested I / O work. Receiving a work request item as a queue element (QE) within the work unit; Testing during the line by the queue processor to determine if a new work request item has been received on the associated processor queue as a receive queue; and New I / O work found in the test step on the specified I / O processor if available to perform the operation, or on the standby I / O queue if the specified I / O processor is unavailable Transferring the request item from the receive queue; and when the queuing processor under test is in use by the ADM work unit and no other queue processor in the subsystem is in use, the other processor from the receive queue. Moving the new ADM work request item found in the test step to the queue , When there is an ADM work request item that is not in use by the queue processor and is not serviced on the associated queue, each queue processor will receive an ADM work request item on the associated processor queue. Initiating the execution of another ADM work unit. Controlling the asynchronous workload of data movement operations among a plurality of queue processors in a subsystem of the data processing system.

A test step further examines the header of the associated processor queue for an indication of a new ADM entry or new I / O entry received on the queue, temporarily diverting from the execution of the ADM work unit, and Examining a common control block containing busy state items of all queue processors of the other queue processors to determine if other queue processors are not currently in use and can process the new ADM entry. The load balancing method according to 0116, wherein

The transfer step further moves the new work item to a common queue accessible from all processors in the subsystem when all queue processors in the subsystem are indicated as currently busy. The method of 0117, comprising the step of:

[0119] The transferring step further comprises the step of initiating, by execution of any of the queue processors, ADM work request items residing on the common queue during execution of the ADM work unit. 0118
3. The load balancing method according to item 1.

In addition, the A currently being executed by each queue processor in each subsystem.
Configuring a common queue header to have a plurality of queue processor busy pointer fields for storing addresses to DM work request items, associating the common queue header with the common queue, and an associated queue. Setting the processor busy pointer field for the processor to the address of the ADM work request item being executed by the processor; and while the ADM work request is being executed by the associated queue processor, the Setting the respective processor busy state field, wherein both setting steps are performed at the start of each ADM work subunit.

The subsystem is prepared to recover from an unexpected interruption to processing by a processor in the subsystem, and another queue processor partially executes using the contents of the checkpoint data field. Checkpoint information for storing checkpoint information about the last successfully completed ADM work subunit by the queue processor so that execution of the completed ADM work request item can continue.
130. The load balancing method as described in 0120, comprising configuring each ADM work request item to have a data field.

The subsystem is prepared to recover from an unexpected interruption to processing by a processor in the subsystem, and configuration steps are further performed to checkpoint the last execution of the partially executed ADM work request item. Indicates whether the contents of the checkpoint data field are available to another queue processor to continue from the ADM work subunit that
0123. Load balancing method according to 0121, comprising providing a valid bit in the checkpoint data field.

The subsystem is prepared to recover from a failure by a processor in the subsystem, and the configuration step further stores a valid bits subfield and an address to the beginning of the ADM program specified by the ADM work request item. A control word subfield, a specified block address subfield that stores the address of a specified block that specifies subunit control parameters used by the associated ADM program, and a success before the currently executing ADM work request item. A plurality of subfields for storing checkpointed subunit data in each ADM work request, including a subunit number subfield for storing the number of subunits moved to Set in the data field That it is characterized in that it comprises a step, load balancing method as claimed in 0121.

The subsystem is prepared to recover from a failure by a processor in the subsystem, and furthermore, an error condition occurs when an error condition occurs during the process of executing the current ADM work request item on any of the queue processors. Sending an indication signal; retrying at least a portion of the processing that caused the error condition; and, if the error condition continues to exist after completion of the retry step, the current ADM work request on another queue processor. Performs recovery of the entry and, on the other queue processor, from the last successfully completed subunit indicated by the checkpoint data field of the current ADM work request entry to the current AD
0123, including processing the M work request item and continuing processing of the current work request item on the queue processor having the error condition if the error condition no longer exists during the retry step. The described load balancing method.

Further, upon completion of the work ADM unit processing by the queue processor, the queue processor accesses the common queue header to determine whether the ADM work request item exists on the common queue, Executing the item if the item is found on the common queue; and, if the ADM work request is not on the common queue, completing the processing of the ADM unit of work by the queue processor Accessing and executing the next ADM work request item from the associated queue by the processor, and, if the work item is not found on the common queue or on the queue associated with the queue processor, 0123. The load balancing method according to 0123, comprising:

In addition, the current A removed from the associated queue
Executing each work unit of the DM work request item by the queue processor; upon completion of each work unit, the busy state field of the associated processor in the common queue header and the busy state field in the ADM work request item. 0125. The load balancing method of 0125, comprising the steps of: clearing the ADM work unit and sending a signal to the central processing unit indicating successful completion of the ADM work unit.

The load of 0124, further comprising: checking the reconfiguration signal after completion of each ADM work subunit; and reconfiguring the subsystem if the reconfiguration signal is received by the subsystem. Balance method.

Further accepting the reconfiguration signal by an idle queue processor designated by the reconfiguration processor by sending an acknowledgment signal to another queue processor in the subsystem; Detecting from the reconfiguration processor an indication of which queue processor is to be added or removed from the subsystem from the reconfiguration processor.

The load balancing method of 0128, wherein the accepting step further comprises performing the accepting step during execution of the sub-unit of work by the reconfiguration processor.

In addition, disabling the queue associated with the queue processor designated to be removed from the subsystem by the reconfiguration processor; and removing all work from the associated queue of the removed queue processor. Moving the request item to a queue associated with an operable queue processor in the subsystem by the reconfiguration processor.

Further, the execution of the unit of work of the ADM work request item associated with the queue processor designated for removal by the queue processor designated for removal has been suspended by another processor. Locating ADM work request items associated with the designated queue processor to be removed by other queue processors when not completed at
The load balancing method according to 0130.

Further, using the checkpoint data field associated with the located ADM work request item, execution of that item is continued by another queue processor from the last successfully executed subunit. 0131. The load balancing method according to 0131, comprising the step of:

Additionally, configuring a queue header for the queue associated with the queue processor to be added to the subsystem, and adding the queue processor to the subsystem to associate the queue processor with the queue represented by the queue header. Writing the identifier of the queue processor to be performed to the queue header.

Receiving in a plurality of queues, each associated with a plurality of queue processors, a work request item specifying parameters for a unit of work requested to be executed by a queue processor in the subsystem; Executing, by each queue processor, a work request item on a queue associated with the processor so as to execute the unit of work by executing a plurality of work sub-units; pausing execution of the current work request item by the processor; Performing a test for a new work request item received on a queue associated with the processor during execution of the current work request item; and
Move the new work item that was found on the queue associated with the queue processor by the test step to another queue, and when all other queue processors in the subsystem are running, Moving the new work item to a common queue, where each item is accessible from all queue processors in the subsystem, the data movement operation between the plurality of queue processors in the subsystem of the data processing system. Load-balancing method for controlling asynchronous workloads on the server.

Further, as a queue element for storing information designating a work unit to be executed by the subsystem, an instruction for placing a work request item in a queue of the subsystem is provided in the central processing unit in the data processing system. 0134. The load balancing method of 0134, comprising: performing by the (CPU); and sending, by the CPU, a signal indicating that the queue element has been enqueued to a queue processor associated with the queue. .

Further, in order to reconfigure the subsystem, work request items are chained to a queue in the subsystem as a queue element, and information specifying a work unit is transmitted to the queue element by the queue processor in the subsystem. The instruction to write to the
Performing by one of the one or more central processing units (CPU) and sending by the CPU to the queue processor a signal indicating that the queue element has been placed in a queue associated with the queue processor. And while the subsystem performs the unit of work,
The method of claim 1134, further comprising: continuing to execute the simultaneously executed instructions by the CPU.

In addition, removing a queue entry (QE) from the queue at the memory location in the subsystem indicated in the queue header associated with the queue by the queue processor, and placing another QE in the queue. Recording the location resulting from the removed QE in the queue header, indicating the next QE that can be selected for execution in the queue if the QE is present, and relating to the queue when the QE is removed. If the queue processor is not busy, the processor executes the unit of work; if the queue processor is busy, the queue associated with the other queue processor is busy if no other queue processor is busy. Placing the QE in a queue and placing the QE in a common queue if all queue processors in the subsystem are busy. , Load balancing method as claimed in 0136.

Each work request item has a work type instruction for indicating an ADM (asynchronous data movement) work request or an I / O device work request, and each work request item has a parameter for the work unit requested to be executed. And the ADM work unit is controlled by a queue processor, where each work unit moves one or more pages of data between locations in or between electronic memories.
A subsystem of a data processing system, comprising one or more ADM work subunits, wherein the I / O work units are transferred to the I / O processor by a queue processor to control requested I / O work Allocating a set of asynchronous data movement (ADM) sub-channels to a plurality of respective queues within the PDU, and the subsystem using an ADM request specified by a sub-channel control block associated with the queue element (QE). When requesting an ADM working unit,
Executing a start subchannel instruction by the CPU to specify a DM subchannel identifier;
Chaining the QE to a queue assigned to the queue and sending a signal indicating the presence of the QE to the queue to a data control processor (DCP) associated with the queue; The QE on the associated queue is accessed by the signaled DCP to obtain the next unit of work specified by the QE, and data is transferred between locations in the same storage medium or between different storage media locations in the system. Executing the working subunits of the QE by the DCP by transferring the pages, and after the DCP has completed each working subunit, the DC
Testing by the DCP whether the QE is waiting in the queue assigned to P, and DCP all QEs found in the test step to other queues associated with other DCPs not currently in use And sends a signal to the DCP instructing it to begin processing QEs on other queues, and if no idle DCP is found, a test is performed to balance the workload between the DCPs. Moving all QEs found in the step from all DCPs to an available common queue (CQ) by the DCP, including any number of CPUs interfacing with any number of DCPs;
A load balancing method for controlling an asynchronous workload of a data movement operation between a plurality of queue processors in a subsystem of a data processing system, wherein P has an associated queue.

The load balancing method of 0138, further comprising the step of setting a status block with information regarding the status of the successful completion of the last work subunit executed by the queue processor.

Further, upon successful completion of the execution of a work item by any of the queue processors in the subsystem, a queue in the common queue header (CQH) is searched for an indication of a work item in the common queue. Accessing by the processor; locating the work item represented by the indication found in the common queue header; and a queue header associated with the queue processor when the queue processor is not executing another work item. Chaining the work items to a location in the associated queue header for storing an indication of the work item on the associated queue; and accessing the work items in the associated queue. Performing by a queue processor.
3. The load balancing method according to item 1.

In addition, to reconfigure the subsystem, a reconfiguration signal is sent to the subsystem by specifying the processor to be removed from the subsystem, and the signal is reconfigured by another processor in the subsystem that becomes the reconfiguration processor. Sending an acknowledgment signal by the reconfiguration processor to other processors in the subsystem to indicate that no other processor must accept the signal; and Indicating the last successfully executed work subunit for the work item that has been removed, setting the inoperative state with respect to the queue associated with the removed processor, and the queue associated with the removed processor. Rework all work items above for service by the reconfiguration processor. Moving to the queue associated with the configured processor and independent of the reconfiguration operation by the reconfigured processor and the removed processor, the other processes of all work items on the queue of each other processor in the subsystem. The method of 0139, further comprising: continuing execution by each processor.

[0142] The method of clause 0141, further comprising the step of continuing execution of all work requests on the common queue by each of the other processors in the subsystem independently of operations by the reconfigurable processor and the removed processor. Load balancing method.

Sending a reconfiguration signal to the subsystem by designating a processor to be added to the subsystem and designating another processor in the subsystem as a reconfiguration processor; Providing and enabling a queue associated with the processor being added to the subsystem by the process performed, and causing the processor to be added to the subsystem to operate by the process performed by the reconfigured processor. Starting with 0
139. The load balancing method according to 139.

Further, each indicates the position of each of the work items being executed by the queue processor,
And providing a plurality of busy status fields, each associated with a queue processor in the subsystem, to indicate when the queue processor is idle.
The load balancing method according to item [0138].

Further, in order to recover from a temporary error condition occurring in a processor in the subsystem, another queue processor is notified of an error condition by a queue processor having a temporary error condition, and the latter is regarded as an error processor. Sending a signal to specify
Reading the busy status field of the error processor by another queue processor to obtain the location of the work item being processed by the processor; and accessing the work request item by the other queue processor and retrieving the item. Queuing step associated with the error processor, and all remaining subunits for the unit of work represented by the work item, following the last successfully executed subunit indicated for the work request item. Resetting the error processor to its initial operating state by another queue processor by continuing execution so that the error processor can re-execute the item after the error condition no longer exists. The load balancing method of 0138, comprising:

The load balancing of 0145, further comprising the step of waiting for a work request item at a location in a queue associated with the processor having the temporary error condition for further processing by the error processor. Method.

The method further includes the step of returning to the load balancing method to check the queue header of the next work request item of the queue processor having the temporary error condition.
145. The load balancing method according to 145.

Additionally, disabling a queue associated with the queue processor having the signaled error condition to recover from an error condition occurring in the queue processor in the subsystem; Moving all queue elements from the queued queue to another queue associated with a ready processor in the subsystem, and the work request item being executed when an error condition occurred with respect to the work request item Reading the contents of the busy status field, available to all processors in the subsystem, to determine the status of the work request item. Operate all work subunits following the subunit executed at For the processor to process, so the incomplete work request item obtained from the queue of the error processor can process recovery processor, error
Placing the work requests of the processor's queue in an associated queue of the recovery processor.

In addition, to eliminate queue processors having a permanent error condition, operation continues during and after operation of the recovery method with all remaining operational queue processors and associated and common queues. 147. The load balancing method of 0148, comprising the step of:

And performing the processing on any of the ready queue processors in the subsystem to return to any of the following processing operations present for the queue processor having the error condition.
The load balancing method according to 0148.

Providing a plurality of data control processors (DCPs) in the subsystem, associating a queue header with each DCP, and providing a common queue header (CQH) accessible from all DCPs; Requesting a data movement operation in the electronic memory by the CPU executing the data movement request instruction specifying the work unit by specifying the channel program and the sub-channel identifier; Select the associated subsystem queue header, chain the queue element (QE) associated with the subchannel identifier to the queue header, and send a signal to the queue processor indicating that the QE is chained to the queue header. Step and QE chained to the associated queue header A step of performing the following tasks unit by access, and starts the channel program is addressed by QE, transferring one or more data pages between the specified positions, DC
Testing the queue header for another QE indication chained to the queue header after P has completed each work unit of work performed by the queue processor; and To
Chain a QE to another queue header associated with a queue processor not currently in use, and signal to the other queue processor that the queue header associated with the other queue processor has a chained QE. Sending and chaining the QE to a common queue header associated with the common queue in the subsystem to balance the workload in the subsystem if all queue processors are busy. An asynchronous data movement method for controlling movement of a data unit between two locations in the same electronic memory or different electronic memories in a data processing system having one or more CPUs.

Further, detecting whether any of the queue processors in the subsystem has failed and processing each QE chained to the queue header of the failed queue processor. Sending a signal indicating a fault condition from the failed queue processor to the non-failed queue processor; de-chaining each QE from the queue header of the failed processor; Chaining to the queue header of the surviving queue processor, and continuing the execution of the work item by another queue processor, the QE representing the work item being executed by the failing processor. Chaining to a queue associated with the operable queue processor. Asynchronous data migration method according to 1.

Sending a signal to the operational queue processor in the subsystem to process each QE chained to a queue header associated with the designated queue processor to be removed from the subsystem. Writing an inoperability indication to a queue header associated with the queue processor to be removed from the subsystem; and disposing each QE chained to the queue header of the removed queue processor as an enabled queue processor. Re-chaining to a queue header associated with the ready queue processor, and providing a QE representing the work item being executed by the failed processor.
Chaining to a queue associated with the ready queue processor to continue execution of the work item by the ready queue processor.
Asynchronous data movement method described in 1.

The method of 0151, further comprising implementing the load balancing method in hardware and / or microcode to make it transparent to system software running in the data processing system. Asynchronous data movement method.

A plurality of queues, each associated with a plurality of queue processors in the subsystem, each provided to receive work requested for the associated queue processor, and for performing work by the subsystem. , A queue element (QE) is generated and
A central processing unit (CPU) means for chaining to the queue as a U request, and the presence of the QE received during the pause of execution by the queue processor of the work unit of the QE currently being executed by the queue processor. Testing means associated with each queue processor for testing associated queues, and detecting means for each queue processor to detect the current execution state of other queue processors in the subsystem; and Means for moving the received QE that has been tested to a queue associated with the queue processor that is detected not to be in the running state; and, when the other queue processor is detected to be in the running state, Means for moving the received QEs to a common queue, wherein each QE on the common queue Computer system for, characterized in that by use queuing processor is feasible to control the asynchronous workload among multiple queues processor.

A control block for each request, including a plurality of data control processors (DCPs), each associated with a plurality of queue headers, and a channel program executed by the subsystem, is assigned to the assigned queue header by the CPU. Any number of central processing units (CPUs) that generate data movement requests in control blocks in electronic memory and request subsystems to execute work units, used as chained queue elements
And CPU means for sending a signal to the DCP when the central processing unit (CPU) has chained the request to the associated queue, accessing the QE on the associated queue and starting the channel program designated by the QE. Means for executing a unit of work by transferring one or more designated data pages within an electronic storage medium or between electronic storage media in a system;
Testing means associated with each DCP to test the associated queue header for the presence of the chained QE in the associated queue;
Means for the DCP to move to another queue associated with the CP, and a DCP for sending a signal to the other DCP indicating that the QE has been moved to the queue associated with the other DCP
Means and a QE chained to a queue header associated with the DCP when no DCP is available to perform the QE.
Means for transferring data between two locations in one electronic memory or in different electronic memories, including means for transferring data to a common queue accessible from all DCPs.

[0157] Which processor queue has a plurality of queue processors, a queue header representing the queue of each queue processor, and a common queue header representing the common queue associated with all queue processors. Also receive an input / output queue element (QE) or ADM (asynchronous data movement) queue element, the common queue receives only ADM QE, and each queue header is the next access in the queue it represents. A queue head pointer field to chain to the QE to be
The subsystem and each QE for the ADM subchannel, including a queue bottom pointer field for chaining to the last QE in the queue it represents, is used when the subchannel is currently processed by the queue processor. A current queue identifier field indicating the queue whose subchannel is being queued as a queue element, and a next Q in the same queue.
Microcode to carry CPU requests for subsystem operation, respectively, including a current queue chain pointer field to locate the subchannel chained as E and a program address field to locate the ADM program A plurality of ADM sub-channels and input / output channels having QEs configured as control blocks, and directing ADM operations to be performed by an ADM processor in the subsystem, wherein the input / output operations are performed by a channel processor. Means for allowing any CPU to select an I / O subchannel or an ADM subchannel to carry the current CPU data transfer request to the subsystem; and an I / O work request item or ADM work request. About the item Controlling the copying of data units between two locations in the same electronic memory or in different electronic memories, including interrupt means for allowing the subsystem to notify the central processing unit of the completion of work. Computer system for transferring a CPU request from any CPU in a data processing system to a subsystem to perform the same.

Further, the AD from the CPU to the subsystem
To process the CPU request for M operation, a QE for the ADM subchannel is used to store a checkpoint for storing data for each last subunit successfully transferred by the associated processor for the running ADM program. Re-chain the QE to the queue of another queue processor which continues execution of the ADM program from the last successfully transferred subunit by using the control data stored in the checkpoint field. Means to allow the running ADM program to recover in the event of a failure or removal of the associated queue processor.

Further, AD from the CPU to the subsystem
A reconfiguration command received by one of the DCPs and thereby designated as a reconfiguration processor to remove or add the DCP to the subsystem to process a CPU request for M operation. A subsystem bus to send to an operational DCP in the subsystem, a queue header associated with the processor to be removed, and a queue header associated with the added processor. 0156. The computer of 0156 comprising means for the reconfigurable processor and means for relocating the QE chained to the queue header of the removed processor to a queue associated with the reconfigured processor.・ It is an invention consisting of a system.

[Brief description of the drawings]

FIG. 1 is a diagram showing a computer system structure including one embodiment of the present invention.

FIG. 2 illustrates a multiple queuing subsystem that represents a preferred embodiment of the present invention in a computer system.

FIG. 3 shows important fields of a queue element which is a micro-coded control block associated with a sub-channel.

FIG. 4 is a diagram showing fields used in the present embodiment, which are included in the header of each processor queue.

FIG. 5 is a diagram showing fields used in the present embodiment, which are included in a header of a common queue (CQ).

FIG. 6 is a flowchart of a CPU request process in which a subchannel on an assigned processor queue is chained as a request source queue element.

FIG. 7 is a flowchart of the workload balancing process used for each ADM queue element (subchannel) on any processor queue or common queue.

FIG. 8 is a flowchart of an “EXECUTE” sub-process of the workload balancing process of FIG. 7;

9 is “CHECKQUEUE” of the subprocess “EXECUTE” in FIG. 8
It is a flowchart of a subprocess.

FIG. 10 is a flowchart of a “GETWORK” sub-process of the workload balancing process of FIG. 7;

FIG. 11 is a flowchart of a reconstruction process used by the ADM subsystem.

FIG. 12 is a flowchart of a recovery process used by the ADM subsystem.

FIG. 13 is a diagram showing a bus connecting between queue processors in a subsystem. This bus is used to signal the workload, recovery, and reconfiguration processes of the preferred embodiment.

[Explanation of symbols]

 1N CPU 20 CPU offload subsystem 21 electronic memory 22 input / output subsystem 23 electronic memory 110 QE signal / recovery / reconfiguration bus 111 reconfiguration signal means

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Thomas Jay Duket United States 12580, St.sburg, NY, Earl R1, Box 364 Be (72) Inventor Christine Reynolds Panner United States 78720-0042, United States Pau Box 200042, Austin, Texas, (42) Inventor Caspar Anthony Scalzi, 12601 United States of America, Pokies, New York, Academy Street 160 (56) References JP-A-2-287858 (JP, A)

Claims (5)

(57) [Claims] 1. A plurality of queues, each associated with a plurality of queue processors in a subsystem, each being provided to receive work requested for the associated queue processor, and the work being performed by the subsystem. Central processing unit (CPU) means for generating a queue element (QE) and chaining it as a CPU request to the queue, and a work unit of the QE currently being executed by the queue processor. , While paused by the queue processor,
Testing means for each queue processor for testing the associated queue for the presence of the received QE; detecting means for each queue processor for detecting the current execution state of other queue processors in the subsystem;
Received QEs tested to be on queue
Means for moving the received QE to a common queue when another queue processor is detected to be in the running state. Means for moving, wherein each QE on the common queue is executable by any available queue processor in the subsystem, the asynchronous workload between the plurality of queue processors. Computer system for controlling the computer. 2. The method of claim 1, further comprising a plurality of data control processors (DCPs), each associated with a plurality of queue headers, and a channel program executed by the subsystem, wherein a control block for each request includes Any number of central processing units that generate data movement requests in control blocks in electronic memory and request subsystems to execute work units, used as queue elements chained by the CPU ( CPU); CPU means for sending a signal to the DCP when the central processing unit (CPU) has chained requests to the associated queue; and a channel program designated to be accessed by the QE on the associated queue. To one or more designated electronic storage media within an electronic storage medium or between electronic storage media in a system. By transferring over data-page,
Means for performing the unit of work, a test means associated with each DCP for testing an associated queue header for the presence of a chained QE in the associated queue; Means for moving the QE to another queue associated with the other DCP, and means for sending a signal to the other DCP indicating that the QE has been moved to the queue associated with the other DCP. Means for the DCP, and when no DCP is available to perform the QE, the QE chained to the queue header associated with the DCP is
Means for transferring data between two locations in one electronic memory or in different electronic memories, including means for transferring to a common queue accessible from the CP. 3. A processor comprising: a plurality of queue processors; a queue header representing a queue of each queue processor; and a common queue header representing a common queue associated with all queue processors. The queue also receives an input / output queue element (QE) or an ADM (asynchronous data movement) queue element, the common queue receives only the ADM QE, and each queue header indicates the next queue in the queue it represents. A queue head pointer field to chain to the QE accessed to
A subsystem, including a queue bottom pointer field for chaining to the last QE in the queue it represents, and each QE for the ADM subchannel whose subchannel is currently being processed by the queue processor. The current queue identifier field, which indicates the queue whose subchannel is being queued as a queue element, and a field for locating the subchannel chained as the next QE in the same queue. CPUs for subsystem operations, each including a current queue chain pointer field and a program address field for locating ADM programs
A plurality of ADM sub-channels and input / output channels having QEs configured as control blocks by microcode to carry requests; and input / output operations indicating that ADM operations are to be performed by an ADM processor in the subsystem. CPU to indicate that it is to be executed by the channel processor
Instruction means for allowing any CPU to select an I / O sub-channel or an ADM sub-channel to convey a data transfer request to the subsystem; Data processing to control the copying of data units between two locations in the same electronic memory or in different electronic memories, including interrupt means for allowing the CPU to notify the central processing unit. C from any CPU in the system to the subsystem
A computer system for forwarding PU requests. 4. The method according to claim 1, further comprising the step of:
To process a CPU request for M operation, a QE for the ADM sub-channel is used to store a checkpoint for storing data for each last sub-unit successfully transferred by the associated processor for the running ADM program. Re-chain the QE to the queue of another queue processor which continues execution of the ADM program from the last successfully transferred subunit by using the control data stored in the checkpoint field. Means for enabling recovery of the running ADM program upon failure or removal of the associated queue processor. 5. The method according to claim 1, further comprising the step of:
One of the DCPs is received and thereby designated as a reconfigurable processor to remove or add the DCP to the subsystem to process a CPU request for M operation;
A subsystem bus for sending reconfiguration commands to an operational DCP in the subsystem, and a queue header associated with the processor being removed is disabled, and a queue header associated with the processor being added is enabled. Means for the reconfigurable processor, and a Q chained to the queue header of the processor to be removed.
Means for relocating E to a queue associated with the reconfigurable processor.