JP2587722B2 - Tunnel injection type static induction transistor - Google Patents

Description

The present invention relates to a tunnel injection type static induction transistor.

[Prior art] An electrostatic induction transistor (hereinafter abbreviated as SIT) changes the height of a potential barrier generated by a depletion layer between gates, thereby reducing current between a source and a drain. It is a transistor to be controlled.

At this time, since the control of the potential is performed through the capacitance of the depletion layer, it is equivalent to a bipolar transistor without the storage capacitance of the base layer, and it operates at a very high speed and low noise compared to the FET. Has excellent properties.

However, since the conventional SIT has a structure in which the dimension between the source and the drain, particularly the dimension between the source and the gate, is relatively large, the carrier is scattered by the crystal lattice and the upper limit frequency is limited.

[Problems to be Solved by the Invention] In order to eliminate the above-mentioned disadvantages, a thermionic emission type SIT in which carriers can move at thermionic velocity without being scattered by a crystal lattice has been previously proposed by the present inventors. Was done.

 The current density J at this time is given by the following equation (1).

Here, q is unit charge, k is Boltzmann's constant, T is absolute temperature, m * is effective mass of carrier, ns is impurity density of source, Φgs is diffusion potential Vg of gate region and source region, and Vg is voltage applied to gate. It is.

When the carrier injection state becomes thermionic emission state
The cut-off frequency fc of the SIT is given by the following equation (2) when the width of the potential barrier is wg and the SIT is cascaded and the second-stage input capacitance is considered.

Therefore, when GaAs is used, the width Wg of the potential barrier is 0.1 μm.
m, the cut-off frequency fc is approximately 780 GHz. From the above, the fc of the thermionic emission type SIT is at most 800 GHz, and a higher cutoff frequency fc cannot be obtained.

Therefore, the present invention provides a tunnel injection type using a quantum effect tunnel injection exceeding the limit of the above-mentioned thermionic emission type SIT.
The purpose is to provide SIT.

[Means for Solving the Problems] A tunnel injection type SIT according to the present invention includes a drain region having a high impurity density of a first conductivity type, and a second conductivity type formed on the drain region and opposite to the first conductivity type. Channel region having at least a portion of a semiconductor region of the first conductivity type, a high impurity density region of the first conductivity type formed on the channel region, and a second impurity region formed on the high impurity density region.
A source region having a high impurity density of a conductive type, a high impurity density region of a first conductive type of the channel and a source region, forming a tunnel injection region, contacting a second conductive type semiconductor region of the channel, and A gate formed of a semiconductor having a larger forbidden band width than the channel formed at a position where the distance between the peak of the potential barrier (intrinsic gate) generated near the source region in the channel and the source region is equal to or less than the mean free path of carriers. An area,
This gate region is formed in a mesh shape or a linear shape having a common end portion, and the dimension of the gate and the gate width (gate interval) is 2λ _{D with} respect to the Debye length λ _D determined by the impurity density of the channel region. It is characterized by being within.

[Operation] When a voltage is applied to the gate, the conductivity type of the region in contact with the gate in the channel region is reversed, electrons are tunnel-injected from the source to the drain, and the electrons move at high speed.
Thermionic emission type S proposed by the applicant in advance for the cut-off frequency of SIT
It can be raised about 100 times of IT.

[Example] Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing a tunnel injection type SIT according to the operation of the present invention. In the figure, reference numeral 1 denotes a drain region of an n ⁺ GaAs substrate, 2 denotes an n ⁻ layer of a channel, 3 denotes a tunnel injection layer of n ⁺ and p ⁺ layers provided in contact with the channel, and 4 denotes a source region. Reference numeral 5 denotes a gate region formed of Ga _1-x Al _x As, which is shown only in cross-section but is reticulated or linear, and ends should be electrodes together. The region is exposed on the surface, 6 is a drain electrode, 7 is a source electrode, and 8 is one of the gates.
The gate electrode is formed on the exposed portion of the surface.

As can be seen from this configuration, in a compound semiconductor in which a good insulating film cannot be obtained as in GaAs, the gate is formed of a mixed crystal such as Ga _1-X Al _X As having a larger bandgap than GaAs. This allows the gate to resemble an insulated gate.

Further, in the configuration shown in the figure, in the channel 2 formed between the source 4 and the drain 1 while passing between the gate regions 5, the source 4
It goes without saying that the distance to a more true gate (intrinsic gate: peak of a potential barrier generated near the source) is equal to or less than the mean free path. At this time, a normally-on operation and a normally-off operation can be performed by changing the interval and thickness of the gate region and the magnitude of the impurity density of the channel region. Ga to be the gate region
The value of x of _1-X Al _X As is, for example, x = 0.3. The impurity density is preferably undoped.

In the tunnel injection type SIT thus configured, the cutoff frequency fc is given by the following equation (3).

Q = CgVg (4) From equations (3) and (4) Becomes Where Gm is the transconductance of (element),
Cg is the input capacitance, Vg is the gate-source voltage, and ft is the reciprocal of the tunnel transition time τ.

 The tunnel transition time is given by the following equation (6).

here, Is the Planck constant divided by 2π (1.0546 × 10 ^-34 J ·
sec), E is the electric field strength of the tunnel junction, and a is the lattice constant. When the lattice constant is 5.6533 ° of GaAs, the electric field strength E is 10 ⁶ V / cm, 5 × 10 ⁶ V / cm, 7 × 10 ⁶ V / cm, 10 ⁷ V / cm.
From the above equations (5) and (6), fc is 1.37 × 10 ¹³ Hz, 6.83 × 10 ¹³ Hz, 9.56 × 10 ¹³ Hz, and 1.37, respectively.
× 10 ¹⁴ Hz, and the cutoff frequency is about 100 THz. This value is about 100 times that of the thermionic emission type SIT previously proposed by the applicant, and the cutoff frequency fc of the SIT can be significantly higher if the tunnel injection based on the quantum effect is used than the thermionic injection. You can see that.

By the way, in the above-described embodiment, there is a problem that the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) are likely to be large, and as a result, the cutoff frequency fc is reduced.

The solution to this problem is the structure shown in FIG. 2, in which Cgs can be made extremely small. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. Since the gate 5 is on the same main surface as the source 4, the gate electrode 8 can be easily taken out, and both Cgs and the gate resistance rg can be reduced, so that higher speed operation can be obtained.

3 and 4 show another structure of the present invention, in which an insulator 9 is provided to reduce Cgd. As the insulator, a SiO ₂ or Si ₃ N ₄ film, a polyimide resin, or the like is preferable. For GaAs dielectric constant 11, Si ₃ N ₄ 5.5, Si
O is 3.8 and polyimide is 3.2, so Cgd is less than half that of GdAs.

FIG. 5 shows an embodiment of the present invention in which the channel is a P layer 10. When the gate region and the P layer of the channel are inverted and the region of the P layer in contact with the gate region 5 becomes the n layer, electrons are tunnel-injected from the source to the drain to operate.

The length from the source to the drain, that is, the channel length can be controlled to a value of, for example, 100 °, but the width between the gates (gate interval, that is, the channel width) needs to be determined based on the Debye length.
The Debye length is given by the following equation (7).

Here, n is the impurity density of the channel, and ε is the dielectric constant.

In the above equation (7), when n is 10 ¹² cm ⁻³ , λ _D is 3.95 μm,
0.4 μm at 10 ¹⁴ cm ^-3 and at 10 ¹⁶ cm ^-3
It is about 0.04 μm. Roughly speaking, the control of the channel width is determined by the accuracy of the photolithography as compared with the control of the channel length. Therefore, the channel width must be determined in consideration of the manufacturing technology.

FIG. 6 shows an embodiment in which a high impurity density region is formed in the p-channel of the embodiment of FIG. 5 in order to efficiently control electrons from the source to the drain in the gate region. Since the buried region 11 has a high potential barrier with respect to the electrons on the source side, the electrons pass through both sides of the buried region of the channel. The p-channel where the part that actually operates forms the gate region and the source electrode 7 are, for example, 0.5 μm to
The thickness may be 1 μm, which facilitates the production.

FIG. 7 shows still another embodiment of the present invention, in which the p region is adjacent to the source region 4 and the remaining portion is n.
The structure is an (n ⁻ ) region.

FIG. 8 shows an embodiment in which the p region is inserted near the source of the channel, in which Cgs can be reduced and the gate region can be formed smaller.

In the embodiments of FIGS. 5 to 8 described above, the distance from the source to the true gate is, of course, shorter than the mean free path.

Incidentally, the impurity densities of the n ⁺ and p ⁺ layers of the tunnel injection layer can be determined as in the following equation. That is, p ⁺ ,
When the impurity density of the n ⁺ layer is uniform, the thickness W of the depletion layer determined by the diffusion potential Vb of 0 bias is expressed by the following equation.

Here, acceptor density of the N _A is the p ⁺ region 4, Np is the donor concentration of the n ⁺ region 3.

The N _A when the 10 ²¹ cm ^-3, N _D 10 ¹⁹ In cm ^-3 W 13
0 Å, E is ^{2.16 × 10 6 V / cm,} N D 10 ²⁰ In cm ^-3 W is 41 Å,
E is about 6.8 × 10 ⁶ V / cm, and fc at that time is respectively
It is about 40THz, 72THz.

In the above embodiment, Ga _1-X Al _X
As is necessary to reduce the surface order between GaAs and GaAs as much as possible, and Ga _1-X Al _X As
_It is preferable to use a mixed crystal to which a small amount of P (phosphorus) is added, such as _1-y . The composition at that time is such that when x = 0.3, y is 0.0
It should be about 1.

The impurity density of the channel may be about 10 ¹⁹ cm ⁻³ from the i-layer, and the tunnel injection region may be about 10 ¹⁸ to 10 ²¹ cm ⁻³ . Electrode material of the source and the drain is to the n ⁺ layer Au-Ge, Au-Ge- Ni,
For the p ⁺ layer, an alloy such as Au—Zn, Ag—Zn, or Cr—Au can be used.

The electrode material of Ga _1-x Al _x As of the gate region, the source, in addition to Ti electrode material for the drain, Pt, W, Cr, Hf, relative to Ga _1-x Al _x As, such as Ni A refractory metal material that does not form a resistive contact can also be used.

In manufacturing the device, the channel region and the source region are formed by a molecular layer epitaxial growth method capable of growing one molecular layer of GaAs according to the invention of the present inventors, a photomolecular layer epitaxial growth method, a vapor phase growth method, a MOCVD method, and an MBE method. , Ion implantation or the like can be used. Source, gate and drain electrodes are formed by vacuum evaporation (resistance heating, electron beam heating,
It can be formed by a combination of (sputtering method), plasma etching, photoetching, photolinography and the like.
In addition, the semiconductor material is not limited to GaAs, and may be a semiconductor such as InP, InAs, II-VI group semiconductor, or a mixed crystal thereof.
It goes without saying that _1-x Ga _x P or In _1-x Ga _x As may be used.

[Effects of the Invention] As described above, according to the present invention, a high-speed, low-noise, tunnel-injection-type electrostatic induction transistor that operates in three terminals such as amplification and oscillation in a high frequency region, which cannot be obtained by a conventional transistor, can be obtained. .

[Brief description of the drawings]

1 to 4 are sectional views for explaining the operation of the present invention.
FIG. 8 to FIG. 8 are cross-sectional views of a tunnel injection type static induction transistor according to each embodiment of the present invention. 1 ... n ⁺ substrate to be drain, 2,10 ... channel, 3 ... tunnel injection region, 4 ... source region, 5 ...
... A gate region formed of a semiconductor having a wider bandgap than GaAs, 6... A drain electrode, 7... A source electrode, 8.
Gate electrode, 9 ... insulator.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Junichi Nishizawa 1-6-16 Yonegabukuro, Sendai City, Miyagi Prefecture (72) Inventor Kaoru 2-9-9 Yonegabukuro, Sendai City, Miyagi Prefecture 406 (56) References Special JP-A-53-57769 (JP, A) JP-A-57-75464 (JP, A) JP-A-57-186374 (JP, A)

Claims (3)

(57) [Claims] A drain region having a high impurity density of a first conductivity type; and a channel region formed on the drain region and having at least a portion of a second conductivity type semiconductor region opposite to the first conductivity type. A high impurity density region of the first conductivity type formed on the channel region; a source region of the second conductivity type having a high impurity density formed on the high impurity density region; A peak of an electric potential barrier (intrinsic gate) formed near the source region in the channel and in contact with the second conductivity type semiconductor region of the channel by forming a tunnel injection region by the high impurity density region of the conductivity type and the source region. ) And a gate made of a semiconductor having a larger forbidden band width than the channel formed at a position where the distance between the source region and the mean free path of carriers is smaller than or equal to A band, the gate region is formed on the common reticulated or linear end, the Debye length lambda _D dimensions are determined than the impurity density of the channel region of the gate and the gate width (gate spacing) for,
Tunnel injection type static induction transistor which is characterized in that within 2 [lambda] _D. 2. A tunnel injection type static induction transistor according to claim 1, wherein the gate region and the semiconductor in the channel region are lattice-corrected. 3. A gate electrode according to claim 1, wherein the gate electrode provided in contact with the gate region is formed of a metal material that does not make a resistive contact with the gate region. Tunnel injection type static induction transistor.