JP2589065B2 - Method for manufacturing semiconductor integrated device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor integrated device such as a MOSFET, and an object thereof is to improve characteristics at a gate voltage smaller than a threshold voltage.

(B) Conventional technology The LOCOS method has been widely used as a device isolation technology in semiconductor integrated circuits (hereinafter referred to as ICs). However, in recent years, the necessity of fine patterns has been increased due to the demand for higher integration, and various new element isolation techniques have been reported instead of the LOCOS method having a large pattern conversion difference (Nikkei Electronics, March 29, 1982, No. 90-101). (See the article on “Publication of New Device Isolation Technology Alternative to Selective Oxidation Method” on page.) One of them is the Swami method, SWAMI (Side Wall
Masked Isolation) method is, for example, IEEE trans.on EDE
D-30 P1506-P1511 by KYChiuet al, "Sloped Wall Swami Method-Defect-free Local Peak Oxidation Process for VLSI Technology" (“The Sloped-Wall SWAMI-A Defect-Fr
ee Zero Bird′s-Beak Local Oxidation Process for S
caled VLSI Technology "). The SWAMI method will be described with reference to FIGS.

First, a semiconductor substrate such as a single crystal silicon wafer (1)
Is thermally oxidized to form an oxide film (2) on the surface (FIG. 4a). Next, a silicon nitride film (3) is deposited thereon (FIG. 2B). Next, a resist film (4) is formed by photolithography on the silicon nitride film (3) in a portion to be an element region, and a silicon nitride film in a portion corresponding to the element isolation region without the resist film (4) is formed. (3) and the oxide film (2) are removed by using an etching technique (FIG. 3C). Next, the semiconductor substrate (1) is etched to form a turret (5) of the semiconductor substrate. The turret part (5) has a first plane part (5a) forming an element region, and a slope part (5b) adjacent to a second plane part (6) adjacent to the turret part. Figure d). Then, a second step is performed to form an element isolation region.
Impurities having the same conductivity type as the impurities of the semiconductor substrate (1) are implanted into the plane portion (6) with ions (7) (boron or the like in the case of an N-channel element) to form a high-concentration region (8) (FIG. 3E). ). Next, a silicon nitride film (9) and an oxide film (10) are formed on the entire surface of the semiconductor substrate (1) by chemical vapor deposition (CVD).
(F). Thereafter, the oxide film (10) is etched in a direction perpendicular to the substrate (1) by using a reactive ion etching (RIE) method. At this time, since the RIE method etches in the vertical direction, the oxide film (10) remains on the side wall of the silicon nitride film (9) (g in the figure). Thereafter, the silicon nitride film (9) is etched, and further the oxide film (10) is etched (FIG. H). Thus, the silicon nitride film (9) is left on the side of the slope (5b). Thereafter, an oxide film (11) to be an element isolation region is formed by thermal oxidation (FIG. I), and the silicon nitride films (3) and (9) are etched and removed (FIG. J). The SWAMI method described above is effective for forming a fine element isolation region without a bird's beak seen in the LOCOS method.

However, the conventional SWAMI method has the following disadvantages. Hereinafter, the defect will be described with reference to FIG. 5 which shows a cross-sectional view of the MOSFET in the channel width direction. In this figure, a transistor current flows in a direction perpendicular to the plane of FIG. The hatched area (12) in the figure indicates that the inversion layer (P) is formed when a gate voltage is applied to the gate electrode (13) made of polysilicon.
(N-type layer in the case of a mold substrate), and that portion becomes a channel portion.

Due to the relationship between the drain-source current (I _DS ) and gate voltage (V _GS ) of MOS transistors, recent emphasis has been placed on them (particularly,
In the field of microelements and dynamic elements, there is a so-called sub-threshold characteristic (shown in FIG. 6) having a threshold voltage (Vt) or less. As shown, while the gate voltage (V _GS) is below Vt abruptly indicating the I _DS decreases characteristic (P) device is required, the above-mentioned
In the device by the SWAMI method, an undesired characteristic that the leak current (I _DS ) is large below Vt as shown by the characteristic (Q) appeared. IEDM 1981 P380-383 “Double threshold MOSFET without bird beak structure” THRESHOLD
MOSFETS IN BIRD'S-BEAK FREE STRUCTURES "). This is caused by the portion (R) in FIG. 5, that is, Vt of the end where the channel portion contacts the element isolation region is the center portion (S).
By lower. This is equivalent to adding a low Vt and very narrow channel transistor in parallel with the central transistor. The Vt at the end (R) becomes lower because the channel region extends downward along the slope. Note that this extension is caused by a lack of a high-density region (P + region in the above example) for the channel stop or a decrease in the concentration in the corresponding portion. This is because the impurity implantation shown in FIG. 4e is not sufficiently performed on the slope portion, or the impurity is absorbed into the oxide film in the subsequent oxidation treatment because the implantation is shallow, so that the impurity concentration on the slope portion becomes low as a result. It depends.

The (c) INVENTION AND SUMMARY Problems The present invention is a method of manufacturing a semiconductor integrated device to prevent an increase phenomenon of I _DS leakage current in the above-mentioned drawbacks or sub thread Tsushi yaw field region with those of the conventional SWAMI process It is something to offer.

(D) Means for Solving the Problems The present invention provides a first flat portion for forming an element region, a second flat portion located lower than the first flat portion, and a slope connecting the two flat portions. a step of attaching a SiO ₂ film by a plasma CVD method on the upper surface side of the semiconductor substrate having, then the SiO ₂
The film is etched using an ammonium fluoride solution until the SiO ₂ film portion corresponding to the slope portion is removed, and the Si film is etched.
A step of selectively providing an opening in the O ₂ film, and through this opening, the impurity concentration of the slope on the slope of the semiconductor substrate prevents the formation of an inversion layer and a gate voltage smaller than a threshold voltage. Implanting impurities so as to suppress the tendency of increase of the leakage current of the semiconductor integrated circuit device, further comprising: a first plane portion for forming an element region; Providing a resist film on the upper surface side of the semiconductor substrate having a second flat portion located lower than the one flat portion and a slope portion connecting the two flat portions so that the surface after application is substantially flat; and Removing the resist film by ashing with a plasma gas to expose the upper portion of the slope portion; and forming a thread on the upper portion of the slope portion exposed by the exposing step by preventing an impurity concentration from forming an inversion layer. Implanting impurities so as to approximately suppress the increase of the leakage current at low gate voltage than Shorudo voltage, a method for manufacturing a semiconductor integrated circuit device having a.

(E) Function The device of the present invention is characterized in that the turret of a semiconductor substrate having an element region on a flat surface has a gate voltage lower than a threshold voltage on a slope adjacent to the flat surface, the impurity concentration preventing formation of an inversion layer. Impurities are implanted to the extent that the increase in leakage current is suppressed, so that the source / drain current in the sub-threshold region smaller than the threshold voltage can be sharply reduced, preventing functional degradation due to leakage current can do.

(F) Embodiment FIG. 1 is a partial sectional view of an embodiment of the present invention.
This figure shows one MOSFET formed on a semiconductor substrate (20) cut along the channel width direction, and the semiconductor substrate (20) has a turret (22) surrounded by an element isolation region (21). ) Is configured to have. This turret (22)
Is a flat portion (23) having an element region, and the flat portion (first
A slope (25) extending from the flat portion (23) to the second flat portion (24) constituting the element isolation region, and a region (26) below the first flat portion (23). Indicates a channel layer. Impurity layers (27) and (28) for preventing the formation of the inversion layer are formed below the slope portions (25) and (25) and below the second plane portion (24). The impurity layer (27) prevents both sides (26a) and (26b) of the channel layer (26) from drooping along the slopes (25) and (25) (refer to the R portion in the conventional example of FIG. 5). It is arranged adjacent to the first plane portion (23) so as to suppress an increase tendency of the leak current at a gate voltage smaller than the voltage.

(29) is an oxide film provided on the first plane portion (23), and a conductive film (30) made of polysilicon to be a gate electrode is formed on the oxide film. Reference numeral (31) denotes an oxide film which forms an element isolation region provided on the slopes (25) and (25) and the second plane (24).

Next, the manufacturing method of the present invention will be described with reference to the process charts of FIGS. Silicon wafer (semiconductor substrate)
The surface (41) of (40) is thinly thermally oxidized (the oxide film thickness is about 200-5
Next, an oxide film (42) is formed by (00), and then a silicon nitride film (SiN) (43) is deposited by a reduced pressure vapor deposition method for about 1000 to 2000 degrees. After that, the resist film (45) is left in the element region (44) by the lithography technique, and the silicon nitride film (4
3) The oxide film (42) is etched by a reactive ion etching method (FIG. 2a). Then C ₂ substrate (40)
Etching is performed by a plasma etching method using F ₆ gas to form a shape having a lobe (44) as shown in FIG.
This step can be performed by etching with a KOH solution. Next, as shown in FIG. 3C, in the case of an N-channel transistor, boron which becomes P-type conductive is ion-implanted (46). This implantation has an energy of 40 KeV and a dose of about 5 × 10 ¹³
/ Cm ² .

Next, after removing the resist film (45) and performing a heat treatment at about 1000 ° C., an oxide film (47) of about 500 ° is formed by thermal oxidation. Thereafter, an oxide film (48) having a thickness of several thousand degrees is entirely formed by a plasma CVD method (FIG. 2d).

Next, this oxide film (48) is treated with an ammonium fluoride solution (NH
₄ F) Etch for several minutes. The oxide film (48) formed by the plasma CVD method has a property that the etching liquid has a large etching rate in the step portion (see the description of Nikkei Electronics, page 93, right column, lines 18 to 23). Opening (4) only on the slope (44) as shown in
9) is established. In this state, boron ions (50) are supplied through this opening (49) at an energy of 900 KeV and 2 × 10 ¹³
The impurity is deeply implanted at a dose of / cm ² to increase the impurity concentration in the slope portion (44) (FIG. 2f). Next, a silicon nitride film (4
The oxide films (47) and (48) other than the portion protected in 3) are removed (FIG. 9G). Thereafter, a silicon nitride film (51) is provided on the entire surface of the substrate (40), and an oxide film (52) is deposited thereon by a CVD method (h in the figure). Then, the oxide film (52) is etched in the vertical direction by the reactive ion etching method, and the nitride film (51) is etched and removed (FIG. I). In addition, the oxide film (52) in the portion adjacent to the slope portion (44) is removed by etching (j in the figure), and thereafter, thermal oxidation is performed to form a second portion corresponding to the element isolation region portion (53).
An oxide film (55) is formed on the flat portion (54) (k in the figure).
Thereafter, the silicon nitride film (51) is removed (FIG. 1).
After that, an element is formed in the element region (44) to complete the semiconductor device, but a known process may be used for the process, and the description is omitted.

FIG. 3 shows another embodiment of the method of the present invention.
FIG. 2A shows the first embodiment in which the process of FIG. 2C is completed. Next, a resist film (60) is provided on the upper surface side of the substrate (40) so that the surface after application is substantially uniform (b in the figure). Next, the resist film (60) is removed by asking with a plasma gas to form an exposed portion (61) on the side of the first flat portion of the slope portion (44). Next, ions (62), which are impurities, are implanted into the exposed portions (61) to increase the impurity concentration of the corresponding portions. Then, after the resist film (60) is removed, the steps after FIG. 2H are performed.

(G) Effect of the Invention The device of the present invention is a part of a turret part of a semiconductor substrate which is surrounded by an element isolation region part and has an element region in a plane part, a part of a slope part on a side defining a channel width adjacent to the plane part. Since the impurity concentration is set high enough to prevent the formation of the inversion layer and to suppress the increase tendency of the leak current at the gate voltage smaller than the threshold voltage, when this device is used as a DRAM read transistor, for example, the switch-off is used. The data leakage speed in the state can be reduced.
Further, the method of the present invention is useful and suitable for miniaturization of elements because the characteristics of the SWAMI method are maintained as they are.

[Brief description of the drawings]

FIG. 1 is a partial sectional view of one embodiment of the apparatus of the present invention, FIG.
1 to 3 are process diagrams of one embodiment of the method of the present invention, FIGS. 3a to 3c are main process diagrams of another embodiment, and FIGS.
FIG. 5 is a partial sectional view of a conventional transistor, and FIG. 6 is a threshold characteristic diagram. (22) ... battery part, (23) ... first plane part, (25) ...
Slope section, (24) ... second plane section.

Claims (2)

(57) [Claims] A first planar portion for forming an element region, a second planar portion positioned lower than the first planar portion, and a plasma CVD method on an upper surface side of a semiconductor substrate having a slope connecting the two planar portions; a step of attaching a SiO ₂ film by law, then the SiO ₂
The film is etched using an ammonium fluoride solution until the SiO ₂ film portion corresponding to the slope portion is removed, and the Si film is etched.
A step of selectively providing an opening in the O ₂ film, and through this opening, the impurity concentration of the slope on the slope of the semiconductor substrate prevents the formation of an inversion layer and a gate voltage smaller than a threshold voltage. Implanting impurities so as to suppress the tendency of increase in the leakage current of the semiconductor integrated circuit device. 2. The method according to claim 1, further comprising applying a first flat portion for forming an element region, a second flat portion positioned lower than the first flat portion, and a slope portion connecting the two flat portions to an upper surface of the semiconductor substrate. A step of applying a resist film so that the subsequent surface is substantially flat, a step of removing the resist film by ashing with a plasma gas to expose an upper portion of the slope, and the slope exposed by the exposure step Implanting an impurity at an upper portion of the portion such that the impurity concentration is such that the formation of the inversion layer is prevented and the tendency of the increase in the leak current at a gate voltage smaller than the threshold voltage is suppressed. A method for manufacturing a circuit device.