JP2590105B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device having an LSI test facilitating circuit and a noise margin evaluation circuit, and particularly relates to a gate array and the like. High-speed, multi-pin custom
Used for IC.

(Prior art) Generally, LSI tests include a DC test, a function test, an AC test, and the like. When measuring the DC characteristics of an output pin during the DC test,
Normally, the target pin is fixed to a high level, a low level, or a high impedance state by operating the LSI. However, in order to fix the output state of the output buffer as described above, all the output pins (including the output mode of the bidirectional pin) are at “H” level and “L” level. High impedance state (“Z”
It is necessary to sequentially provide input data which always changes to the level (level). Therefore, there is a disadvantage that the test time is long. Further, since the output pins are changed by sequentially changing the input data by operating the LSI, it is difficult to measure all the pins at once, which also increases the test time.

FIG. 6 shows a conventional test facilitating circuit for facilitating the test of the output buffer by hardware. OR gate 11 ₁ In this circuit, 11 _2, from the internal circuit ... to one input terminal of the signal S1, S2, ... are supplied, these OR gate 11 _1, 11 _2, ... the other to the input terminal and the test mode A control signal SC for switching between the normal operation mode and the normal operation mode is supplied. Then, the OR gate 11 _1, 11 ₂ ... it outputs the output buffer 12 _1, 12 _2, and output ... and the output terminals 13 _1, 13 ₃ ... via. However, in such a configuration, the outputs of the output buffers 12 ₁ , 12 ₂ ,... Can only be fixed to the “H” level. If the NOR gates are used in place of the OR gates 11 ₁ , 11 ₂ ,..., The outputs of the buffers 12 ₁ , 12 ₂ ,... Can be fixed at the “L” level, but cannot be fixed at the “H” level. The outputs of the buffers 12 ₁ , 12 ₂ ,... Cannot be set to the high impedance state. In addition, the circuit configuration as described above has a disadvantage in that the output delay time increases because a delay of one stage of the OR gate (or NOR gate) occurs. As described above, the function of the conventional test facilitation circuit cannot be said to be sufficient.

In addition, when evaluating the noise margin of the completed LSI, it is usually performed by changing the input level voltage during the execution of the function test. However, with such a method, it is difficult to directly evaluate the malfunction output of the input buffer without knowing which input buffer malfunctioned. Furthermore, since simultaneous output switching cannot be arbitrarily performed, the noise margin cannot be evaluated if there is no test pattern for simultaneous switching. It is also difficult to find an optimization condition for improving a noise margin.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor integrated circuit device, in order to perform the DC test of the output buffer, an input pattern sequence for the DC test is required, and the simultaneous switching is arbitrarily performed. There is a disadvantage that it is difficult to evaluate the noise margin because it cannot be caused.

The present invention has been made in view of the above circumstances, and an object of the present invention is to perform a DC test of an output buffer easily without preparing an input pattern sequence for a DC test, and perform simultaneous switching. An object of the present invention is to provide a semiconductor integrated circuit device in which a noise margin can be easily evaluated by adopting a configuration that can be arbitrarily raised.

(Means and Actions for Solving the Problems) That is, in the present invention, in order to achieve the above object, a latch circuit is provided in each output buffer (including a bidirectional terminal output buffer) of the semiconductor integrated circuit device. Is established,
The output state of the output buffer can be arbitrarily determined irrespective of the state of the preceding circuit by the contents of the latch circuit. Further, the latch circuits are cascaded so that data for output determination can be serially transferred.

In the above-described configuration, if data is stored in the latch circuit in advance and the output buffers are simultaneously operated by a common trigger signal, simultaneous switching can be arbitrarily performed based on the data stored in the latch circuit. Therefore, a malfunction caused by simultaneous switching can be easily known by utilizing this fact.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of a semiconductor integrated circuit device. In the figure, 14 is a chip of the semiconductor integrated circuit device, 15 is an original functional unit, and 16 is a mode switching signal input terminal. The mode switching signal MS switches between the normal operation mode and the test mode. 17 is a clock input terminal to which the clock signal CK is supplied, 18 ₁ to 1
8 ₅ is the output buffer, 19 _{1 to} 19 ₅ is the output buffer 18 ₁ to 1
8 is a test for the latch circuit of _5. Also, the 20 ₁ to 20 ₄ in the input buffer, 21 ₁ to 21 ₄ is a test latch circuit of the input buffer 20 ₁ to 20 _4. 22 original function unit 15 and the malfunction signal output of the clock signal line, 23 is a clock signal line for transmission output value determining data, 24 _{1-24 5} original function unit
The output signal line from 15, 25 _to 253 ₄ input signal lines to the original function unit 15, 26 malfunction signal serial output line, 27 is a data serial input line for the output value determination.

With the above construction, the output in the case of the testing of the buffer 18 _{1-18 5,} the mode switching is set by signal MS to the test mode, the data serial input line for the output value determined
Sequentially each latch circuit the output value determination data from 27 19 _{5-19 1}
And latch it. And these latch circuits 19
_{5-19 1} based on the output value determination data latched executes the output buffer 18 _{5-18 1} DC test. When each of the tests of the "H" level, "L" level, and "Z" level of the output is executed, the above operation is repeated three times to latch the respective output value determination data.

On the other hand, in the case of the test input buffers 20 ₁ to 20 _4, the mode switching signal MS is set to the normal operation mode,
Sequentially reading the data latched in the latch circuit 21 ₁ to 21 ₄ from the malfunction signal serial output line 26 from the clock input terminal 17 is given a clock signal CK. Therefore, by checking the signal obtained from the output line 26, it is possible to easily check which input buffer has malfunctioned.

FIG. 2 shows the output buffer 18 in the circuit of FIG.
Shows a detailed configuration example of the near _{1-18 5} and test latch circuits 19 ₁ to 19 _5. In FIG. 2, reference numeral 18 denotes an output buffer (here, a tri-state buffer), reference numerals 28 to 31 denote semiconductor switches composed of N-channel MOS transistors for switching between a normal operation mode and a test mode, 32 an inverter, and 33 an "L". A data latch circuit for determining the “level” and “H” level, 34 is a data latch circuit for determining a high impedance state, 35 is a latch circuit for simultaneous switching operation, 36 is a data shift signal line for determining an output value, and 37 is In the test mode, a clock signal line for data shift, 38 is an output pad, and 39 is a trigger signal line for simultaneous switching operation.

In the above configuration, the connection between the original function unit 15 and the test mode function unit is switched by the mode switching signal MS. That is, first, when the mode switching signal MS is set to “H” level, the semiconductor switches 28 and 29 are turned on,
When the semiconductor switches 30 and 31 are turned off, the output buffer 18 is connected to the original function unit 15 and is separated from the test mode function unit. Therefore, the output buffer 18 performs a normal operation. On the other hand, when the mode switching signal MS is set to “L” level, the semiconductor switches 30 and 31 are turned on, and the semiconductor switches 28 and 29 are turned off, and the output buffer 15 is connected to the test mode function unit, and It is separated from the functional unit 15.

Now, assuming that the mode switching signal MS is at "L" level, the operation at this time will be described. Data is sequentially input to each of the latch circuits 33, 34, and 35 from the data shift signal line 36 based on the clock signal supplied to the data shift clock signal line 37. After transferring any data to all the latch circuits 33, 34, 35, a clock signal is input to the trigger signal line 39 for simultaneous switching operation as a trigger signal TS. As a result, an output signal determined by each of the latch circuits 33, 34, and 35 is obtained at the output pad 38 via the output buffer 18.
At this time, the trigger signal line 39 for the simultaneous switching operation
Since all the latch circuits are operated by the clock signal supplied from the controller, not only the DC test can be facilitated but also the noise margin can be checked as in the case of simultaneous switching.

In the circuit shown in FIG. 2, a configuration in which a tri-state buffer is used as the output buffer 18 is shown. However, the same applies when a normal output buffer is used. The signal circuit, that is, the semiconductor switches 28 and 31, and the latch circuit 34 for determining the high impedance state are not required. Further, the present invention can be similarly applied to the bidirectional output buffer 18 'of the bidirectional terminal 40 as shown in FIG. The block 41 in FIG. 3 has the same configuration as that of the circuit in FIG. 2 except for the output buffer 18, and 42 is a bidirectional input buffer.

FIG. 4 shows the input buffer 20 in the circuit of FIG.
20 ₁ to 20 ₄ and shows the detailed structure of the periphery of the test latch circuit 21 ₁ to 21 _4, an example of the malfunction detection circuit of the input buffer 20 ₁ to 20 ₄ by simultaneous switching noise. In FIG. 4, 43 is an input pad, 20 is an input buffer, 44
Is an OR gate, 45 is an inverter, 46 is a latch circuit (flip-flop) for storing a malfunction signal, 47 is a semiconductor switch using a P-channel MOS transistor, 48 is a semiconductor switch using an N-channel MOS transistor, and 49 is a malfunction due to noise. A pulse input line, 50 is an output signal line of the preceding latch circuit (for serial output), 51 is an input signal line of the next latch circuit (for serial output), 52 is a clock signal line, 53
Is a clear signal line of the latch circuit 46 to which the clear signal C is supplied.

In the above configuration, the mode switching signal MS is set to “H”.
When set to the level, the input buffer 20
, So that it operates in the normal operation mode. At this time, the semiconductor switch 47 is turned off and the semiconductor switch 48 is turned on, and the clock signal CK is supplied to the latch circuit 46. On the other hand, when the mode switching signal MS is set to “L” level, the semiconductor switch 47 is turned on and the semiconductor switch 48 is turned off, and the output of the input buffer 20 is supplied to the latch circuit 46. At this time, the data input terminal of the flip-flop as the latch circuit 46 is set to “H” by the “L” level of the mode switching signal MS.
Fixed to level. In this state, simultaneous switching is intentionally performed. At this time, when noise of a level that can be regarded as “H” level occurs in the input buffer 20, this “H” level signal is supplied to the flip-flop via the semiconductor switch 47 and the pulse input line 49. (Latch circuit) Input to the clock input terminal of 46. As a result, the "H" level signal output from the OR gate 44 is latched by the flip-flop 46,
The fact that the input buffer 20 malfunctioned is stored. Next, when the mode switching signal MS is switched to the “H” level to return to the normal operation mode, the flip-flops 46 provided corresponding to the respective input buffers are connected in series. By supplying the signal CK, the data stored in the flip-flop 46 is sequentially shifted and output from the external terminal. Therefore, by checking the signal output from the external terminal, it is possible to detect which input buffer has malfunctioned.

FIG. 5 shows a trigger signal TS for obtaining the simultaneous switching operation of the output buffers in the circuit shown in FIG.
Is shown. In FIG. 5, 54 is an output value determining data transmission line, 23 is the output value determining data transmitting clock signal line, and 55, 55,... Are output value determining data latch circuits (in the circuit of FIG. 2). 55n is the output value determining data latch circuit 5
5, 55,..., 56 is a latch circuit for generating a trigger for simultaneous switching, 57 is a power supply V _DD (“H” level), 58 is a trigger generation signal line for simultaneous switching, and 59 is a clear signal C supplied. Clear signal line.

First, the trigger generation latch circuit (flip-flop) 58 is reset by the clear signal C, and the simultaneous switching trigger signal line 58 is at "L" level. When sequentially sending output value determination data via the output value determination data transmission line 54, the "H" level is always transferred to the first bit. When a clock signal is input +1 times the number of stages of the latch circuits 55, 55,..., 55n, the first input “H” level signal is input to the clock input terminal of the latch circuit (flip-flop) 56 for simultaneous switching. An “H” level is output to the trigger signal line 58. Since this signal line 58 is connected to the latch circuit 35 via the trigger signal line 39 in the circuit of FIG. 2, a trigger is caused by the rise of the simultaneous switching trigger signal line 58 from "L" level to "H" level. Then, simultaneous switching based on the output determination data occurs. Therefore, if such a trigger generation circuit is used, the trigger signal TS can be generated without an externally applied signal, so that simultaneous switching can be performed without increasing the number of pins.

According to such a configuration, various effects described in the following (1) to (5) can be obtained.

(1) Test data dedicated to DC test (all outputs are “L”
Level, “H” level, and “Z” level), it is possible to reduce the time for DC testing during LSI development.

(2) Since the DC test method is the same in all cases, test programs and test jigs can be standardized and cost can be reduced.

(3) Since it is basically unnecessary to operate all functions, the test time can be reduced and the test efficiency can be improved.

(4) After completion of the LSI, any number of output buffers at any position can be simultaneously switched easily from the outside from the outside, and it is possible to know which position of the input buffer has malfunctioned due to the simultaneous switching. The margin can be easily evaluated.

(5) Since the noise margin can be checked under various conditions, it is easy to find an optimization condition for improving the noise margin. This results in LS
I leads to cost reduction.

[Effects of the Invention] As described above, according to the present invention, a DC test of an output buffer can be easily performed without preparing an input pattern sequence for a DC test, and simultaneous switching can be arbitrarily performed. By doing so, a semiconductor integrated circuit device in which the noise margin can be easily evaluated can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 2 and 3 are detailed configurations around an output buffer and a test latch circuit in the circuit of FIG. FIG. 4 is a circuit diagram showing an example.
5 is a circuit diagram showing a detailed configuration example around an input buffer and a test latch circuit in the circuit shown in FIG. 5. FIG. 5 shows a trigger signal generation circuit for simultaneous switching operation of the output buffer in the circuit shown in FIG. FIG. 6 is a diagram showing a conventional test facilitation circuit. 14: a chip of a semiconductor integrated circuit device, 15: an original functional part, 16: a mode switching signal input terminal, 17: a clock input terminal, 18 ₁ to 18 ₅ ... an output buffer, 19 _{1 to} 19 ₅ ... … Test latch circuit, 20 _{1 to} 20 ₄ …… Input buffer, 21 _{1 to} 21 ₄
…… Test latch circuit, 22, 23 …… Clock signal line, 2
4 _{1 to} 24 ₅ …… Output signal line, 25 _{1 to} 25 ₄ …… Input signal line, 26
… Malfunction signal serial output line, 27… Data serial input line for output value determination, MS… Mode switching signal, CK… Clock signal.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-87150 (JP, A) JP-A-60-220942 (JP, A) JP-A-57-133656 (JP, A)

Claims (2)

(57) [Claims] A first latch means for testing, which is provided in cascade connection with each of a plurality of output buffers and stores output value determination data, and is cascade-connected to each of a plurality of input buffers. A second latch means for storing an output signal of each input buffer. When a test of the output buffer is performed, a test mode is set by a mode switching signal, and an output value is determined. Data is sequentially supplied to the first latch means and latched, and a DC test of the output buffer is executed based on the output value determination data latched by the first latch means. When the operation is performed, the normal operation mode is set by the mode switching signal, the clock signal is supplied, and the data latched by the second latch means is read out serially. Each of the first latch means receives an output value determination data in response to a clock signal, and outputs an "L" level signal and an "H" signal.
A first latch circuit for determining a level;
A second latch circuit for determining the high impedance state of the output buffer, and a second latch circuit for determining the high impedance state of the output buffer. And a third latch circuit for performing simultaneous switching operations of the respective output buffers, and in response to the mode switching signal, connecting the input terminal of the output buffer to the original during normal operation mode. Connected to a functional unit, disconnecting the first to third latch circuits, supplying an output of the first and third latch circuits to an input terminal of the output buffer in a test mode, and controlling an input terminal of the output buffer. And a first switch circuit for supplying an output of a third latch circuit and disconnecting an original function unit. A fourth latch circuit provided at an output terminal of the input buffer for storing a malfunction signal during simultaneous switching; and a fourth latch circuit in a normal operation mode in response to the mode switching signal. A second switch circuit for supplying a clock signal and supplying the output of the input buffer to the fourth latch circuit in a test mode to latch the output, and wherein a data input terminal of the fourth latch circuit is fixed. Wherein the semiconductor integrated circuit device causes simultaneous switching and latches a malfunction in the fourth latch circuit. 2. The apparatus according to claim 1, further comprising: a trigger generation circuit provided at the last stage of the cascade-connected first and second latch circuits and generating the trigger signal. "The first and second cascade-connected first and second
And the trigger signal is generated in response to the "H" level added to the first bit when the number of serial stages of the first and second latch circuits is exceeded. The semiconductor integrated circuit device according to claim 1.