JP2590154B2 - Program debug support device for parallel processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processor, and more particularly to a program debugging support for a parallel processor suitable for supporting program debugging.

[Conventional technology]

Conventionally, as described in, for example, Japanese Patent Application Laid-Open No. Sho 60-5349, there is a trace device for recording program execution histories of a plurality of processors as a debugging support of a program of a parallel processor composed of a plurality of processors.

In this tracing device, any one of a plurality of processors is set as a reference processor, and when the operation state (address, data, interrupt, CPU state) of the reference processor matches a predetermined state, the reference point is set. Before and after, the program execution history of a plurality of processors was recorded.

[Problems to be solved by the invention]

The above prior art is effective when a plurality of processors execute programs of the respective processors in synchronization. However, in a parallel processor in which each processor executes a program in each processor asynchronously and transfers data between the processors asynchronously with processing in each processor via a network, the program is executed in each processor. The execution time varies depending on the distance between the processors, delay in data transfer due to collision of a path on the network, interrupt processing in the processors, and the like.

The prior art does not consider the above points,
Even when the operation state of a reference processor is set as a reference point and before and after the operation state of another processor is traced, the trace results of processors other than the reference processor may not include necessary information.

Also, in the initial stage of parallel processor program development, if a program that is not fully debugged is executed by each processor, the parallel processor in which each processor executes the program asynchronously can execute various processes in one execution. And the location where the bug occurs differs each time the program is executed, and reproducibility in executing the program cannot be guaranteed. This makes it difficult for programmers to isolate bugs, such as whether the bugs are caused in multiple operations related to each processor or whether they are unique to the processor. There was a problem that the efficiency of the system became poor.

An object of the present invention is to provide a parallel processor program debugging support that guarantees reproducibility in program execution and improves the efficiency of parallel processor program debugging.

[Means for solving the problem]

The above object is achieved by controlling a single data transfer bucket between processors in a network capable of transferring data between arbitrary processors.

For this purpose, first, in an instruction executed by each processor for instructing data transfer between arbitrary processors, an operand for designating the order of data transfer is provided.

In the data transmission device of each processor, there are provided a counter for holding the order of transmission to the network and means for comparing the counter with the order for data transfer specified by the instruction.

[Action]

When each processor sends a packet on the network in order to perform inter-processor data transfer, the data transmission device in each processor uses an operand that specifies the order of data transfer specified by the inter-processor data transfer instruction. The counters which hold the order of sending to the network are compared, and only when the result of the comparison is coincident, the counter is sent to the network. If they do not match, do not send the packet to the network until they match.

The value of the counter that holds the order of sending to the network, which is held by each processor, broadcasts that the processor that sent the packet to the network sent one packet to all processors, and updated the counter value. By doing so, it is guaranteed that all processors have the same value. As a result, it is possible to control only one packet to flow on the network, and to send the packet to the network in a specified order, so that reproducibility in program execution can be guaranteed, and the program data of the parallel processor can be guaranteed. The efficiency of bagging can be improved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First
The figure shows an overall configuration diagram of the parallel processor. 101
Is a network capable of transferring data between arbitrary processors, and has a function of sending a data packet to a target processor using the transfer information of the data packets 102 and 107. The network 101 can have various configurations such as a cross-bus switch, a multi-stage switch network, and a bus. 110 to 111 are processors, here 2
Only the stand is shown. Each of the processors 110 to 111 includes a data receiving device 120, a data transmitting device 130, an instruction processor 140, and a local storage 150.

The instruction processor 140 reads out an instruction from the local storage 150, decodes the instruction, and performs various controls for executing the instruction.

The data transmission device 130 generates a data packet 102 or 107 to be transmitted to the network 101, and
1 and is constituted by a network transmission control 131 composed of a microprocessor and the like.

The data packet 102 includes a processor number 103 (hereinafter abbreviated as RCVPE) on the receiving side that receives the transfer data, a control code 104 indicating how the receiving processor controls the transfer data, and a transfer data on the receiving processor. Is stored in an address 105 of the local storage 150 (hereinafter abbreviated as ADDR) and transfer data 106 (hereinafter abbreviated as DATA). The data packet 107 is composed of a processor number 108 (hereinafter abbreviated as RCVPEALL) common to all processors and a control code 109 indicating how the receiving processor controls the data packet in order to pass the data packet to all processors. Is done.

The data receiving device 120 receives the data packets 102 and 107 sent from the network 101 and performs various controls in accordance with control codes in the data packets. The data receiving device 120 is controlled by a network receiving control 121 composed of a microprocessor. Be composed.

Although it is not necessary to specify the data transfer method between the processors in the present invention, here, it is assumed that data is transmitted and received asynchronously between the processors performing data transfer, and the processing of the instruction processor is performed when the transferred data reaches the processor on the receiving side. Interrupt and capture data. At this time, it is assumed that an address of a local storage for storing the data is used for the data.

Next, the support of the program debugging of the parallel processor will be described in detail with reference to FIG.

First, a transmission process in which a certain processor sends data to another processor will be described.

When the instruction processor 140 decodes the data transfer instruction,
It is checked whether data transfer to the data transmitting apparatus 130 is possible, that is, whether the data transmitting buffer 132 is empty. If data transfer is not possible, wait until it is possible. If data transfer is possible, the instruction processor 140 sets the data transmission buffer 132 with the operand specified by the data transfer instruction. As this operand, the processor number of the receiving side (RCVP
E), a control code (S
END), a local storage address (ADDR) for storing the transfer data in the local storage by the receiving-side processor, the transfer data (DATA), and the order of data transfer (SQN).

Here, the operand for designating the data transfer order of the data transfer instruction is to be incorporated into the program of each processor by the programmer, or automatically generated by the compiler at the time of compiling the program of the parallel processor by flow analysis.

When the instruction processor 140 finishes setting the operand, it instructs the data transmitting apparatus 130 to send the operand to the network 101, and terminates the instruction. The instruction processor continues to start the next instruction.

When the data transmitting apparatus 130 is activated by the instruction processor 140, the comparator 134 compares the SQN of the data transmission buffer 132 with the register 133 in the data transmitting apparatus 130 that holds the transmission sequence number. The result of the comparison is sent to the network transmission control 131 by a signal 135. In the network transmission control 131, if the comparison results match, the data packet 10 other than the SQN of the data transmission buffer 132 is used.
As 2, a process of sending to the network 101 is performed. If the compared results do not match, the data packet 102 is not sent to the network 101, and the process waits until the compared results match.

Further, in the network transmission control 131, after transmitting the data packet 102 to the network 101, the data packet 107 is generated to add the contents of the register 133 to the entire processor plus 1, and the data packet 107 is transmitted to the network 101.
The data packet 107 is composed of a processor number (RCVPEALL) common to all processors and a control code (COUNT UP) indicating that the register 133 is incremented by one, and is stored in a buffer 136 in the data transmitting apparatus in advance.
Set from 40.

Next, data packet reception processing will be described. The data packet 102 sent from the network 101 is held in the network reception control 121 in the data receiving device 120. The network reception control 121 decodes the control code (SEND) 104 in the received data packet 102, determines that data has been sent from another processor, and reports this to the instruction processor 140. Instruction processor 1
At 40, when the report is received, the processing is interrupted, the data address (ADDR) 105 and the data (DATA) 106 in the data packet 102 are received from the network reception control 121, and written to the local storage 150. After performing the above processing, the instruction processor 140 restarts the interrupted processing.

When the data receiving device 120 receives the data packet 107, the network reception control 121 in the data receiving device 120 controls the control code (COUN) in the data packet 107.
TUP) 109 is decoded, and a signal 122 instructs the data transmitting apparatus 130 to add 1 to the register 133 holding the transmission sequence number. In the data transmission device 130, the signal 12
According to 2, the transmission sequence number control 136 sets the content of the register 133 plus one.

On the other hand, the normal operation, that is, the data transfer between the processors is not in the specified order, and when each processor performs the data transfer asynchronously at an arbitrary time, the data transfer processing of each processor is as follows.

In the transmission process, when the instruction processor 140 decodes the data transfer instruction, the instruction processor 140 checks whether data transfer is possible to the data transmitting apparatus 130. If not, wait until it is. If data transfer is possible, the instruction processor 140 sets the data transmission buffer 132 with the operand specified by the data transfer instruction. At this time, the order of data transfer (SQN) need not be set. When the instruction processor 140 finishes setting the necessary operands, it activates the data transmission device 130 and terminates the instruction.

When activated by the instruction processor 140, the data transmitting apparatus 130 performs a process of transmitting data other than the SQN of the data transmission buffer 132 to the network 101 as the data packet 102 regardless of the comparison result 135 of the comparator 134. In the network transmission control 131, the data packet 107 is not transmitted to the network 101 during normal operation.

The receiving process is the same as that for debugging support. In this embodiment, in order to distinguish between debugging support and normal operation,
Mode register 1 in the data transmitter 130 of each processor
37 are provided. This mode register 137 is set by the instruction processor 130, and the network transmission control 131
Sent to The network transmission control 131 uses the mode register 137 to distinguish between debugging support and normal operation processing.

FIG. 2 shows an embodiment in which the embodiment shown in FIG. 1 is provided with means for limiting the range in which data packets are transmitted to a network in a designated order. This means is provided with registers 232 and 233 for holding the upper limit (UPPER) and the lower limit (LOWER) of the transmission sequence number for transmitting the data packets in the designated order in the data transmitting device 230, and the SQN of the data transmission buffer 132 and the Compare 232,233, UPPER232 and LOW
Only data packets between ER233 are transmitted in the specified order.

Hereinafter, description will be made with reference to FIG. In the transmission process, the instruction processor 140 performs the operation described with reference to FIG. In the data transmission device 230, when activated by the instruction processor 140, the comparator 134 compares the register 133 holding the transmission sequence number with the SQN of the data transmission buffer. The result of the comparison is sent to the network transmission control 231 by a signal 135. The comparator 234 compares the SQN of the data transmission buffer 132 with the UPPER 232 and the LOWER 233. This comparator 234
SQN of data transmission buffer 132 is UPPER232 and LOWER2
It is determined whether or not it is within the range indicated by 33. Here, it is assumed that the values of UPPER232 and LOWER233 have been set in the instruction processor 140 in advance. Comparator 2
The result of 34 is sent by signal 235 to the network transmission control 231.

In the network transmission control 231, the comparison result 235
When the value is outside the range indicated by UPPER232 and LOWER233, the data packet 102 is transferred to the network 10 regardless of the comparison result 135.
Perform processing to send to 1. Then, the data packet 102
After transmitting the data packet 107 to the network 101, the data packet 107 is transmitted as described with reference to FIG.

On the other hand, when the comparison result 235 is within the range indicated by UPPER 232 and LOWER 233, the network transmission control 231 performs control based on the comparison result 135 and performs the operation described in FIG. The operation described in FIG. 1 is also performed for the receiving process.

As described above, according to this embodiment, when data is transferred between processors, it is possible to control so that only one packet flows on the network, and the packets are transferred to the network in the designated order. Can be sent.

Further, in the embodiment shown in FIG. 1, there is provided a register 133 for holding the transmission sequence number and a means for comparing with a value determined in advance by the instruction processor 140, and when the comparison result matches, the processing of the instruction processor 140 is stopped. You can also. As a result, all the processors can be stopped at the same time, and the efficiency of program debugging is improved by checking the operating state of each processor at this time.

〔The invention's effect〕

According to the present invention, in a parallel processor in which each processor performs data transfer at an arbitrary time asynchronously with the processing of each processor, when performing program debugging of the parallel processor, only one packet flows on the network. In this manner, the packets can be sent to the network in the designated order, so that reproducibility in the parallel processor program execution can be guaranteed, and the efficiency of the parallel processor program debugging can be improved.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 2 is shown in FIG.
9 is an embodiment of the present invention provided with means for limiting the range of the order of sending to the network. 101… Network, 102,107 …… Data packet, 11
0,111… Processor, 120… Data receiving device, 130…
... data transmission device, 140 ... instruction processor, 150 ... local storage, 133 ... register holding transmission sequence number, 134 ... comparator, 137 ... mode register for separating normal operation and debug operation.

Continuing on the front page (72) Inventor Koichiro Menda 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shigeo Nagashima 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi, Ltd. In-house (72) Inventor Kazuo Ojima 1 Horiyamashita, Hadano City, Kanagawa Prefecture Inside the Kanagawa Plant of Hitachi, Ltd.

Claims (1)

(57) [Claims] An apparatus for supporting program debugging of a parallel processor having a communication path for performing data transfer between a plurality of processors and each processor. First means for designating the order of data transfer, second means common to each processor for maintaining the order of transmission to the communication path, and the second means each time data transfer between processors is performed. A third means for updating the order of the means, a fourth means for comparing the contents of the order of the first means and the second means, and a third means for designating one of a debug support mode and a normal operation mode. In the case where the designation of the fifth means and the designation of the fifth means is a debug support mode, when the comparison result of the fourth means is the same, Data transfer is performed, and when the comparison results do not match, the data transfer between the processors is stopped. When the designation of the fifth means is a normal operation mode, regardless of the comparison result of the fourth means. Sixth means for controlling data transfer between processors,
A program debugging support device for a parallel processor, comprising: