JP2590772B2 - Fault cross section observation method and device for IC chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for observing a fault cross section for an IC chip, and more particularly to a method and an apparatus for observing a fault cross section for an IC chip for detecting and analyzing a fault on a semiconductor IC chip.

[0002]

2. Description of the Related Art Conventionally, this kind of failure analysis is performed, for example, by using FIG.
As shown in (1), a failure location is estimated using an EB (Electron Beam) tester or the like (first process: 50), and then a cross section of the failure suspected location is exposed using an FI beam (Focused Ion Beam) (second process). : 51) and then SIM
(Scanning Ion Microscope) A method of detecting a physical defect by observing an image or an SEM image has been employed. FIG. 6A shows a potential distribution image by the EB tester. Here, reference numeral 60 indicates an image of the captured wiring. FIG. 6B shows a SIM image. Here, reference numeral 61 indicates a scratch provided as a mark.

[0003]

In this conventional failure analysis method, when exposing a cross section with an FI beam, if a physical defect does not appear on the chip surface, a clear place where the cross section should be exposed cannot be specified. Therefore, accurate cross-section exposure may not be possible.

Here, there are the following two reasons why a clear place where the cross section should be exposed cannot be specified.

[0005] The SIM image obtained by the FI beam apparatus can only obtain information on a very small surface of the chip. Therefore, it is difficult to determine the position of a device having a flat chip surface today.

[0006] Even if the point to be observed can be identified quite clearly by scratching the chip with a laser or the like after estimating the suspected failure part, voids in the wiring and via holes that cannot be seen from the surface as shown in FIG. 6B. It is difficult to clearly limit the positions such as.

FIG. 6B shows an example of the SIM image described above. In this case, since it is flattened, nothing is visible except for the scratches on the marks.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to improve the disadvantages of the prior art, especially for an IC chip capable of clearly specifying a section to be exposed on a semiconductor IC chip and effectively capturing predetermined observation information. It is an object of the present invention to provide a method for observing a fault cross section and an apparatus therefor.

[0009]

According to the first aspect of the present invention, there is provided a first method for narrowing down a suspected fault location on a semiconductor IC chip.
, A second step of supplying a current to the location narrowed down in the first step, and a third step of irradiating the focused area in the location narrowed down in the first step. A configuration including a fourth step of detecting a change in current and a fifth step of locating the current change on the display unit based on the detected current change signal and performing sectioning by an ion beam. Has been adopted.

The invention according to claim 2 adopts a configuration in which the first to fifth steps are executed in the same apparatus.

According to the third aspect of the present invention, a sample stage capable of transferring a semiconductor IC chip to a three-dimensional space, and an ion beam for outputting a predetermined ion beam to the semiconductor IC chip mounted on the sample stage A current change detection unit that supplies a predetermined inspection current to the semiconductor IC chip and detects a change in the semiconductor IC chip, based on information from the ion beam from the beam generation unit and current change information from the current change detection unit And a display section for displaying a current change position in the ion beam cross section.

This aims to achieve the above-mentioned object.

[0013]

[Operation] Before performing the cross-sectional exposure with the FI beam,
A target wiring or a wiring serving as a mark can be clearly obtained as an image in the BIRCH image (corresponding to the above).

In the IBIRCH image, the target wiring and the void in the via hole are clearly displayed as an image (corresponding to the above).

[0015] Since these steps are performed in the same apparatus, the FIB can be easily obtained with the positional information clearly obtained.
Cross-section can be exposed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

In the embodiment shown in FIG. 1, first of all,
As shown in FIG. 1A, a first step 10 for narrowing down a suspected failure location on a semiconductor IC chip is performed. The first step 10 is to narrow down a failure location using an EB tester (electron beam tester) or the like.

Subsequently, in the middle stage 11, IBIRCH (Io
A process of capturing a wiring image and a defect image by an n Beam Induced Resistance Change method is performed. This IBI
In the RCH method, an image is obtained by irradiating an ion beam while scanning a target area, detecting a change in resistance of a target wiring as a change in current in synchronization with the irradiation, and displaying the change as luminance on a CRT for each irradiation position. It is.

For this reason, in this middle stage 11, FIG.
As shown in FIG. 5, a second step 11A for supplying a current to the location narrowed down in the first step 10 described above, a third step 11B for irradiating the focused location with the focused ion beam, and Fourth step 1 for detecting change in current
1C.

The IBI executed in the middle stage 11
While observing the exact position where the cross section should be exposed by the RCH method, a cross section is formed by an ion beam while positioning the current change on the display unit in a later fifth step 12.

In this case, each of the middle and subsequent steps is performed by an IC chip failure section observation apparatus shown in FIG.

The device for observing a fault cross section for an IC chip shown in FIG. 2 has a sample table 21 capable of transferring a semiconductor IC chip to a three-dimensional space position, and a semiconductor IC chip (sample) mounted on the sample table 21. An ion beam generator 23 for outputting a predetermined ion beam B to the semiconductor device 22;
A current change detection unit 24 is provided for supplying a predetermined test current to the chip 22 and detecting a change in the current. Sign 2
Reference numeral 5 denotes an image display unit that displays a current change position in the ion beam cross section based on information on the ion beam B from the beam generation unit 23 and current change information from the current change detection unit 24. Reference numeral 26 denotes a power supply.

FIG. 3 shows an operation result of the embodiment shown in FIGS. In FIG.
First, in FIG. 3A, a suspected failure location is narrowed down by a potential distribution image of the EB tester. After that, the DUT (Device Under Test) is moved to the sample chamber of the ion beam B, and the same operating conditions as those in which the above-mentioned failure suspected portion can be observed in the potential distribution image are electrically added, and the IBIRCH image is observed. By such a procedure, as shown in FIG.
Defects there can be observed. In FIG. 3, reference numeral 30 indicates a wiring image, and reference numeral 31 indicates a captured defect image.

FIG. 4 shows another embodiment. In the embodiment shown in FIG. 4, a suspected failure location is first narrowed down by an IBIRCH image (FIG. 4A). In this case, IBIRCH
The narrowing down of the failure suspected area by the image is effective when the abnormality of the potential is not remarkable but the abnormality of the current is remarkable like the I _DDQ failure.

Such narrowing down is performed at a relatively low magnification of, for example, 100 times, because it is necessary to search a wide range of chips. Thereafter, by observing at a high magnification of, for example, 3,500 times, a defect that may cause a failure can be observed (FIG. 4B). In FIG. 4, reference numeral 33 indicates a wiring image, and reference numeral 34 indicates a captured defect image.

[0026]

As described above, according to the present invention,
In the step of exposing a cross section on a semiconductor IC chip, a cross section should be exposed on a semiconductor IC chip when exposing a device chip having a flattened surface and exposing a lower layer portion of a multilayer wiring, which has been difficult in the past. It is possible to clearly specify the location, and also to limit the positions of wiring and voids in via holes that are difficult to see from the surface, which was difficult in the past, and to expose the cross section efficiently In addition, it is possible to provide an unprecedented excellent method for observing a faulty cross section for an IC chip and a device therefor, which enable cross section exposure with a high success rate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a schematic configuration diagram showing an apparatus for executing the embodiment of FIG. 1;

FIGS. 3A and 3B are explanatory views showing the cross-section exposure method obtained in FIGS. 1 and 2. FIG. 3A shows a potential distribution image obtained by an EB tester, and FIG. 3B shows wiring and an image captured by an IBIRCH image. It is explanatory drawing which shows the example of a defect.

FIG. 4 is an explanatory view showing another example of a cross-section exposure method.
FIG. 4A is a diagram showing an example of narrowing down a current abnormal part using an IBIRCH image, and FIG. 4B is an enlarged explanatory diagram of a defective portion in FIG. 4A showing an example of wiring and defects captured by an IBIRCH image. .

FIG. 5 is a process chart showing a conventional example.

FIG. 6 is a view showing an example of an image obtained in FIG. 5;
(A) shows a potential distribution image by the EB tester, and FIG.
(B) shows a SIM image.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st process 11A 2nd process 11B 3rd process 11C 4th process 12 5th process 21 Sample stage 22 Semiconductor IC chip 23 Ion beam generation part 24 Current change detection part 25 Image display part

Claims (3)

(57) [Claims] 1. A first step of narrowing down a suspected portion on a semiconductor IC chip, a second step of supplying a current to the narrowed down portion in the first step, and a narrowing down in the first step. Of irradiating a focused ion beam on the spot
And a fourth step of detecting a change in the supplied current, locating the current change in the image display unit based on the detected current change signal, and performing cross sectioning with an ion beam. A method for observing a fault cross section for an IC chip, comprising a fifth step of performing. 2. The method for observing a fault cross section for an IC chip according to claim 1, wherein the first to fifth steps are performed in the same apparatus. 3. A sample stage capable of transferring a semiconductor IC chip to a three-dimensional space position, and a semiconductor IC mounted on the sample stage.
An ion beam generator that outputs a predetermined ion beam to the C chip; and a current change detector that supplies a predetermined inspection current to the semiconductor IC chip and detects a change in the current. A fault cross section observation device for an IC chip, comprising: an image display section for displaying a current change position in an ion beam cross section based on information by an ion beam and current change information from a current change detection section.