JP2590973B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device for forming an insulated gate (IG, MIS) type semiconductor element using a layer made of a polycrystalline semiconductor formed on a substrate. And a method for producing the same.

[Conventional technology]

Conventionally, a layer made of polycrystalline silicon is formed in a predetermined region on a substrate, and the layer is covered with an oxide film. Then, a gate electrode is formed through the oxide film, and a predetermined wiring is formed. Various semiconductor devices having a structure in which a semiconductor element of a die type is formed have been proposed. In the process of manufacturing such a device, if the unevenness of the surface of the polycrystalline silicon becomes large when polycrystalline silicon is buried on the substrate by the CVD method etc., the withstand voltage of the oxide film formed on the surface decreases. As a result, for example, when a semiconductor element such as a MOSFET is formed, the gate withstand voltage is reduced.

In particular, in the case where an oxide film such as silicon dioxide is formed on a silicon substrate as a substrate such as a so-called SOI (Silicon On Insulator) structure and polycrystalline silicon is buried thereon, polycrystalline silicon is used. Since the underlying oxide film of amorphous is amorphous, polycrystalline silicon formed thereon has large irregularities on its surface, and the gate withstand voltage is significantly reduced. Therefore, a sufficient gate voltage is applied. Cannot be performed, and there is a problem that it is weak against noise.

In view of the above, the present invention has been made in view of the above points, and provides a method of manufacturing a semiconductor device in which a surface of a layer made of a polycrystalline semiconductor is satisfactorily planarized. The purpose is to improve performance and reliability.

[Means for solving the problem]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a layer of a polycrystalline semiconductor on a substrate; oxidizing a surface of the polycrystalline semiconductor layer to form an oxide film; Performing a step of flattening the surface of the semiconductor layer; a step of removing the oxide film; a step of solid-phase growing the polycrystalline semiconductor layer after the oxide film removing step; and a patterning of the polycrystalline semiconductor layer. Forming an insulating film on the surface of the island made of the polycrystalline semiconductor, and forming an insulated gate semiconductor element using the island as a semiconductor substrate. It is characterized by.

[Action]

According to the above manufacturing method, since the polycrystalline semiconductor layer is oxidized before the solid phase growth, the oxidation is performed in a state where the grain size in the polycrystalline semiconductor layer is small, and the oxidation reaction Be active along. Therefore, the convex portions on the surface are oxidized well, and the surface of the polycrystalline semiconductor layer is flattened.

〔Example〕

 Hereinafter, the present invention will be described using embodiments shown in the drawings.

1 (a) to 1 (h) are cross-sectional views for explaining a manufacturing method of a first embodiment of the present invention in the order of steps. This first embodiment is an insulated gate semiconductor device according to the present invention. MOSF
This is an example of forming T.

First, as shown in FIG. 1 (a), the main surface of a single crystal silicon substrate 1 is thermally oxidized to form a silicon oxide film 2 having a thickness of about 5000 °, and then, for example, a reduced pressure is applied on the silicon oxide film 2. A polycrystalline silicon layer 3 having a thickness of about 1000 to 1500 ° is deposited by a CVD method. At this time, the polycrystalline silicon layer 3
The diameter of the inside is about 0.1 μm, and the unevenness of the surface is much larger than the surface of the single crystal silicon substrate.

Next, as shown in FIG.
Oxidation with dry oxygen at a temperature of 1000 to 1100 ° C (hereinafter referred to as “flattening oxidation”
Is performed to form an oxide film 4 having a thickness of about 500 to 1000 °. At this time, the surface of oxide film 4 has an uneven shape, but the surface of polycrystalline silicon layer 3 thereunder is planarized.

Next, as shown in FIG. 1 (c), the oxide film 4 is removed by an etching solution such as HF (hydrofluoric acid), and then the Si ⁺
The polycrystalline silicon layer 3 is made amorphous by ion implantation to form an amorphous silicon layer 5. Note that this ion implantation is a step performed for solid phase growth to be described later.
For example, it is performed at 60 to 80 KeV and at a dose of about 5 × 10 ¹⁵ cm ⁻² . As the ions to be implanted in addition to the Si ⁺ ions Ge ⁺
It is possible to use ions which do not adversely affect the semiconductor such as, for example.

Next, as shown in FIG.
Solid phase growth annealing is performed under the conditions of about 0 ° C. and about 50 H to form a polycrystalline silicon layer 6 having a grain size of about 1 μm. Then, P (phosphorus), which is an N-type impurity, is ion-implanted as channel doping at about 40 KeV and about 1 × 10 ¹¹ cm ⁻² .

Next, as shown in FIG. 1E, the polycrystalline silicon layer 6 is patterned into a predetermined shape by a normal photo-etching process to form an island 6a of the polycrystalline silicon layer. Oxidation with dry oxygen to reduce film thickness
A gate oxide film 7 of about 800 to 1000 ° is formed on the surface of the island 6a.

Next, as shown in FIG. 1 (f), after phosphorus-doped polycrystalline silicon is formed, a gate electrode 8 is formed by patterning it into a predetermined shape by photo-etching, and the surface is heated to a temperature of about 1000 ° C. Oxidize.

Next, as shown in FIG. 1 (g), a P-type impurity such as B (boron) is ion-implanted using the gate electrode 8a as a mask at 40 KeV and a dose of about 1 × 10 ¹⁵ cm ⁻² , and a source and a drain are formed. Areas 6a ₁ and 6a ₂ are formed. Subsequently, annealing is performed in a nitrogen atmosphere at a temperature of 1000 ° C. for about 30 minutes to perform an activation process. Then, as shown in FIG. 1 (h), a P-channel MOSFET is formed by forming an interlayer insulating film 9 and an Al wiring 10 using a normal semiconductor processing step.

Here, the first embodiment is characterized in that planarization oxidation is performed before solid-phase growth of polycrystalline silicon, and the operation and effect of the flattening oxidation will be described below.

That is, according to the first embodiment, FIG.
As shown in (b), flattening oxidation is performed in a state where the grain size is small before solid phase growth, so that an oxidation reaction is activated along the grain boundaries, and the surface of the polycrystalline silicon phase has In particular, the convex portion is not only oxidized from the surface side (upper side in the figure) but also oxidized from the side surface direction proceeding from the grain boundary, and the oxidation reaction proceeds faster by that amount. Therefore, after oxidation, the entire surface is flattened and a good surface is obtained.

On the other hand, assuming a manufacturing process of flattening and oxidizing after solid phase growth, as shown in FIGS. 3 (a) and 3 (b),
Since the grain size of the polycrystalline silicon layer 3a is increased by the crystal growth by solid phase growth, oxidation from the grain boundaries as described above hardly progresses, and only oxidation from the surface side progresses. Therefore, even if flattening oxidation is performed, the uneven shape on the surface of the polycrystalline silicon layer 3a almost reproduces the state before oxidation, and the effect is small.

FIG. 4 is a view showing an experimental result by the present inventors,
The graph shows the gate breakdown voltage depending on the presence or absence of the planarization oxidation step or the difference in the order between the step and the solid layer growth step.
From this figure, it can be seen that when the planarization oxidation is performed before the solid layer growth, the gate breakdown voltage is almost doubled, and the present invention is effective. Note that this experimental result shows that the gate oxide film
Performed on 880mm MOSFET.

Next, a second embodiment of the present invention will be described with reference to the sectional view shown in FIG.

The second embodiment is an example in which a MOS capacitance is formed as an insulated gate type semiconductor device according to the present invention, and FIG. 5 shows the final figure.

Then, in the manufacturing process, the first polycrystalline silicon layer 11 is formed in a predetermined region on the silicon oxide film 12, and after the flattening oxidation is performed in the same manner as in the first embodiment, solid-phase growth is performed and the surface is formed. Flatten. Thereafter, an oxide film 12 is formed in a predetermined region on the surface of the first polycrystalline silicon layer 11, and a second polycrystalline silicon layer 13 is further formed on the oxide film 12, similarly to the first embodiment. The interlayer insulating film 9,
And an Al wiring 10 connected to the first and second polycrystalline silicon layers 11 and 13, respectively. In the second embodiment, components that can be formed in the same steps as in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

Therefore, also in this embodiment, the first polycrystalline silicon layer 11 is formed.
Is flattened satisfactorily, so that the gate breakdown voltage of the oxide film 12 formed thereon is improved, and the capacity of the MOS capacitance can be increased.

Although the present invention has been described with reference to the first and second embodiments, the present invention is not limited thereto and can be variously modified without departing from the gist thereof. A channel MOSFET may be configured. or,
Without being limited to the SOI structure, for example, a polycrystalline semiconductor layer may be formed over an insulating substrate. In the flattening oxidation step, the oxidation may be performed by wet oxidation. However, in wet oxidation, the oxidation rate from the grain boundaries is too fast, and it is difficult to control the dry oxidation.

〔The invention's effect〕

As described above, according to the present invention, an oxide film is formed on the surface of the polycrystalline semiconductor layer, and solid-phase growth is performed after removing the oxide film, so that the surface of the polycrystalline semiconductor layer can be planarized. There is an effect that the gate breakdown voltage of the insulated gate semiconductor element can be improved in a state where the grain size in the polycrystalline semiconductor layer is increased, and its performance and reliability can be improved.

[Brief description of the drawings]

1 (a) to 1 (h) are cross-sectional views for explaining a first embodiment of the present invention in the order of steps, and FIGS. 2 (a) and 2 (b) perform flattening oxidation before solid phase growth. 3 (a) and 3 (b) are cross-sectional views showing an operation state when flattening oxidation is performed after solid phase growth, and FIG. 4 is a cross-sectional view showing a gate due to a difference in process. FIG. 5 shows a breakdown voltage, and FIG. 5 is a sectional view for explaining a second embodiment of the present invention. 1 ... single crystal silicon substrate, 2 ... silicon oxide film, 3, 6 ...
... polycrystalline silicon layer, 4 ... oxide film, 5 ... amorphous silicon layer, 6a ... island, 7 ... gate oxide film, 8 ... gate electrode.

Claims (4)

(57) [Claims] A step of forming a layer of a polycrystalline semiconductor on a substrate; a step of oxidizing a surface of the polycrystalline semiconductor layer to form an oxide film to planarize a surface of the polycrystalline semiconductor layer; A step of removing an oxide film; a step of solid-phase growing the polycrystalline semiconductor layer after the oxide film removing step; and a step of forming an island of a polycrystalline semiconductor by patterning the polycrystalline semiconductor layer. Forming an insulating film on the surface of the island made of the polycrystalline semiconductor, and forming an insulated gate semiconductor element using the island as a semiconductor substrate. 2. The method according to claim 1, wherein the step of oxidizing the surface of the polycrystalline semiconductor layer is a step of performing dry oxidation. 3. The method according to claim 1, wherein the step of forming the insulated gate semiconductor element is a step of forming a MOSFET. 4. The method according to claim 1, wherein the step of forming the insulated gate semiconductor element is a step of forming a MOS capacitance.