JP2591684B2 - Execution confirmation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an execution confirmation method of an information processing device having a plurality of built-in processing devices in order to improve reliability, and relates to a terminal of a comparison circuit even when a cache is provided in a CPU. The purpose of the present invention is to reduce the number to reduce the cost and to guarantee the real-time reliability of the processing, and to connect to the output side of the instruction address register (45) to read the contents of the instruction address register. An external terminal (31a) that outputs to the outside of the processor as an execution confirmation signal,
An external terminal (31) which is connected to the flag output side of (8) and outputs a flag indicating the state of the data of the operation result from the operation unit (48) to the outside of the processor as an execution confirmation signal.
a) or an external terminal (31a) connected to the flag output side of the computing unit (48) and outputting a flag, which is one of the computation results, from the computing unit (48) to the outside of the processor as an execution confirmation signal Is provided.

[Industrial applications]

The present invention relates to an execution confirmation method for an information processing device incorporating a plurality of processing devices to improve reliability.

[Conventional technology]

Conventionally, as shown in FIG. 5, an execution confirmation method implemented in an information processing apparatus includes two CPUs (central processing units) 1 and 2 each including a microprocessor and the same CPUs 1 and 2.
And a control signal, address, data, etc. from both CPUs 1 and 2 to synchronize the
And a comparison circuit 4 having a data bypass function for checking whether or not the processings of the CPUs 1 and 2 match each other. When data is input to the CPU 2, the data is directly transmitted to the CPU 2 through the comparison circuit 4 but using the data bypass function without using the comparison function.

As shown in FIG. 6, the CPU 1 or 2 receives control signals,
An external interface 11 for transmitting addresses, data, and the like to the system bus 5 and the comparison circuit 4, and an instruction cache for storing instructions input via the external interface 11
12, an operand cache 13 for storing operands input via the external interface 11, and an instruction decoder 14 for decoding instructions read from the instruction cache 12.
An instruction address register 15 for storing an output from the instruction decoder 14, an execution control unit 16 for executing the instruction decoded by the instruction decoder 14, an operand cache 13 and a general-purpose register 17 controlled by the execution control unit 16, And an arithmetic unit 18 for executing an operation while inputting / outputting data between them.

In the execution confirmation method in this information processing apparatus, the same processing is executed by synchronizing the CPU 1 and the CPU 2 with the output of the clock 3, and the output results executed at the same time are compared by the comparison circuit 4. It checks whether they match or not, and confirms whether the processing is performed correctly.

[Problems to be solved by the invention]

In the above-mentioned conventional execution confirmation method, in order to assure the reliability of the processing by confirming that the two CPUs 1 and 2 give the same processing result, the bus (which constitutes an external bus) Line) is connected to the comparison circuit 4 to compare whether the operations on the bus match.

Therefore, since the number of signal lines of the address bus and the data bus is large, the number of terminals of the comparison circuit 4 is increased, and the cost is increased. Further, in a device in which the CPUs 1 and 2 have the instruction cache 12 or the operand cache 13, the access of the instruction or the operand is affected by the time lag for going outside, and the content of the processing is compared with the comparison circuit 4 in real time. If the comparison cannot be performed, especially when the operand cache is write-back or copy-back, it may take a considerable time for even the stored data to come out to the outside, and the comparison cycle becomes slow.

Therefore, due to such structural factors, even when an information processing device having a high reliability is configured in a CPU redundant configuration, the system cost is high and the real-time reliability of the process is guaranteed. There was a problem that it was not possible.

The present invention has been made in view of the above problems,
The technical problem set to solve the problem is that even if the CPU has a cache, the number of terminals of the comparison circuit can be reduced to reduce the cost and to guarantee the real-time reliability of the processing. An object of the present invention is to provide an execution confirmation device as described above.

[Means for solving the problem]

The present invention, as a specific means for solving the above-mentioned problems, comprises an instruction cache for storing an instruction to be executed as shown in an embodiment of FIG. (42), an instruction decoder (44) for decoding the instruction read from the instruction cache (42), and storing the output from the instruction decoder (44), updating the address in accordance with the execution of the instruction, and updating the instruction cache (44). An instruction address register (45) to be output to the instruction control unit (42), an execution control unit (46) for controlling instruction execution, an operation unit (48) for performing an operation according to the control of the execution control unit (46), and storing the operation result. A microprocessor (31) having a general-purpose register (47);
5) An external terminal (31a) connected to the output side for outputting the contents of the instruction address register to the outside of the processor as an execution confirmation signal is provided.

This is connected between the output side of the instruction address register (45) and the input side of the external terminal (31a), as shown in the embodiment of FIG. 1 or FIG. A signal degenerating means (49b or 52) for degenerating a signal from the address register (45) into a signal having a smaller number of bits than the input signal is provided.
52), a signal obtained by reducing the number of bits of all or part of the contents of the instruction address register to a smaller number of bits is used as an execution confirmation signal as the external terminal (31a).
It is desirable to output the data via a.

As shown in the embodiment of FIG. 3, an instruction cache (42) for storing an instruction to be executed, an operand cache (43) for storing data necessary for executing the instruction,
An instruction decoder (44) for decoding an instruction read from the instruction cache (42);
An instruction address register (45) for storing the output from the CPU and updating the address according to the execution of the instruction and outputting the updated address to the instruction cache (42); and an execution control unit (46) for controlling the execution of the instruction
And a computing unit (48) that performs an operation according to the control of the execution control unit (46), and a general-purpose register (47) that stores the operation result. Side, the computing unit (48)
And an external terminal (31a) for outputting a flag, which is one of the calculation results, to the outside of the processor as an execution confirmation signal.

Further, as shown in FIG. 4, an instruction cache (42) for storing an instruction to be executed, an operand cache (43) for storing data necessary for executing the instruction, and a read-out instruction from the instruction cache (42). An instruction decode (44) for decoding the instruction, an instruction address register (45) for storing an output from the instruction decode (44), updating an address according to the execution of the instruction, and outputting the updated address to the instruction cache (42); An execution control unit (46) for controlling instruction execution;
An arithmetic unit (4) that performs an operation according to the control of the execution control unit (46)
8) and a microprocessor (31) having a general-purpose register (47) for storing an operation result, connected to the output side of the execution control unit to indicate whether the execution of a branch instruction has changed the program sequence. An external terminal (31a) for outputting a branch instruction signal from the execution control unit to the outside of the processor as an execution confirmation signal is provided.

(Operation)

According to the configuration described above, if any processing of each microprocessor at the same time has an error, the present invention compares the signals directly output from the external terminals 31a and 32a by the comparison circuit, and It is found that the processing is an error, and if it is an error, an error detection signal is output, and each of the microprocessors 31 and 32 inputs an error detection signal from each of the external terminals 31a and 32a, and outputs the The execution is stopped, and the transmission of data or the like is interrupted with the stop. This allows each microprocessor 3
It is possible to directly confirm in real time that the processing is correctly performed for each of 1, 32, and high reliability can be guaranteed. In addition, since the processing in each of the microprocessors 31 and 32 can be confirmed with the minimum necessary data, the number of connection terminals is reduced, which contributes to cost reduction.

〔Example〕

Hereinafter, as an embodiment of the present invention, a case where an instruction address or its degeneration signal, a flag which is one of operation results, or a branch instruction signal is used as a signal output during execution of each microprocessor will be described. .

FIG. 1 shows a first embodiment. Here, 31 and 32 are CPUs each composed of a one-chip microprocessor, one for executing necessary processing, and the other for executing the same processing for confirming the processing. is there.

The CPUs 31 and 32 each have an external terminal 31 for directly outputting the data being processed without passing through the external interface 41.
a, 32a, and that the processing of one device 31 or 32 matches the processing of the other device 32 or 31 with the data generated at the same time taken out through the external terminals 31a and 32a. Be able to confirm.

The internal configuration of the CPU 31 (or 32) includes control signals,
System bus (not shown) for address and data
And an instruction cache for storing instructions input through the external interface 41
42, a copy-back type operand cache 43 for storing operands input via the external interface 41
An instruction decoder 44 for decoding the instruction read from the instruction cache 42, an instruction address register 45 for storing an output from the instruction decoder 44, an execution control unit 46 for executing the instruction decoded by the instruction decoder 44, An arithmetic unit 48 controlled by the control unit 46 to execute an operation while inputting / outputting data between the operand cache 43 and the general-purpose register 47, and the data generated during processing are directly used for comparison by the comparison device 34 side. And an external terminal 31a (or 32a) for inputting an error detection signal from the side of the comparison device 34, which is output when the comparison result is inconsistent.

The output side of the instruction address register 45 and the external terminal 31a (or 32a) are connected by an internal bus 49a so that all the instruction addresses can be output from the external terminal 31a (or 32a), or the internal bus 49a The exclusive OR circuit 49b as signal degeneration means is interposed to output exclusive OR of adjacent bit data, thereby outputting data (degeneration data) with a reduced number of output data bits. Be able to do it.

The execution control unit 46 and the external terminal 31a (or 32a) are connected by a signal line 49c so that the error detection signal input by the execution control unit 46 can be received as a halt signal, and the subsequent processing is interrupted. To be able to

When the CPUs 31 and 32 configured as described above are checked for coincidence, the following procedure is performed.

Each of the CPUs 32, 32 transmits the contents from the instruction address register 45 to the internal bus 49a and the external terminal 31a or 32a when the arithmetic unit 48 proceeds with the processing according to the instruction from the execution control unit 46.
, Respectively, to the comparison device (not shown) at the same time.

The comparison device does not output a signal when the contents input from both CPUs 31 and 32 match, and transmits a 1-bit error detection signal to each CPU 31 and 32 when they do not match.

In each of the CPUs 31 and 32, the error detection signal is supplied to the external terminals 31a and 32a.
And input to the execution control unit 46 via the signal line 49c, and the execution control unit 46 stops the processing of the arithmetic unit 48.

When an error detection signal is input, an input / output system interrupt mechanism (not shown) is operated to interrupt input / output of control signals, addresses, data, and the like.

As described above, in the first embodiment, the contents of the instruction address register 45 can be directly taken out via the external terminals 31a and 32a, and the output data can be compared by the comparison device 34. , 32 at the same time can be confirmed in real time by an external device (comparator).

Further, by inputting the output from the instruction address register 45 or its degenerated data to an external device, the number of terminals of the external device can be reduced, and the CPU
An external comparison device can be made inexpensive, easy to assemble into an LSI, simplifies the package for incorporation, facilitates printed wiring, reduces overhead, and has high reliability. Can be reduced in price.

As another mode of the first embodiment (CPU 31 or 32), as shown in FIG. 2, a part of the lower digits of the instruction address is transmitted.

The lower digit output side of the instruction address register 45 and the external terminal 31
a (or 32a) is connected by the internal bus 51 so that a part of the lower digits of the instruction address can be output from the external terminal 31a (or 32a), or the internal bus 51 can be exclusively used as signal compression means. The degenerate data can be output through a logical OR circuit 52, and the rest of the CPU 3
The configuration is the same as the configuration of 1 (or 32).

In general, since the execution of a program proceeds sequentially, it is sufficiently practical to compare only the lower digits, whereby the number of terminals can be further reduced and the internal operation can be easily confirmed by an external device.

In the second embodiment, as shown in FIG.
Signal line that outputs a flag that is one of the operation results in
53 is connected to the external terminal 31a (or 32a), and the other parts are configured similarly to the CPU 31 (or 32).

As a result, various flags can be output during the operation, and the external device can check the internal execution sequence.

In the third embodiment, as shown in FIG. 4, a signal line 54 for outputting a branch signal from the execution control unit 46 is connected to the external terminal 31a.
(Or 32a), and the other parts
The configuration is the same as the configuration of the PU 31 (or 32).

Thus, every time the execution control unit 46 changes the program sequence to execute the branch instruction, a branch signal is output from the execution control unit 46 each time, and the internal operation can be confirmed by the external device.

According to the various embodiments of the CPU 31 (or 32), the correctness of the processing can be checked in real time for both CPUs 31 and 32, and the number of terminals is reduced in the comparison device as the checking device. As a result, manufacturing costs can be reduced.

〔The invention's effect〕

As described above, in the present invention, the instruction address register (4
5) is connected to an external terminal (31a) for outputting the contents of the instruction address register to the outside of the processor as an execution confirmation signal or to a flag output side of a computing unit (48), Connects to the external terminal (31a) that outputs the status of the data of the operation result from the unit (48) as an execution confirmation signal to the outside of the processor, or to the output side of the execution control unit, and executes the branch sequence to execute the program sequence. A branch instruction signal indicating whether or not
By providing the external terminal (31a) for outputting from the execution control unit as an execution confirmation signal to the outside of the processor, even when observing a bus or the like for accessing the external memory due to the provision of the built-in cache, it cannot be observed For the internal operation, a signal for separately confirming the internal state is output from the external terminal (31a) so that the external device can easily check the correctness of the processing of the microprocessor (31) based on the output signal. Malfunctions can be detected by comparing with the dual operation, and the signals output from the external terminals (31a, 32a) provided in the built-in microprocessors (31, 32) can be compared and examined. By doing so, it is possible to detect a synchronization shift between the microprocessors (31, 32).

Therefore, when an error in the processing is found, each microprocessor (3
1, 32) can be stopped in a timely manner, and transmission of control signals, addresses, data, etc., to the output system can be interrupted. As a result, it is possible to directly confirm in real time that the processing is correctly performed for each of the microprocessors (31, 32), and it is possible to guarantee high reliability.

In addition, since the processing in the plurality of microprocessors (31, 32) can be confirmed using the minimum necessary data, the number of connection terminals can be minimized in the configuration, and the number of connection terminals can be minimized. Costs can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural explanatory view of a first embodiment of the present invention, FIG. 2 is a structural explanatory view showing another embodiment of the first embodiment, and FIG. FIG. 4 is a structural explanatory diagram of a third embodiment, FIG. 5 is a structural diagram showing an execution confirmation method in a conventional information processing apparatus, and FIG. 6 is a conventional microprocessor configuration. FIG. 31, 32: Microprocessor (CPU) 31a, 32a: External terminal 42: Instruction cache 43: Operand cache 44: Instruction decoder 45: Instruction address register 46: Execution control unit 47: General purpose register 48 … Calculators 49a, 51… Internal buses 49b, 52… Signal degeneration means (exclusive OR circuit) 49c, 53, 54… Signal lines

Claims (4)

(57) [Claims] An instruction cache for storing an instruction to be executed, an instruction decoder for decoding an instruction read from the instruction cache, and an output from the instruction decoder. An instruction address register (45) for updating the address in accordance with the execution of the instruction and outputting the updated address to the instruction cache (42); an execution control unit (46) for controlling the execution of the instruction; In a microprocessor (31) having an operation unit (48) for performing an operation and a general-purpose register (47) for storing an operation result, the microprocessor is connected to an output side of the instruction address register (45).
An execution confirmation device, comprising an external terminal (31a) for outputting the contents of the instruction address register to the outside of the processor as an execution confirmation signal. 2. A signal between the instruction address register (45) and an input terminal of an external terminal (31a) is connected between an output side of the instruction address register (45) and an input terminal of an external terminal (31a). A signal degenerating means (49b or 52) for degenerating a small number of signals is provided.
52), a signal obtained by reducing the number of bits of all or part of the contents of the instruction address register to a smaller number of bits is used as an execution confirmation signal as the external terminal (31a).
2. The execution confirmation device according to claim 1, wherein the output is outputted via a communication terminal. 3. An instruction cache (42) for storing an instruction to be executed, an operand cache (43) for storing data necessary for executing the instruction, and an instruction for decoding an instruction read from the instruction cache (42). Decoder (44)
And stores the output from the instruction decoder (44), updates the address in accordance with the execution of the instruction, and updates the instruction cache (4
(2) an instruction address register (45) to be output to an execution control unit (46) for controlling instruction execution;
6) A microprocessor (31) having a computing unit (48) for performing a calculation according to the control and a general-purpose register (47) for storing a calculation result, wherein the microprocessor (31) is connected to a flag output side of the computing unit (48). An execution confirmation device, comprising: an external terminal (31a) for outputting a flag indicating a state of data of an operation result from an operation unit (48) as an execution confirmation signal to the outside of the processor. 4. An instruction cache (42) for storing an instruction to be executed, an operand cache (43) for storing data required for executing the instruction, and an instruction for decoding an instruction read from the instruction cache (42). Decoding (44)
And stores the output from the instruction decode (44), updates the address according to the execution of the instruction, and updates the instruction cache (4
(2) an instruction address register (45) to be output to an execution control unit (46) for controlling instruction execution;
6) A microprocessor (31) having an operation unit (48) for performing an operation according to the control and a general-purpose register (47) for storing an operation result, wherein the microprocessor (31) is connected to an output side of the execution control unit to execute a branch instruction. An execution terminal for outputting a branch instruction signal indicating whether or not a program sequence has been changed by the execution control unit to the outside of the processor as an execution check signal from the execution control unit.