JP2591871B2 - PLO duplex switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dual PLO (P
Hase LockedOscillator) circuit @P
The present invention relates to a switching circuit for switching between the LO working system (N system) and the PLO standby system (E system).

[0002]

2. Description of the Related Art An example of a conventional PLO duplex switching circuit will be described with reference to FIG. In this FIG.
A selection circuit 22 for switching the O clock {the PLO working clock (N system) 3 and the PLO backup clock (E system)} to one of them by an asynchronous switching control signal c, and 22 is a phase of the clock selected by the selection circuit 21. This is a tank circuit that corrects fluctuations and clock interruptions. Reference numeral 9 denotes a switching control signal input terminal to which a switching control signal is applied, and 10 denotes a clock output terminal from which a clock output is obtained.

The PLO duplex switching circuit shown in FIG. 2 includes a PLO circuit @ PLO working (N system) 3 and a PLO
The switching operation is performed by a switching control signal c which is completely asynchronous with the output clock phase of the O spare (E system) 4 #, and the effect is absorbed by the tank circuit 22.

[0004]

The above-mentioned conventional PLO
In the duplex switching circuit, the PLO clock {the PLO working clock (N system) and the PLO spare clock (E system)} are switched by an asynchronous switching control signal, so that the clock has a hazard and the hazard has a tank circuit. And the output clock fluctuates.

[0005]

SUMMARY OF THE INVENTION A PLO duplex switching circuit of the present invention comprises a dual PLO working clock (N
System) and a PLO backup clock (E system), a first selection circuit for switching to one of them by a switching control signal, and correcting the phase fluctuation and clock disconnection of the clock selected by the first selection circuit. In a PLO duplex switching circuit comprising a tank circuit, two NOR circuits having different PLO clocks input to one of input terminals in order to capture a phase of a switching timing from the clock output from the tank circuit and the PLO clock; A second selection circuit for selecting output clocks of the two NOR circuits, and a circuit for retiming an asynchronous switching control signal by the clock selected by the second selection circuit, The dual PLO clock is switched by a control signal.

[0006]

According to the present invention, the switching control signal input asynchronously is converted into a switching signal synchronized with the input clock to eliminate the fluctuation of the input clock of the tank circuit when the system is switched.

[0007]

FIG. 1 is a block diagram showing an embodiment of a PLO duplex switching circuit according to the present invention. In FIG. 1, the same reference numerals as those in FIG. 2 denote corresponding parts, and 1 denotes one of a duplicated PLO clock {PLO working clock (N system) 3 and PLO spare clock (E system) 4} by a switching control signal. Is a tank circuit that corrects the phase fluctuation of the clock selected by the selection circuit 1 and the clock disconnection.

Reference numeral 5 denotes a NOR circuit for producing a switching clock at a PLO backup clock (E system) 4 and a clock output g delayed by 90 ° which is an output of the tank circuit 2, and 6 denotes a PLO working clock (N system) 3. And tank circuit 2
A NOR circuit for producing a switching clock by a clock output g delayed by 90 ° which is the output of the NOR circuit. These NOR circuits are one of the input terminals for detecting the phase of the switching timing from the clock output from the tank circuit 2 and the PLO clock. And two different PLO clocks. 7 is a NOR circuit 5 and NO
This circuit selects a non-operational clock from the output of the R circuit 6. The circuit 7 constitutes a selection circuit for selecting the output clocks of the two NOR circuits. Numeral 8 denotes a flip-flop circuit for making the switching signal inputted asynchronously a timing at which no hazard is generated. This flip-flop circuit 8 is a circuit for retiming the asynchronous switching control signal by the clock selected by the selecting circuit 7. Make up.

[0009] The dual PLO clock is switched by the synchronization control signal after retiming.

FIGS. 3A and 3B are time charts showing waveform examples of respective parts for explaining the operation of FIGS. 1 and 2. FIG.
A current clock (N system) a is shown, (b) is a PLO backup clock (E system) b, (c) is a switching control signal c, and (d) is an output signal d, (e) of the NOR circuit 5. ) Is the actual switching control signal e, which is the output signal of the flip-flop circuit 8, and (f) is the output signal f of the selection circuit 1,
(G) shows the output (clock) g of the tank circuit 2, (h) shows the output signal h of the selection circuit 21 of FIG. 2, and (i) shows the output (clock) i of the tank circuit 22 of FIG. is there.
T indicates a clock width which is an output of the selection circuit 1 in FIG. 1, and t indicates a clock width which is an output of the selection circuit 21 in FIG. Here, the clock width T and the clock width t are not equal.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. First, in the conventional PLO duplex switching circuit shown in FIG.
Hazard occurs at the input of 2. For this reason, the tank circuit 22 is affected by this hazard, and its output fluctuates over several clocks as shown in FIG.

However, the P of the present invention shown in FIG.
The double LO switching circuit has a configuration in which the switching control signal c input from the switching control signal input terminal 9 is retimed by the output of the NOR circuit 5 or the NOR circuit 6 by the flip-flop circuit 8. And this NO
Since the output of the R circuit 5 (see (d) of FIG. 2) or the output of the NOR circuit 6 is the PLO clock (N system or E system) and the NOR of the output of the tank circuit 2, it is input to the NOR circuit. A rising transition point occurs at the “L” level of the PLO clock.

Further, the NOR circuit 5 or the NOR circuit 6
Is selected by the selection circuit 7 on the side generated by the PLO clock to be switched from here. For this reason, the actual switching control signal e (see FIG. 2E) output from the flip-flop circuit 8 is output from the switching destination P
This occurs at the "L" level of the LO clock, and no hazard occurs in the selection circuit 1 when the clock is switched.
A stable clock (see FIG. 2 (g)) can be output as an output of the tank circuit 2.

[0014]

As described above, according to the present invention, the switching control signal inputted asynchronously is converted into a switching signal synchronized with the input clock, and the fluctuation of the tank circuit at the time of switching of the system is eliminated, so that the switching at the time of switching is achieved. This has the effect that fluctuations in the output clock of the switching circuit can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLO duplex switching circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional PLO duplex switching circuit.

FIG. 3 is a time chart showing a waveform example of each unit for explaining the operation of FIGS. 1 and 2;

[Explanation of symbols]

 Reference Signs List 1 selection circuit 2 tank circuit 3 PLO working clock (N system) 4 PLO spare clock (E system) 5, 6 NOR circuit 7 selection circuit 8 flip-flop circuit 9 switching control signal input terminal 10 clock output terminal

Continuation of the front page (56) References JP-A-60-137147 (JP, A) JP-A-3-66240 (JP, A) JP-A-4-284038 (JP, A)

Claims (1)

(57) [Claims] 1. A dual PLO working clock (N
System) and a PLO backup clock (E system), a first selection circuit for switching to one of them by a switching control signal, and correcting the phase fluctuation and clock disconnection of the clock selected by the first selection circuit. In a PLO duplex switching circuit comprising a tank circuit, two NOR circuits in which different PLO clocks are input to one of input terminals in order to capture a phase of a switching timing from the clock output from the tank circuit and the PLO clock; A second selection circuit for selecting output clocks of the two NOR circuits, and a circuit for retiming an asynchronous switching control signal by the clock selected by the second selection circuit, A PL characterized in that a duplicated PLO clock is switched by a control signal. Redundant switching circuit.