JP2595606B2 - Data transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a data transmission device, and is particularly suitable for use in a data transmission device having a memory for writing data to be transmitted.

[Summary of the Invention]

A series of data is periodically read from a data memory in the transmission device and transmitted, and a data source transmits a code signal for switching the memory from a read state to a write state on the basis of data received from the data memory on a time basis. This is a data transmission device that writes desired data at a desired position.

[Conventional technology]

2. Description of the Related Art A recognition system using microwaves is used to streamline distribution management and manufacturing management of articles. In such a recognition system, the transmitting device is formed in the shape of a tag (tag) or a card and attached to an article. The transmission device is provided with a data generation circuit, which transmits the data generated here as an identification code, and recognizes the article by receiving the identification code by an identification device called a communicator.

The data generation circuit is generally formed of a one-chip IC, and a memory circuit for generating a unique identification code is integrally incorporated. The data written in the memory circuit varies depending on the purpose of using the transmitting device.
If the data is fixed, it can be written in advance when manufacturing the integrated circuit.

However, in a physical distribution management system such as a home delivery service or an airmail service, the data generated by the data generation circuit differs each time the transmission device is used. Therefore, in this case, it is necessary to allow a user using the transmission device to freely write arbitrary data in the memory circuit using the data writer.

[Problems to be solved by the invention]

When transmitting and receiving data between a tag-like or card-like transmitting device and a communicator, generally, following a write or read command for a memory, address information of a write or read position, data byte number information,
The communicator sends status information and the like, and in response to this, the transmitting device reads out the data at the corresponding address or needs a communication protocol that writes the received data to the corresponding address. For this reason, it is necessary to incorporate hardware and software for processing the communication protocol into the transmission device (tag or card), which has been a complicated and costly factor.

SUMMARY OF THE INVENTION In view of this problem, an object of the present invention is to make it possible to read and write a memory in a tag or card-like transmission device with a simple procedure and hardware without using a complicated communication protocol.

[Means for solving the problem]

As shown in FIG. 1, a data transmitting apparatus according to the present invention includes a memory 7 in which transmission data is written, an antenna 4 for transmitting a read output from the memory 7, and an antenna 4 for periodically reading the contents of the memory 7 and A detection circuit 10 for detecting a predetermined code signal SW supplied from a data supply source (writer 22) at a predetermined point in the reading cycle; A switching circuit (flip-flop 12) for switching the memory 7 from a read state to a write state in response to the detection output of the code signal, wherein data supplied following the code signal is written into the memory 7 as the transmission data; It is.

As shown in FIG. 5, the data transmitting apparatus according to the second aspect of the present invention includes a memory 7 to which transmission data is written, an antenna 4 for transmitting a read output from the memory 7, A periodic address means (address counter 6) for readout and deriving from the antenna 4; an input terminal 26 connected to a supply source (write unit 27) of write data to the memory 7; A detection circuit 10 for detecting a predetermined code signal supplied from the input terminal 26 at a predetermined time;
And a switching circuit (flip-flop) for switching from a read state to a write state. Data supplied to the input terminal 26 following the code signal is written to the memory 7 as the transmission data.

[Action]

The memory 7 is always in a read state, and the contents of the memory are periodically transmitted from the antenna 4. Therefore, the data supply sources (writers 22 and 27) can know the write position (address) in the memory using a series of received data as a time axis, and at a predetermined point in the read cycle, the data supply sources (write units 22 and 27). The encoders 22 and 27) transmit the code signal SW. When the detection circuit 10 detects this code, the memory 7 is switched from a read state to a write state, and data supplied following the code signal is written into the memory 7 as transmission data.

Therefore, immediately before the data write area (for example, the user area) of the memory 7 is read at the time of transmission of the code signal, the desired data is correctly written in the desired data write area without using a complicated communication protocol. be able to.

〔Example〕

FIG. 1 is a block diagram of a data transmitting apparatus according to an embodiment of the present invention. This data transmission device is configured as an ID tag device used in a distribution management system. As shown in the plan view of FIG. 2, the data transmission device is disposed on a dipole antenna 4 on the surface of the tag body 1 and a data generation circuit. 2 and the battery 3 are embedded in the tag body 1.

The data generation circuit 2 is a one-chip IC provided with terminals such as a power terminal 2a, a ground terminal 2b, and a data input / output terminal 2c.
The positive and negative electrodes of the battery 3 are directly connected to the terminals 2a and 2b, respectively. One feed point 4a of the dipole antenna 4 is a data input / output terminal.
2c, and the other feeding point 4b is connected to the ground terminal 2b.

A data storage circuit 9 including a clock signal generator 5, an address counter 6, and a memory 7 is provided in the data generation circuit 2. The memory 7 always operates in a read mode. In this case, a series of data (composed of high-level and low-level digital signals) read from the memory 7 is supplied to the gate electrode of the FET transistor 14 via the gate circuit 13 as the identification code signal ID. Therefore, the FET transistor 14 is turned on / off in accordance with the data read from the memory 7.

Since the drain electrode of the FET transistor 14 is connected to the data input / output terminal 2c and the source electrode is grounded, the impedance between the data input / output terminal 2c and the ground terminal 2b is increased by turning on / off the transistor 14. Change. Therefore, the impedance between the feeding points 4a and 4b of the dipole antenna 4 changes. For example, when the transistor 14 is turned on, it becomes 50 [Ω], and when it is turned off, it becomes 100 [Ω].
[Ω].

As shown in the block diagram of the data transmission / reception system in FIG. 4, a transmission antenna 17 of a communicator (recognition device) 16 is provided.
When a microwave 18 of 2.45 GHz is transmitted from the antenna, a reception current I flows through the dipole antenna 4, so that a reception wave (a transmission wave from the communicator 16) is received from the dipole antenna 4.
18 is re-emitted. The dipole antenna 4 is formed so as to resonate with a radio wave of 2.45 GHz. When the impedance between the feeding points 4a and 4b is 50 [Ω], the antenna impedance matches the reception wave of 2.45 GHz. The phase characteristic and amplitude characteristic of the reflected wave 20 re-radiated from the dipole antenna 4 differ between when the dipole antenna 4 is matched and when it is not. Accordingly, the communicator 16 receives the reflected wave 20 by the receiving antenna 21 and detects a change in the phase or amplitude, whereby the transmission data written in the memory 7 can be detected.

The memory 7 has a storage capacity of, for example, several hundred bits, and the first several tens of bits are used as a read-only area (ROM) 7a, in which a bit clock as shown in a waveform diagram of a time chart A in FIG. Reproducible frame synchronization signal 8
Has been written. Therefore, a synchronization signal circuit is constituted by the area 7a.

User area 7b in areas other than read-only area 7a
(RAM) is provided so that arbitrary data can be freely written when the memory 7 is switched to the write mode.

When writing data to the user area 7b,
The ground terminal 23 and the input / output terminal 25 provided on the dipole antenna 4 are brought into contact with the respective elements on the ground side and the signal input side of the dipole antenna 4 to read the frame synchronization signal 8 derived from the dipole antenna 4. Thereby, the writer 22 reproduces the bit clock ck inside the data generating circuit 2 from the frame synchronization signal 8 and establishes a data writing bit clock synchronized with the bit clock ck.

As shown in the operating mode diagram of the time chart B of FIG. 3 After establishing the bit clock for writing, at time t ₁ immediately after the frame sync signal 8 is transmitted, the memory circuit operating in read mode R A predetermined code signal SW is output from the input / output terminal 2 as a signal for switching 7 to the write mode W. The code signal SW may be, for example, a bit clock having a predetermined wave number. The code signal SW input from the dipole antenna 4 to the data generation circuit 2 is supplied to one input terminal of the coincidence detection circuit 10 and the memory 7 through the buffer amplifier 11.

The coincidence detection circuit 10 is constituted by an exclusive OR circuit, and a bit clock signal ck is supplied from the clock signal generator 5 to the other input terminal. Therefore, when the same signal is supplied to the two input terminals, the coincidence detection signal is derived from the coincidence detection circuit 10 to the set terminal S of the flip-flop circuit 12. Thus the level is inverted control signal flip-flop circuit 12 is outputted from the set output terminal Q, a memory 7 at the time t ₂ of FIG. 3 is switched from the read mode R in write mode W. This control signal is supplied to the gate circuit 13 through the inverter 15, and when the memory 7 enters the write mode, the gate circuit 13 is turned off. Therefore, the FET 14 is turned off.

Since the data generation circuit 2 operates in the write mode W in this manner, following the code signal SW, any data such as the type of baggage, reception number,
When data such as the reception date and time and the preceding data are transmitted, these data are sequentially written into the user area 7b of the memory 7.

When the user area 7b ends, the address designation of the address counter 6 returns to the beginning. At this time, the memory circuit 7
Is switched from the control output terminal Q of the address counter to the reset terminal R of the flip-flop circuit 12 as a signal SR for switching to the read mode R. Therefore,
Since the flip-flop circuit 12 is reset and the level of the control signal output from the output terminal Q is inverted, the memory 7 switches to the read mode R at time t3 in FIG. ₃ and the gate circuit 13 turns on. .

When the memory 7 operates in the read mode R, the data written in the azer area 7b is read following the frame synchronization signal 8 written in the read-only area 7a. As described above, the read data is the identification code ID.
Is given to the gate electrode of the transistor 14 and transmitted from the dipole antenna 4.

FIG. 5 is a block diagram of a data transmitting apparatus showing another embodiment. In this example, an independent data input terminal 2d is provided in the data generation circuit 2, and an external input terminal 26 is provided at the end of the tag body 1 as shown in the plan view of the ID tag device in FIG. , 26 are connected. When writing data to this data transmitting device, the frame synchronization signal 8 transmitted from the dipole antenna 4 is received by the receiving antenna 24 provided in the writer 22 to reproduce a big clock. Establish a data write bit clock. Next, the write terminal 27a of the writer 27 is brought into contact with the external input terminal 26 of the ID tag device. When making contact, for example, an insertion port is provided in the writer 27, and an ID tag device is inserted into this insertion port to bring the terminals 2d and 26 into contact.

In this embodiment, a pattern generator 30 for generating a code signal of a predetermined bit pattern based on the output clock of the clock signal generator 5 is provided, and the code signal generated by the generator 30 is used as a reference signal. The signal is input to the other input terminal of the match detection circuit 10 as a signal. Therefore, when switching to the write mode, a code signal of the same pattern is input from the writer 27 as a signal SW for switching to the write mode.

In the case of this embodiment, since the input and output signal paths are separated, an external signal can be received while outputting the data written in the memory 7. Therefore, the gate circuit 13 shown in FIG.
May not be provided.

In addition, since a signal from the outside can be input while outputting data, a predetermined code signal SW is input during a period in which the frame synchronization signal 8 is being read, as shown in the operation mode diagram of the time chart B in FIG. be able to. Therefore,
Memory 7 is changed over to write mode W at time t ₁ the transmission of the frame sync signal 8 is completed.

Note that the same bit pattern as the frame synchronization signal 8 as the predetermined code signal can be used. The bit pattern comparison reference signal may be generated by the pattern generator 30 or may be the one written in the area 7a of the memory 7.

Further, a synchronization signal circuit configured to generate a bit pattern of the frame synchronization signal by the pattern generator 30 and to periodically derive the bit pattern from the antenna 4 may be provided. In this case, the frame synchronization signal 8 need not be written in the memory 7.

Also, by providing a detection circuit similar to the coincidence detection circuit 10 and leading its output to the reset terminal R of the flip-flop circuit 12, it is possible to externally input a signal SR for switching the memory circuit 7 to the read mode after writing is completed. it can.

〔The invention's effect〕

As described above, in the present invention, since the memory 7 is always in the read state and the contents of the memory are periodically transmitted from the antenna 4, the data supply source (the writers 22 and 27) transmits The write position (address) to the memory can be known as an axis, and the code signal SW is transmitted from the data supply source (writers 22 and 27) at a predetermined point in the read cycle to read the memory 7 from the read state. By switching to the write state, data supplied following the code signal is written to the memory 7 at this desired position. Therefore, desired data can be correctly written in a desired data write area without using a complicated communication protocol.

Further, in the second aspect of the present invention, since the input terminal 26 connected to the supply source of the write data to the memory 7 is provided, the reception and transmission timings do not overlap at the antenna, and the read / write of the memory is not performed. Switching of the write state and transmission of the write data can be reliably performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data transmission device showing one embodiment of the present invention, FIG. 2 is a plan view of an ID tag device, FIG. 3 is a time chart showing an area of a memory circuit, and FIG. 5, FIG. 5 is a block diagram showing a modification of the data transmission device, FIG. 6 is a plan view showing a modification of the ID tag device, and FIG. 7 is a time showing a modification of switching to the write mode. It is a chart. In the reference numerals used in the drawings, 2 ... a data generation circuit 4 ... a dipole antenna 7 ... a memory circuit 7a ... a read-only area 7b ... a user area 8 ... a frame synchronization signal 10 ... a coincidence detection circuit 12 ... Flip-flop circuit SW: Code signal.

Claims (2)

(57) [Claims] 1. A memory in which transmission data is written, an antenna for transmitting a read output from the memory, periodic address means for periodically reading the contents of the memory and deriving the content from the antenna; A detection circuit for detecting a predetermined code signal supplied from a data supply source at a predetermined point in time, and a switching circuit for switching the memory from a read state to a write state based on a detection output of the code signal. A data transmitting apparatus in which subsequently supplied data is written in the memory as the transmission data. 2. A memory in which transmission data is written, an antenna for transmitting a read output from the memory, periodic address means for periodically reading the contents of the memory and deriving the contents from the antenna, An input terminal connected to a supply source of write data; a detection circuit for detecting a predetermined code signal supplied from the input terminal at a predetermined time in the read cycle; and a memory for detecting and outputting the code signal A switching circuit for switching from a read state to a write state, wherein data supplied to the input terminal following the code signal is written to the memory as the transmission data.