JP2597582B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a solid-state imaging device having a structure in which a photoconductive film is stacked as a photoelectric conversion unit on a CCD imaging device chip.

(Prior Art) A conventional solid-state imaging device in which a conventional CCD image sensor is used as a signal charge readout unit, and a photoconductive film such as an amorphous silicon (a-Si) film is stacked thereon to form a photoelectric conversion unit, It has the feature of high sensitivity.

4 (a) and 4 (b) show a cross-sectional structure of a main part of such a stacked CCD image pickup device and a structure showing a part thereof in an equivalent circuit. Reference numeral 21 denotes a p-type Si substrate, and a plurality of n ⁺ -type layers 22 forming a storage diode are formed in a matrix on the surface thereof. A vertical CCD register having an n ⁺ -type buried channel 23 along which the transfer gate 25 is formed via a gate insulating film is formed along the storage diode array. 26
Is a p ⁺ type channel stopper. A field transfer gate 26 is formed on the transfer channel 27 between the n ⁺ -type layer 22 and the n ⁺ -type buried channel 23 of the stacked diode via a gate insulating film. The surface of this CCD image sensor chip is a CVD insulating film
28, and a contact hole is opened in the n ⁺ type layer 22.
Each pixel electrode 29 is formed so as to be in contact with. An a-Si film 30 is formed as a photoconductive film on the CCD image sensor chip, and a transparent electrode 31 is further formed thereon.

In such a stacked type CCD imaging device, the imaging operation is performed by applying a negative bias electrode V _G to the transparent electrode 31. As a result, the signal charges (electrons in the figure) generated by the photoelectric conversion in the a-Si film 30 drift downward and move to the pixel electrode.
Collected in 29 and stored in stacked diodes. The signal charge of the storage diode is read out to the vertical CCD register by applying a negative transfer pulse to the field transfer gate 26 during the invalid period of one scan field. Although not shown in FIG. 4, the signal charges read out to the vertical CCD register are read out by a horizontal CCD register provided at the output end of the vertical CCD register for each horizontal column during a valid period.

In this laminate-type CCD imaging device, when a high negative voltage V _G applied to the transparent electrode 31, the higher the film electron mobility of the a-Si film 30, the sensitivity improvement is achieved. Also, this negative voltage V _G is such that the hot electron effect occurs in the film.
Is sufficiently high, the sensitivity is further multiplied. Further, by applying such a high voltage, the probability that signal charges are captured by trap levels in the a-Si film 30 is reduced, and the effect of reducing photoconductive afterimage is also obtained.

However, when the sensitivity is multiplied by applying a high voltage to the transparent electrode 31 in this way, when an excessive signal charge is generated in the a-Si film 30, this leaks to the vertical CCD register,
Affects playback images. That is, since the imaging cell portion can be equivalently represented as shown in FIG.
Applying a negative high voltage V _G 31 perform imaging, strong light spot in a case where a large number of signal charges within a-SI30 is generated, increasing the potential of the n ⁺ -type layer 22 of the storage diode lower . As a result, even when the field transfer gate 26 has a zero bias, electrons in the n ⁺ -type layer 22 leak into the n ⁺ -type buried channel layer 23 of the vertical CCD register over the barrier of the transfer channel 27. Since the signal charges of the previous field are accumulated in the vertical CCD register during the valid period, the signal charges are mixed due to such leakage of the excessive signal charges. When excessive signal charge leakage is large, it spreads in the vertical CCD register and appears as a vertical bright line on the reproduced image.

(Problems to be Solved by the Invention) As described above, when a high voltage is applied to the transparent electrode and imaging is performed in the stacked CCD imaging device, when an excessive signal charge is generated in the photoconductive film, this is reproduced. There is a problem that a bright line is generated on an image.

An object of the present invention is to provide a stacked type CCD imaging device which solves such a problem.

[Structure of the Invention] (Means for Solving the Problems) In the stacked type imaging apparatus according to the present invention, the horizontal CCD of the conventional vertical CCD register (first vertical CCD register) is used.
A second vertical CCD register for temporarily storing the signal charges is provided on the register side, and a drain region for discharging excess signal charges is provided. During the effective period of the imaging operation, a voltage of the first polarity that accelerates the transport of the signal charge generated on the transparent electrode on the photoconductive film to the storage diode is applied, and during the invalid period, a voltage of the opposite second polarity is applied. Applied. Then, at the beginning of the invalid period, an operation of sweeping the excess signal charge of the first vertical CCD register to the drain region is performed,
The signal charge of the storage diode is then transferred to a first vertical CCD register, and the signal charge is subsequently transferred to a second vertical CCD register.
Transferred to register. Therefore, during the valid period, the imaging operation is performed in a state where there is no signal charge in the first vertical CCD register, and the signal charge in the second vertical CCD register is read out by the horizontal CCD register for each horizontal column.

(Operation) According to the present invention, an excess signal of the first vertical CCD register is swept out at the beginning of the invalid period, and then the signal charge of the storage diode is transferred to the first vertical CCD register. In addition, at this time, a bias voltage is applied to the transparent electrode on the photoconductive film so that even if the excess signal charge is generated in the photoconductive film, it is not transported to the storage diode. Further, during the valid period, when the excess signal charge is generated, this is the first signal charge.
, The signal charges of the previous field have already been transferred to the second vertical CCD register. Therefore, according to the present invention, even when a high voltage is applied to the photoconductive film to increase the sensitivity, mixing of signal charges due to excessive signal charges generated in the photoconductive film is reliably prevented, and the reproduced image is reproduced. The generation of the bright line on the top is prevented.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 is a schematic plan view showing a CCD image pickup device according to one embodiment. In FIG. 1, reference numeral 11 denotes a photosensitive region, which has a matrix arrangement of stacked diodes 12 and first vertical CCD registers 12 arranged along each column thereof. Storage diode 1
There is a field transfer gate 14 between 2 and the first vertical CCD register 13. Although not shown in the drawing, a photoconductive film is formed on the photosensitive region 11 by lamination. This laminated photosensitive area
The sectional structure of 11 is basically the same as that of FIG. 4 (a) described above. A temporary storage area 15 is provided in contact with one end of the photosensitive area 11. The temporary storage area 15
It is constituted by a second vertical CCD register 16 in which a channel connected to the channel of the first vertical CCD register 13 is formed. Clock terminal φ of the second vertical CCD register 16
_S1 is to [phi] _S4, the further drive voltage is adapted to be applied to the clock terminal phi _I1 to [phi] _I4 of the first vertical CCD registers 13. A transfer gate 17 is provided between the first and second vertical CCD registers 13 and 16. At the other end of the photosensitive region 11, a drain region 18 forming a pn junction for discharging excess signal charges of the first vertical CCD register 13 is provided. A predetermined reverse bias is applied to the drain region 18. A horizontal CCD for reading the signal charges of the second vertical CCD register 16 for each horizontal column is provided below the temporary storage area 15.
A register 19 is provided, and pixel signals are sequentially read out to the output unit 20 by the horizontal CCD register 19.

The operation of the CCD imaging device having the above configuration will be described below.

Figure 2 shows the voltage V _G to be applied to the transparent electrodes of the photoconductive film, the drive voltage applied to clock terminal phi _I1 of the photosensitive region 11, and the time variation of the clock voltages phi _FS applied to the field transfer gate 14 . This embodiment uses n channels. The operation of reading the signal charge is constituted by repetition of a vertical invalid period and a vertical valid period. Voltage V _G applied to the transparent electrodes on the photoconductive film, the disable period is a positive voltage V _GH, the effective period is set to a negative voltage V _GH. In contrast,
The clock φ _I1 is maintained at the “H” level voltage (negative near zero) V _IH during the valid period. During such an effective period, for example, when an intense light spot hits and excess signal charges are generated in the photoconductive film, the excess signal charges pass under the field transfer gate and pass through the photosensitive region 11 in the same manner as described in the conventional example. It flows into the first vertical CCD register 13. At this time, although omitted in the figure, an “L” level voltage is applied to the transfer gate 17 between the first vertical CCD register 13 and the second vertical CCD register 16 so that the first vertical CCD register 13 Excess signal charge is prevented from flowing into the second vertical CCD register 16. In the invalid period, a transfer pulse is applied to the clock terminals φ _{I1 to} φ _I4 of the first vertical CCD register 13 during the initial first period T ₁ , and the excess signal charge of the first vertical CCD register 13 is Is performed to drain region 18. Then the second period T _2, and transfers the signal charge of each storage diode 12 to the first vertical CCD register 13 by the clock phi _FS. Followed by third period T _3, the first vertical CCD
The signal charge transferred to the register 13 is transferred to the clock terminal φ _I1
By applying a transfer clock to to [phi] _I4 and φ _S1 ~φ _S4, it is transferred to the second vertical CCD registers 16 in the temporary storage area. During this invalid period, the positive voltage _VGH is applied to the transparent electrode, so that no excess signal charge flows into the first vertical CCD register 13. The signal charges thus transferred to the temporary storage area 15 are read out by the horizontal CCD register 19 via the output unit 20 for each horizontal column in the next valid period. Then, during the valid period, the excess signal charge is generated as described above, and this is the first vertical charge.
Even if the signal charge flows into the CCD register 13, the signal charge imaged during the valid period of the previous field at this time is the second vertical CC
Since the signal charges are transferred to the D register 16, mixing of signal charges does not occur.

Figure 3 (a) ~ (d) show the state of the potential distribution of the movement of the cells of the signal charges of the major time t ₁ ~t ₃ in the timing diagram of Figure 2. In the cell structure diagram of FIG. 3A, the same reference numerals as those in FIG. 4 are used. At time t ₁ of the validity period, already when the potential of the n ⁺ -type layer 22 of the excessive signal charge as described occurs to the storage diode is greatly lowered, the third field transfer gate as shown in Figure (b)
26 through the channel below 26 into the n ⁺ buried channel 23 of the first vertical CCD register. At time t ₂ shown in FIG. 3C, the excess signal charges of the first vertical CCD register 13 are removed to the drain region 18. At this time, even if excessive signal charges are generated in the photoconductive film, a positive voltage V is applied to the transparent electrode.
_{Since GH} is applied and the excess signal charge is removed to the transparent electrode side, it does not flow into the first vertical CCD register 13. Time t ₃ of FIG. 3 (d) is a signal charge of the n ⁺ -type layer 22 of the storage diode, by applying a negative pulse voltage to the field transfer gate 26, the first vertical CCD registers 13
In the n ⁺ -type layer 23 of FIG.

As described above, according to this embodiment, a high voltage is applied to the transparent electrode of the stacked CCD image pickup device for high sensitivity and low image lag. As a result, excess signal charge flowing into the first vertical CCD register is obtained. Are drained to the drain region at the beginning of the invalid period. Therefore, the occurrence of a bright line on a reproduced image, which has conventionally been a problem, is reliably prevented.

The present invention is not limited to the above embodiment. For example, in the embodiment, the photoconductive film is a single layer, but may be a multi-layer photoconductive film. In addition, a structure in which another material film is interposed between the photoconductive film and the transparent electrode or the pixel electrode below the photoconductive film may be used. In short, the signal charges generated in the photoconductive film are read by the lower readout unit. Any format may be used as long as it can be read. The transfer gate provided between the first vertical CCD register and the second vertical CCD register is not limited to one gate electrode.
A multi-electrode configuration may be used. In the embodiment, the channel of the first vertical CCD register and the channel of the second vertical CCD register correspond to 1: 1. However, for example, the second vertical CCD register corresponds to one channel of the first vertical CCD register. A configuration in which these two channels correspond to each other.

In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a CCD image pickup apparatus according to one embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation thereof, and FIGS. FIGS. 4 (a) and 4 (b) are views showing the flow of signal charges, and FIGS. 4 (a) and 4 (b) are views showing the cross-sectional structure of the main part of the stacked CCD image pickup device. 11: photosensitive area, 12: storage diode, 13: first vertical CCD register, 14: transfer gate, 15: temporary storage area, 16: second vertical CCD register, 17: transfer gate , 18 …… Drain area, 19 …… Horizontal CCD register, 20
…… Output part, 21 …… p-type Si substrate, 22 …… n ⁺ -type layer (storage diode), 23 …… n ⁺ -type layer (buried channel), 24 ……
p ⁺ channel stopper, 25 transfer gate, 26 transfer gate, 27 transfer channel, 28 insulating film, 29 pixel electrode, 30 a-Si film (photoconductive film), 31 …… Transparent electrode.

Claims (2)

(57) [Claims] A solid-state imaging device chip in which a plurality of signal charge storage diodes and a signal charge readout unit for reading out the signal charges are arranged and formed on a semiconductor substrate, and a pixel electrode connected to each of the diodes is formed on the surface; In a solid-state imaging device having a photoconductive film serving as a photoelectric conversion unit stacked on the chip and a transparent electrode formed on the photoconductive film, the signal charge readout unit is provided in each column of the storage diodes. A plurality of first vertical CCD registers formed along the second vertical CCD register; and a second vertical CCD register provided adjacent to one end of the first vertical CCD register for temporarily storing signal charges of the first vertical CCD register. And a horizontal CCD for reading out signal charges of the second vertical CCD register for each horizontal column.
A CD register; and a drain region provided adjacent to a transfer end of the first vertical CCD register for discharging excess signal charges of the first vertical CCD register.
A voltage of a first polarity is applied to the transparent electrode to accelerate transfer of signal charges generated by the photoconductive film to the storage diode during an effective period of a scan field, and the storage diode is applied to the transparent electrode during an invalid period. Is the reverse bias
Polarity voltage and initially a first vertical CCD from the storage diode during the validity period of the previous field.
An operation of sweeping the excess signal charge leaked into the register into the drain region is performed, and then the signal charge of the storage diode is read into the first vertical CCD register, and the read signal of the first vertical CCD register is read out. The solid-state imaging device is characterized in that, after transferring the electric charge to the second vertical CCD register, the signal electric charge of the second vertical CCD register is read out for each horizontal column by the horizontal CCD register during the valid period. apparatus. 2. A channel of the first vertical CCD register and a channel of the second vertical CCD register are connected via a transfer gate which is opened only when signal charges are transferred between the two channels. 2. The solid-state imaging device according to claim 1.