JP2597760B2 - Path activation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path activating method for determining a path activating condition when a delay test pattern is created. In recent years, with the increase in the scale and speed of computers, it has been required to perform not only a circuit test but also a function test as well as a delay test. In general, the creation of a delay test pattern has stricter activation conditions than the function test, and it takes much time to create the pattern. Therefore, it is necessary to select a path that is strict in terms of delay first, and to narrow down the number of paths to be tested in the delay test to generate a test pattern. However, if the path is determined beforehand, pattern generation becomes increasingly difficult and time-consuming, so it is necessary to increase the speed.

[0002]

2. Description of the Related Art FIG. 10 shows an example of a test path. FIG.
, 1 is a source latch, 2 is a target latch, and a plurality of gates (OR gates) from the source latch 1
The signal change is sent to the target latch 2 via 3 and 4,
Perform a delay test.

A gate (NOR gate) 5 is connected to the input side of the gate 4, and gates (AND gates) 6, 7 are connected to the input side of the gate 5. One input condition of the gate 7 is the input condition 1. A gate (OR gate) 8 is connected to the input side of the gate 3. Both input conditions of the gate 8 are the input condition 2, and the output side of the gate 8 is connected to one input side of the gate 7.

Here, it is immediately understood that the input of the gates 3 and 4 on the non-pass side on the path does not propagate on the path unless 0 is required. Therefore, input conditions (activation conditions) that simultaneously satisfy these requirements must be obtained. To determine the activation conditions, the ATG (Au
tomatic Test-pattern Generator). AT
In G, first, one required condition is extracted, and an input condition that satisfies the required condition and does not contradict other required conditions is obtained.

Here, whether or not a contradiction occurs is determined by performing a simulation every time the value of the external input is determined by the ATG and comparing it with a required value. In the same manner, the activation condition is repeatedly obtained until all the required conditions are satisfied. If an inconsistency occurs in the middle, the operation of changing the combination of the input conditions obtained so far and obtaining an input condition that does not cause an inconsistency is repeated.
In this way, a delay test pattern is created by the ATG.

Here, it is assumed that the ATG first seeks a condition that satisfies the 0 requirement for the input of the gate 4.
Since the gate 5 is a NOR gate, it is understood that one of the inputs only needs to be 1. Here, it is assumed that the ATG has decided to set the lower input of the gate 5 to 1. Since the gate 7 is an AND gate, both inputs must be set to 1.
The input condition 1 is determined so that the lower input of the gate 7 is set to 1, and the input condition 2 of the gate 8 is set so that the upper input of the gate 7 is set to 1. Then, since the output of the gate 8 becomes 1 at this point, the first input request, that is, the gate 3
Conflicts with the requirement that the lower input be zero.

After all, the ATG repeats backtracking, gives up on setting the lower side of the gate 5 to 1, and continues processing in the direction of creating a pattern in which the upper input is set to 1. Therefore, the time required for obtaining the input conditions 1 and 2 and the processing time required for the backtrack are all wasted.

[0008]

In such a conventional path activating method, the input of the gate 3 must be absolutely zero for a delay test. Therefore,
The output of gate 8 must ultimately be zero. Therefore, the output of the gate 7 finally becomes 0. However, when the test pattern is obtained, the output of the gate 8 is X until the input condition 2 is determined.
There is a problem that it is not understood that the input on the lower side cannot be set to 1 and the useless processing of obtaining the input conditions 1 and 2 is performed.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and reduces unnecessary processing and reduces ATG.
It is an object of the present invention to provide a path activating method for speeding up the operation.

[0010]

According to the present invention, as shown in FIG. 1, when a signal change is sent from a source latch 11 to a target latch 12 through a plurality of gates 13 and 14 for testing, a path activation is performed. In the path activation method for determining the conditions for the operation, the constant gate 19, which always disconnects the output side of the driver 18, 15 connected to the input side of the gate 13, 14 and always outputs the required value,
20 are connected.

[0011]

In the present invention, the output sides of the drivers 18, 15 connected to the input sides of the gates 13, 14 are disconnected,
Instead, the constant gates 19 and 20 which always output the requested value are connected, so that the gates 15 and
Before the output value of 18 becomes the required value, the value of the net becomes the required value. Therefore, the net that finally becomes 1 is set to 0
And the net that becomes absolute 0 is not made to be 1, and wasteful processing can be reduced.

As a result, the search range of the ATG can be narrowed, and the speed of the ATG can be increased.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 7 are views showing an embodiment of the present invention.
FIG. 2 shows a logic circuit to be subjected to a delay test. In FIG. 2, reference numeral 11 denotes a source latch and 12 denotes a target latch.
A plurality of OR gates 13 and 14 are connected between them.

The NOR gate 15 is connected to one input side of the OR gate 14, and AND gates 16 and 17 are connected to the input side of the NOR gate 15, respectively. on the other hand,
An OR gate 18 is connected to one input side of the OR gate 13, and an input condition of the OR gate 18 is an input condition 2. The output of the OR gate 18 is one input of the AND gate 17, and the other input condition of the AND gate 17 is the input condition 1.

Next, the operation will be described. FIG. 4 is a flowchart for explaining the operation. In FIG. 4, first, at step S1, a required point and a required value for which an input value is required are determined before ATG is started. In this example, one input side of the OR gate 13 and one input side of the OR gate 14 are required points, and both required values are 0.

Next, in step S2, a driver for outputting to a required point is determined. In this example, the OR gate 13
An OR gate 18 connected to one input side of the OR gate and a NOR gate 15 connected to one input side of the OR gate 14. Next, in step S3, the net having the required point is cut at the output of the driver. Therefore, the output of the OR gate 18 is not input to the OR gate 13, and the output of the NOR gate 15 is not input to the OR gate 14.

Next, in step S4, constant gates 19 and 20, which always output a requested value, are connected to the OR gates 13 and 14 instead of disconnecting the net at the request point (see FIG. 3). Therefore, as shown in FIG. 3, one input of the AND gate 17 is 0, and its output is 0 regardless of the input condition 1. NOR gate 1
Since one input of 5 is 0, the output of the AND gate 16 becomes 1 and both inputs of the AND gate 16 become 1 in order for the output to be 0.

On the other hand, since the output of the NOR gate 18 is required to be 0, the input conditions thereof are both 0. FIG. 5 shows the input / output relationship of the OR gates 13 and 18 and the AND gate 17, and FIG. 6 shows the input / output relationship when the output of the OR gate 18 is disconnected and the constant gate 19 is connected.
Shown in

Then, the output of the OR gate 18 is disconnected,
FIG. 7 shows the network table 21 when the constant gate 19 is connected. This network table is a representation of circuit connections on a database.
Arrows indicate that the input / output pins linked cyclically are connected by one net.

As described above, when the ATG attempts to set the output of the NOR gate 15 to 0, it does not attempt to set the lower input to 1, thereby reducing unnecessary processing. As a result, the search range of the ATG can be narrowed,
The speed of the ATG can be increased. Next, FIG. 8 is a diagram showing another embodiment of the present invention.

In FIG. 8, instead of connecting the OR gate 18 and the NOR gate 15 connected to the OR gates 13 and 14 to the constant gates 19 and 20, the required values are directly connected to the OR gates 13 and 14 and the AND gate 17 connected to the net. To simulate and flag the outputs of the OR gate 18 and the NOR gate 15. When simulating with ATG, look at the flag and, if the flag is set, set the event ahead. Don't tell.

FIG. 9 shows the network table 21 in this case. The output 01 of the OR gate 18 is not transmitted to the OR gate 3 and the AND gate 17 because a flag is set. Since the input of the OR gate 13 is 0 and the input of the AND gate 17 is 0, the same effect as in the above embodiment can be obtained.

[0023]

As described above, according to the present invention, it is possible to narrow the ATG search range by simulating the part where the value to be finally determined is determined first and sending the value first. As a result, the speed of the ATG can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram of a logic circuit to be tested

FIG. 3 is a diagram showing one embodiment of the present invention.

FIG. 4 is a flowchart for explaining an operation;

FIG. 5 is a connection diagram showing an input / output relationship;

FIG. 6 is a connection diagram showing an input / output relationship in place of a constant gate.

FIG. 7 shows a network table.

FIG. 8 is a diagram showing another embodiment of the present invention.

FIG. 9 shows a network table.

FIG. 10 is an explanatory view of a conventional example.

[Explanation of symbols]

 11: Source latch 12: Target latch 13, 14, 18: OR gate (gate) 15: NOR gate (gate) 16, 17: AND gate 19, 20: Constant gate 21: Network table

Claims (2)

(57) [Claims] 1. A path activation circuit for determining a condition for path activation when a signal change is sent from a source latch (11) to a target latch (12) via a plurality of gates (13) and (14) for testing. In the method, the gate (1
3), the driver (1) connected to the input side of (14)
8), constant gates (19), (2) which always disconnect the output side of (15) and always output the requested value.
(0) is connected. 2. A path activation circuit for determining a condition for path activation when a signal change is sent from a source latch (11) to a target latch (12) via a plurality of gates (13) and (14) for testing. In the method, the gate (1
3), simulation is performed by inputting required values to the input side of (14), and a flag is set to the output side of the driver (18), (15) so that an event is not transmitted. Path activation method.