JP2597767B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a memory cell of a DRAM (Dynamic Random Access Memory).

[0002]

2. Description of the Related Art FIG . 10 is an equivalent circuit showing a memory cell of a conventional DRAM having a stacked capacitor structure. This memory cell includes a selection transistor Q1 and a capacitor Cs for storing data. The gate of the selection transistor Q1 is connected to a word line WL,
One end of the current path of the selection transistor Q1 is connected to the bit line BL.
, And the other end is connected to the capacitor Cs.

FIGS. 11 and 12 show the structure of the above-mentioned memory cell, and the same parts as those in FIG. 10 are denoted by the same reference numerals.

In FIGS. 11 and 12 , a capacitor Cs
Are provided above the diffusion layer n ⁺ of the select transistor Q1. That is, the polysilicon layer 31 is in valid contact with the diffusion layer n ⁺ of the selection transistor Q1, and the polysilicon layer 32 as a plate electrode provided above the polysilicon layer 31 with an insulating film interposed therebetween is biased to a constant potential. Is done. The pair of polysilicon layers 31 and 32 are formed to extend above a word line WL as a gate of the selection transistor Q1 in order to increase the storage capacitance.

[0005]

[SUMMARY OF THE INVENTION Incidentally, in the DRAM, with miniaturization of memory cells, the number of memory cells connected to the bit line is increased, there is a tendency that the capacity of the bit line is increased. Further, with the miniaturization of the processing technology, the occupied area of the unit cell has been reduced. For this reason,
In order to secure the storage capacity CS, a technique such as further thinning the insulating film of the capacitor is required. But,
There is a limit in reducing the thickness of the insulating film for reasons such as securing the reliability of the capacitor. For this reason, it is becoming difficult to secure the ratio of the capacity CB of the bit line to the storage capacity Cs of the cell, so-called CB / Cs ratio.

[0006] Further, it is considered that the power supply voltage will be 5 V or less in the LSI of the ultra-miniaturized process generation in the future. When the power supply voltage of the DRAM is lowered, the amount of charge stored in the capacitor decreases, so that the amount of charge transferred to the bit line at the time of reading data also decreases. Therefore, it is expected that it will be difficult to reliably amplify data by the sense amplifier.

Here, the relationship between the bit line capacitance CB and the cell storage capacitance Cs will be further described.

FIG . 13 shows a conventional DRA including peripheral circuits.
FIG. 14 illustrates the operation of FIG. The bit line potential VBL is the initial setting level of the bit line before reading.

First, the read operation will be described.

(1) Before the start of the active cycle, the bit lines BL0 to BL3 are precharged to the VBL level because the equalizing signal EQL is at the high level.

(2) One word line WL0 is selected by a row decoder (not shown), and the word line WL0 is supplied with a voltage of Vcc (= 5V) or higher by a bootstrap circuit (not shown).
It is boosted to 5V.

(3) Dummy word lines DWL0 and / DWL0 (/ means an inverted signal) are selected corresponding to the selected word line, and the dummy word line DWL0 is changed from the VBL level to Vcc bell, DWL0 goes from VBL level to V
ss level.

(4) The data "1" stored in the selected cell connected to the bit line BL0 and the data "0" stored in the selected cell connected to the bit line BL2 are stored in the bit lines BL0 and BL2, respectively. Appears in In the memory cell, the storage level of "1" is V1 and the storage level of "0" is V00.
Then, the level v of the bit line after the data “1” is read
1 is: v1 = (V1 + CB / Cs.VBL) / (1 + CB / Cs) (1), and the level v0 of the bit line after reading data "0"
Is as follows: v0 = (V0 + CB / Cs.VBL) / (1 + CB / Cs) (2) V1 = 5V, V0 = 0V, VBL = 2.5V, CB
Assuming that / CS = 15, v1 = 2.665V v0 = 2.344V. Bit line BL1, bit line BL
3 is VBL = 2.5 V, the potential difference .DELTA.v amplified by the sense amplifier is equal to .DELTA.v1 = 0.156 V when reading data "1", .DELTA.v0 = 0.156 V when reading data "0". Becomes

(5) The sense amplifier is activated, the bit lines BL0 and BL3 are amplified to the Vcc level, and the bit line B
L1 and BL2 are amplified to the Vss level.

(6) A pair of bit lines BL0 and BL1, or BL2 and BL3 selected by a selection signal supplied from a column decoder (not shown) to a column selection line CSL.
Are transferred to output lines DQ and / DQ, respectively.

Next, the write operation will be described. In this write operation, the operations (1) to (3) described in the read operation are the same. Thereafter, in (4), the write level supplied to the output lines DQ and / DQ is
The data is transferred to the sense amplifier through the column switch transistor selected by the column selection line CSL. The level of the pair of bit lines becomes the Vcc and Vss levels by the sense amplifier, and this level is written to the selected memory cell.

Here, when the above equations (1) and (2) are respectively modified, v1 = VBL + (V1-VBL) / (1 + CB / Cs) (3) v0 = VBL + (V0-VBL) / (1 + CB) / Cs) (4)

As is apparent from the equations (3) and (4), when the capacity and the ultrafineness are advanced and the bit line capacity CB is increased and the capacity Cs of the capacitor is reduced, v1, v
0 both approach VBL.

Since the amplification reference voltage of the sense amplifier is VBL, the potential differences Δv1 and Δv0 amplified by the sense amplifier are
Are getting smaller together. Therefore, it is difficult to reliably amplify data by the sense amplifier.

An object of the present invention is to provide a semiconductor memory capable of ensuring a sufficient ratio between the bit line capacitance CB and the cell storage capacitance Cs even when the capacity, ultrafineness, and low voltage are advanced. It is to provide a device.

[0021]

In order to solve the above-mentioned problems, the present invention provides a selection transistor having a gate connected to a word line and one end of a current path connected to a bit line, and a current path for the selection transistor. A storage node connected to the other end, and a plate electrode insulated from the storage node, and an inversion layer is formed in a portion of the plate electrode corresponding to the storage node according to information stored in the storage node. And a pulse generating means connected to the plate electrode and supplying a pulse signal to the plate electrode, wherein the capacitor has a storage node acting as a gate electrode, and a capacitor corresponding to the storage node of the plate electrode. This portion has a thin film transistor structure acting as a channel region.

[0022]

Further, the portion of the plate electrode corresponding to the storage node has a lower impurity concentration than other portions.

The storage node and the plate electrode are made of polysilicon.

Further, the storage node and the plate electrode are made of amorphous silicon.

Further, the storage node and the plate electrode are made of single crystal silicon.

Further, the pulse generating means includes an oscillating circuit for generating a pulse signal, a boosting circuit for boosting the pulse signal generated by the oscillating circuit to a predetermined potential, and selecting a selection transistor when reading stored information. a predetermined potential output from the boost circuit previously supplied to the plate electrode, which have a supply circuit to stop the supply of the electric potential relative to the plate electrode prior to the selection of the selection transistor is canceled.

According to the present invention, the gate is connected to the word line.
Connected to the bit line at one end of the current path.
A transistor and the other end of the current path of this select transistor
Storage node connected to the
The storage node is a gate electrode
Acts as a pair with a storage node of the plate electrode.
The corresponding portion has a lower impurity concentration than the other
Of thin film transistor structure acting as
And the plate electrode is set to a high potential when reading information.
Potential supply means.

Further, according to the present invention , a predetermined
Configure source and drain regions provided at intervals
A diffusion layer, and insulating the semiconductor substrate from the semiconductor substrate;
Having a gate electrode as a word line provided by
An S-type selection transistor;
Forming the storage node on the first diffusion layer
A semiconductor layer and an insulating layer provided on the first semiconductor layer.
And the first semiconductor layer has an area larger than that of the first semiconductor layer.
The part corresponding to the body layer has a lower impurity concentration than the other parts.
Channel region, and the other part is a high impurity concentration
High level when reading stored information.
And a second semiconductor layer.

The first and second semiconductor layers are made of polysilicon.

Further, the second semiconductor layer is made of amorphous silicon.

The first and second semiconductor layers are made of single crystal silicon.

Further, according to the present invention, the gate is connected to the word line.
Connected, one end of the current path connected to the bit line
Other than the transistor and the current path of this select transistor.
Storage node connected to the end and isolated from this storage node
Having a gate electrode connected to the storage node.
A part corresponding to the storage node of the plate electrode
Is formed according to the information stored in the storage node.
The key of the thin film transistor structure as the channel region to be formed
Reading information stored in the capacitor and the storage node
Pulse generating means for generating a pulse signal for
Selection signal generation means for generating a selection signal for selecting a logic line
In response to a selection signal output from the selection signal generation means.
The pulse signal output from the pulse generation means is
Supply means for supplying to the plate electrode.

The supply means is constituted by an AND circuit.

[0035]

According to the present invention , a key of a thin film transistor structure is provided.
Data “0” is stored in the storage node of the capacitor
In the case where the channel region formed on the plate electrode is
Is not formed, the resistance of the channel region is high.
Has become. Also, data “1” is stored in the storage node.
Inversion layer is formed in the channel region if
Therefore, the resistance value of the channel region is low. In this state, when the potential of the plate electrode is boosted by a pulse signal output from the pulse generating means at the time of data reading, data "0" is stored as the potential of the channel region of the cell storing data "1". High level in a short time as compared with the channel region of the cell in question. Therefore, the potential of the storage node capacitively coupled to the channel region also becomes high. When the selection transistor of the cell data "1" is stored is selected, it amplified transferred charge amount corresponding boosted as described above is transferred to the bit line. Therefore, the charge transferred to the bit line increases, and the potential change of the bit line also increases. Therefore, amplification by the sense amplifier becomes easy.

[0036]

An embodiment of the present invention will be described below with reference to the drawings. The same parts as those in FIG. 10 are denoted by the same reference numerals, and only different parts will be described.

FIG. 1 shows an equivalent circuit of the present invention, and shows one memory cell MC.

For example, an n-channel selection transistor Q1
Is connected to the word line WL, and the source of the select transistor Q1 is connected to the bit line BL. The drain of the selection transistor Q1 is connected to the plate electrode PL via a capacitor (hereinafter, referred to as a switched capacitor SC) whose state changes according to stored information. The switched capacitor SC has a storage node SN connected to the drain of the selection transistor Q1,
The storage node SN is provided with an insulating film (not shown) interposed therebetween, and is constituted by a channel region CH connected to the plate electrode PL. The storage node SN is formed of, for example, a polysilicon film, and the channel region CH is formed of, for example, a polysilicon film integrally with the plate electrode PL. The channel region CH has a lower impurity concentration than the plate electrode PL.

A pulse generating circuit 11 is connected to the plate electrode PL. The pulse generating circuit 11 outputs a pulse signal for boosting the plate electrode PL when reading data.

FIGS. 2 and 3 respectively show the memory cell MC.
FIG.

The switched capacitor SC is formed on a diffusion layer of the selection transistor Q1. That is, p
In the semiconductor substrate 12, a diffusion layer n + forming the source S and drain D of the n-channel transistor Q1 is provided. An oxide film 15 is provided on the semiconductor substrate 12, and a gate as a word line WL is provided on the oxide film 15. Polysilicon film 13 forming storage node SN is provided on drain D of transistor Q1. An insulating film 16 is provided on the polysilicon film 13, and, for example, a polysilicon thin film 14 is provided on the insulating film 16. The area of the polysilicon thin film 14 is larger than the polysilicon film 13. The portion of the polysilicon thin film 14 corresponding to the polysilicon film 12 (overlap) has a low impurity concentration (n @-) to form a channel region CH, and the other portion has a low resistance high impurity region. It constitutes the plate electrode PL. An insulating film 17 is provided on the polysilicon thin film 14, and on the insulating film 17,
A bit line BL is provided. This bit line BL is connected to the source S.

When the switched capacitor SC has a storage node SN as a gate and a plate electrode PL as a drain, the switched capacitor SC does not have a source and therefore does not have a transistor structure. Transistor: TFT).

The operation principle of the above configuration will be described with reference to FIG. The switched capacitor CS is
When data "0" is stored in storage node SN, no inversion layer is formed in channel region CH, and when data "1" is stored, an inversion layer is formed in channel region CH. . Therefore, when data "1" is stored, the channel region CH has the same potential as the plate electrode PL.

When reading data stored in the memory cell, before the word line WL is selected, a plate pulse φp is output from the pulse generation circuit 11 and the potential of the plate electrode PL is changed from 0V to V2 higher than this. For example 1
/ 2Vcc. At this time, when data “0” is stored in storage node SN, no inversion layer is formed in channel region CH. Therefore, the channel region CH is in a high resistance state, and the channel region CH remains at 0 V even when the plate electrode PL is boosted. Therefore, storage node SN capacitively coupled to channel region CH
Also remains at 0V.

When data "1" is stored in storage node SN, since the inversion layer is formed in channel region CH, when the potential of plate electrode PL is boosted, the potential of channel region CH also rises. Potential. Therefore,
The potential of the storage node SN capacitively coupled to the channel region CH is also boosted to a high potential.

Next, when the word line WL is selected, the charge of the storage node SN is transferred to the bit line BL, and the stored data is read out to the bit line BL. The read potential of bit line BL is amplified by a sense amplifier (not shown), and data "1" is rewritten to storage node SN via the bit line.

Next, before the selection of the word line WL is completed, the potential of the plate electrode PL is returned to 0V. When data “1” is stored in the storage node SN, the channel region CH has low resistance because the inversion layer is formed in the channel region CH, and the potential of the channel region CH also returns to 0V. When data “0” is stored in the storage node SN, since the inversion layer is not formed, the channel region CH has a high resistance and the plate electrode PL
Even if a pulse of a positive potential is applied, the voltage remains at 0V.

When the plate electrode PL returns to 0 V, charge is replenished from the bit line to the capacitor of the memory cell storing the data "1", so that the "1" level of the memory cell is at the potential of the bit line. And is kept at the same potential. Here, when the amount of charge transferred to the bit line BL is obtained in the same manner as in the conventional example, the level v1 of the bit line after "1" is read
Is as follows: v1 = (V1 + V2 + CB / Cs.VBL) / (1 + CB / Cs) = (V1 + V2-VBL) / (1 + CB / CS) + VBL (5) The level v0 of the bit line after "0" is read is , V0 = (V0 + CB / Cs.VBL) / (1 + CB / Cs) = (V0-VBL) / (1 + CB / Cs) + VBL (6)

The equations (5) and (6) are replaced with the conventional equation (3)
Compared with the equation (4), the level of v1 is V2 / (1+
It can be seen that it is higher by CB / Cs). That is, the read amount of the bit line at the time of reading is increased by this amount, and the operation margin can be improved.

FIG. 5 shows an example of the pulse generation circuit 11, and FIGS. 6a and 6b show signals of various parts. When reading out the stored information, the pulse generation circuit 11 boosts the plate electrode before the selection of the selection transistor, and drops the plate electrode before the selection of the selection transistor is released.

That is, the pulse generation circuit 11 generates R
A timing pulse generating circuit 21 for generating a pulse signal φtp for a predetermined time in response to a fall of an AS (Row Address Strobe), and a power supply voltage in accordance with pulse signals φ1 and φ2 output from the oscillation circuit 22 and having a 90 ° phase difference. A boosting circuit 23 for boosting Vcc to a predetermined voltage Vp; an output circuit 24 for outputting the voltage Vp output from the boosting circuit 23 as a plate pulse φp in response to a pulse signal φtp output from the timing pulse generating circuit 21 And is constituted by.

The timing pulse generation circuit 21 is mainly composed of a delay circuit 21a, a NAND circuit 21b, etc., and generates a pulse signal φtp in response to a fall of RAS. That is, when RAS is at a high level, the output of the timing pulse generation circuit 21 is at a low level. When RAS goes low,
The timing pulse generation circuit 21 outputs a high-level timing pulse signal φtp. This pulse signal φt
p has a pulse width corresponding to the delay time set in the delay circuit 21a.

The oscillating circuit 22 generates pulse signals φ1 and φ2 having a phase difference of 90 °, and these pulse signals φ1 and φ2 are supplied to a capacitor constituting the booster circuit 23.

The booster circuit 23 includes a plurality of capacitors 23a
And a plurality of transistors 23b diode-connected and a limiter 23c, and a pulse signal φ1
, Φ2, the power supply voltage Vcc is boosted using a capacitor 23a and a plurality of transistors 23b,
A predetermined voltage Vp is generated by 3c.

The output circuit 24 changes the voltage Vp output from the booster circuit 23 to a plate pulse φ in response to the pulse signal φtp output from the timing pulse generation circuit 21.
Output as p. That is, when RAS is at high level, the pulse signal φtp is at low level, so that the output of the booster circuit 23 is not selected in the output circuit 24, and the plate pulse φp is at low level. Also, RAS
Goes low, the pulse signal φtp goes high, the output circuit 24 selects the output of the booster 23, and the potential Vp is output as a plate pulse φp. The pulse width of the plate pulse φp corresponds to the delay time set in the timing pulse generation circuit 21.

According to the above embodiment, the selection transistor Q
1 is connected to a switched capacitor SC having a TFT structure,
An inversion layer is formed in the channel region CH of the switched capacitor SC according to stored data. Further, at the time of reading data, the plate electrode PL of the switched capacitor SC is boosted. Therefore, storage node SN storing data "1" is boosted in accordance with the potential of plate electrode PL. When selection transistor Q1 is selected, transfer charge amplified by the boosted potential is transferred to bit line Since the data is transferred to the BL, the amplification by the sense amplifier becomes easy.

In addition, since the plate electrode PL is boosted at the time of reading data to amplify the charge transferred to the bit line BL, the storage capacity Cs of the cell can be substantially increased. Therefore, even when the capacity of the DRAM is increased and miniaturized, and when the power supply voltage is reduced to 5 V or less, the ratio CB / Cs of the bit line capacity CB and the storage capacity Cs of the cell is sufficiently ensured. Is what you can do.

Further, the pulse generating circuit 11 boosts the plate electrode only for a short time at the time of reading data, and does not constantly boost the voltage as in the prior art. Therefore, the deterioration of the gate oxide film can be prevented, and the reliability can be improved.

Next, a second embodiment of the present invention will be described.
This will be described with reference to FIGS. 2 and 3 are denoted by the same reference numerals, and only different portions will be described.

Although the memory cell in the above embodiment is of a type in which a bit line is provided at the uppermost part, this embodiment shows a memory cell of a bit line embedded type in which a bit line is embedded in another wiring. I have.

That is, as shown in FIGS. 7 and 8, a storage node SN constituted by a polysilicon film 13 is provided on one diffusion layer of the select transistor Q1, and a bit line BL is provided on the other diffusion layer. Is provided. An insulating film 17 is provided on the storage node SN and the gate, and a plate electrode PL made of the polysilicon film 14 is provided on the insulating film 17 and the bit line BL. Of the plate electrodes PL, the storage node S
The portion corresponding to N has a low impurity concentration (n-), and a channel region CH is formed.

With such a configuration, the same effect as in the above embodiment can be obtained.

In each of the above embodiments, the switched capacitor SC is formed by the thin film technique. However, the switched capacitor SC may be formed by an epitaxial growth method.

Although the switched capacitor SC is formed of polysilicon, it is also possible to use amorphous silicon.

Further, although the switched capacitor SC is formed of a thin film, it is not necessary to use a thin film if single crystal silicon is used.

In the above embodiment, the switched capacitor SC is formed by the stack structure. However, the present invention is not limited to this, and the switched capacitor SC may be formed by a trench structure or a combination thereof.

Further, even when the switched capacitor SC is constituted by a normal MOS capacitor,
It is possible to secure a sufficient ratio between the bit line capacitance CB and the cell storage capacitance Cs.

FIG. 9 shows a third embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

The memory cells MC are arranged in a matrix. One ends of the bit lines BL1 to BLn are connected to a column decoder 92 via a sense amplifier 91. One end of each of the word lines WL1 to WLn is connected to a row decoder 93.
It is connected to the. Memory cell MC is selected by column decoder 92 and row decoder 93, and data read from memory cell MC is supplied to sense amplifier 92.
Supplied to

The other ends of the word lines WL1 to WLn are connected to one input terminals of AND circuits A1 to An. One input terminals of these AND circuits A1 to An are connected to the pulse generator 11. The output terminals of these AND circuits A1 to An are connected to the plate electrodes PL1 to PLn, respectively.

In the above configuration, AND circuits A1 to An
Supplies a pulse signal output from the pulse generator 11 to the plate electrode only when selected by the word line. Therefore, since the pulse generator 11 only needs to drive the memory cells in the row direction selected by the word line, the driving capability of the pulse generator 11 can be reduced.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

[0073]

As described above, according to the present invention, the ratio of the bit line capacitance CB to the cell storage capacitance Cs can be increased even when the capacity, the ultra-fine structure, and the voltage are reduced. A semiconductor memory device that can be sufficiently secured can be provided.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing one embodiment of the present invention.

FIG. 2 is a plan view showing the cell structure of FIG. 1;

FIG. 3 is a sectional view taken along line 3-3 in FIG. 2;

FIG. 4 is a view for explaining the operation of FIGS. 1 to 3;

FIG. 5 is a circuit diagram showing an example of a pulse generation circuit shown in FIG. 1;

FIG. 6 is a waveform chart shown for explaining the operation of FIG. 5;

FIG. 7, showing a second embodiment of the present invention, is a plan view showing a cell structure.

FIG. 8 is a sectional view taken along the line 8-8 in FIG. 7;

FIG. 9 is a circuit diagram showing a third embodiment of the present invention.

FIG. 10 is an equivalent circuit showing a memory cell of a conventional DRAM.

FIG. 11 is a plan view showing a configuration of the memory cell shown in FIG. 10;

FIG. 12 is a sectional view taken along the line 12-12 in FIG. 11;

FIG. 13 is a circuit diagram showing a DRAM including a conventional peripheral circuit.

14 is a waveform chart shown for explaining the operation of FIG.

[Explanation of symbols]

BL: bit line, WL: word line, Q1: selection transistor, SC: switching capacitor, SN: storage node
, CH ... channel region, PL ... plate electrode, 11 ...
Pulse generation circuit, 12, 13 ... polysilicon thin film, A1
~ An ... AND circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical display location H01L 29/786 G11C 11/34 352D

Claims (13)

(57) [Claims] A current path having a gate connected to a word line;
A select transistor having one end connected to the bit line and a switch connected to the other end of the current path of the select transistor.
Storage node and a plate electrode insulated from this storage node.
A pole corresponding to the storage node of the plate electrode.
Inverted layers are provided according to the information stored in the storage nodes.
Is connected to the plate electrode, and a pulse signal is applied to the plate electrode.
Pulse generating means for supplying a signalWith The capacitor is such that the storage node serves as a gate electrode
Act and correspond to the storage node of the plate electrodes
A thin film transistor structure in which a portion acts as a channel region
Made A semiconductor memory device characterized by the above-mentioned. 2. The semiconductor memory device according to claim 1 , wherein a portion of said plate electrode corresponding to the storage node has a lower impurity concentration than other portions. 3. The storage node and a plate electrode,
2. The semiconductor memory device according to claim 1 , wherein said semiconductor memory device is made of polysilicon. 4. The storage node and a plate electrode,
2. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device is made of amorphous silicon. 5. The storage node and a plate electrode,
2. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device is made of single crystal silicon. 6. The pulse generating means includes an oscillating circuit for generating a pulse signal, a boosting circuit for boosting the pulse signal generated by the oscillating circuit to a predetermined potential, and selecting a selection transistor when reading stored information. A supply circuit for supplying a predetermined potential previously output from the booster circuit to the plate electrode, and stopping the supply of the potential to the plate electrode before the selection of the selection transistor is released. The semiconductor memory device according to claim 1. 7. A selection transistor having a gate connected to a word line and one end of a current path connected to a bit line, a storage node connected to the other end of the current path of the selection transistor, and insulated from the storage node. A plate electrode, wherein the storage node acts as a gate electrode,
A portion of the plate electrode corresponding to the storage node has a lower impurity concentration than other portions and has a thin film transistor structure acting as a channel region; and potential supply means for setting the plate electrode to a high potential when reading information. A semiconductor memory device comprising: 8. A MOS having a diffusion layer forming source and drain regions provided at predetermined intervals in a semiconductor substrate, and a gate electrode as a word line provided on the semiconductor substrate and insulated from the semiconductor substrate. Type select transistor; a first semiconductor layer formed on one diffusion layer of the select transistor and forming a storage node; and a first semiconductor layer provided insulated on the first semiconductor layer, The area corresponding to the first semiconductor layer is larger than that of the first semiconductor layer, and the portion corresponding to the first semiconductor layer is a channel region having a lower impurity concentration than the other portions, and the other portion is a plate electrode having a high impurity concentration. And a second semiconductor layer to be formed. 9. The semiconductor memory device according to claim 8 , wherein said first and second semiconductor layers are made of polysilicon. 10. The semiconductor device according to claim 1, wherein said second semiconductor layer is made of amorphous silicon.
9. The semiconductor memory device according to 8 . 11. The semiconductor device according to claim 1, wherein the first and second semiconductor layers are made of single crystal silicon.
9. The semiconductor memory device according to 8 . 12. A selection transistor having a gate connected to a word line and one end of a current path connected to a bit line, a storage node connected to the other end of the current path of the selection transistor, and insulated from the storage node. A plate electrode, the storage node serving as a gate electrode,
A portion corresponding to the storage node of the gate electrode
Where an inversion layer is formed according to the information stored in the channel
A capacitor having a thin film transistor structure as a region; a pulse generating means for generating a pulse signal for reading information stored in the storage node; a selection signal generating means for generating a selection signal for selecting the word line; A semiconductor memory device comprising: a supply unit that supplies a pulse signal output from the pulse generation unit to a plate electrode in accordance with a selection signal output from the selection signal generation unit. 13. The semiconductor memory device according to claim 12 , wherein said supply means is constituted by an AND circuit.