JP2601147B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of an integrated circuit, and more particularly to a drive capability of an output terminal (that is, a current driver).
Dynamic capacity) can be variably controlled.

[0002]

[Prior art]

[Output Buffer] A conventional output buffer in a digital integrated circuit will be described below.

The output of a digital integrated circuit usually outputs a logic level by changing a voltage level or an amount of current. In a normal TTL logic integrated circuit, the output terminal is 2.7
When "V" or more is output, it indicates "H" level.
It indicates the “L” level when V or less is output.

FIG. 3 shows an example of a conventional output circuit and load. The transistor 202 is for "H" level drive, and the transistor 203 is for "L" level drive. When the output terminal is at “H” level, the transistor 202 is turned on,
Turn off 03. When the output terminal is at the “L” level, the transistor 202 is turned off and the transistor 203 is turned on.

[0005] In normal use, the output 206 of the integrated circuit of FIG. 3, the input stage of the next stage logic integrated circuit is connected. This is schematically represented by a load resistance 204 and a load capacitance 205.

When the load capacity is heavier than expected, the output delay increases, and when the load capacity is light, overshoot and undershoot occur in the signal.

[Drive capability variable output driver] FIG. 4
Shows an output drive circuit whose drive capability is variable from × 1 times to × 16 times.

In FIG. 4, transistors 306, 307, 30
8, 309 are P-channel transistors for driving the output to H level. Also, transistors 314, 315, 316,
317 is an N-channel transistor that drives the output to L level. In FIG. 4, both P-channel and N-channel transistors do not turn on at the same time.

Here, in order to make the drive capability variable,
A plurality of sets of P-channel and N-channel transistors are prepared, and some of them are selectively driven to determine the overall drive capability.

In order to efficiently and uniformly change the output drive capability, the drive capability of the transistor 306 is set to be the minimum unit with respect to the drive capability of the transistor.
The drive capability of transistor 307 is
The drive capability of the transistor 308 is set to be four times, and the drive capability of the transistor 309 is set to be eight times.

Similarly, the N-channel transistor 314
When the drive capacity of the
The driving capability of the transistor 5 is doubled, the driving capability of the transistor 316 is increased four times, and the driving capability of the transistor 317 is increased eight times.

In order to make the driving capability of a MOS transistor 2 ⁿ times that of the transistor having the minimum driving capability,
For example, the channel width is set to 2 ⁿ times the channel width W _ref of the transistor having the minimum drive capability.

The output driver can provide the drive capability as shown in Table 1 to the drive capability control signal 301.

[0014]

[Table 1]

[Automatic Driving Capability Correction Circuit] FIG. 5 shows an automatic driving capability correction circuit on the low level voltage side.

The transistors 409, 410, 411, and 412 constitute a dummy output driver. These transistors are composed of a group of transistors having the same size as the actual output driver.

In FIG. 5, the dimensions of each transistor are determined as follows.

The transistor 412 has the smallest drive capability among the four transistors, and has the minimum resolution drive capability of the variable drive capability.

Also, the transistor 411 is
It has twice the drive capacity of 12 and the transistor 410
The transistor 412 has four times the driving capability of the transistor 412, and the transistor 409 has eight times the driving capability of the transistor 412.

The setting of the drive capability of these transistors is the same as that of the variable drive capability driver.

Each of the transistors 409, 410, 411, and 412 has a source terminal connected to the ground 415 and a drain connected to the output terminal 417. The output terminal 417 is connected to the power supply terminal 414 via a dummy resistor 413 representing the impedance driven by the output circuit.

At the time of output, the dummy output driver drives the dummy resistor 413, and the output terminal 417 is at a low voltage level. The output voltage of the output terminal 417 passes through a low-pass filter 405, and a stable low-level drive voltage from which high-frequency components have been removed is input to one input terminal of a comparator 406.

A reference voltage obtained by dividing the power supply voltage Vcc by resistors 401 and 402 is applied to the other input terminal of the comparator 406. The comparator 406 compares the low-level drive voltage with the reference voltage, and outputs an up-count instruction when the low-level drive voltage is lower than the reference voltage, and outputs a down-count instruction when the low-level drive voltage is higher than the reference voltage. Output. The output signal of comparator 406 indicates one of up-count and down-count.

The flip-flop 408 supplies the output of the comparator 406 to the counter 407 as a command in synchronization with the clock.

The counter 407 is a 4-bit up / down binary counter. The counter 407 counts up (for example, the value of the binary counter is incremented by 1 by the output of the flip-flop 408).
Increment or countdown (eg, binary counter value)
1) .

When the counter 407 counts up, the drive capability of the dummy driver changes in an increasing direction, and when the counter 407 counts down, the drive capability of the dummy driver changes in a decreasing direction.

Here, the counter is incremented by one (1).
The change in the drive capacity corresponding to the increase / decrement (decrease by 1) is defined as one step, that is, the minimum resolution of the drive capacity.

That is, the correction circuit continues to adjust the counter until the output terminal 417 of the dummy output buffer reaches the voltage closest to the reference voltage 418. by this,
It approaches the target drive ability in steps of one step.

[Drive Capability Automatic Correction Process] FIG. 6 shows how the output voltage 503 follows the reference voltage 502. The reference voltage is the voltage indicated by 418 in FIG. 5, and the output voltage is the voltage indicated by 417 in FIG.

FIG. 6 shows an example in which the output driver is operating very ideally. The output voltage changes for each minimum step voltage and changes in a direction approaching the reference voltage. As shown in FIG. 6, the change unit is every step.

In FIG. 6, since the reference voltage is initially lower than the output voltage, the counter counts down and the output voltage decreases (503 in FIG. 6).

Next, when the output voltage exceeds the reference voltage, the counting direction of the counter changes, and the output voltage repeats up and down across the reference voltage.

In the correction circuit, the output voltage of the dummy output buffer becomes stable when the output voltage of the dummy output buffer repeats the change of one step across the reference voltage. In FIG. 6, the stable state starts from 504.

When the reference voltage changes in the middle, the output changes so as to follow the change direction of the reference voltage. This is shown at 505 in FIG.

[Output Waveform of Dummy Buffer] The output terminal 417 of the dummy output buffer of the automatic correction circuit is the same as the output of the output terminal 318 of the output driver with a given load. Therefore, when the drive capability control output 416 of the automatic correction circuit is given to the drive capability control signal 301 of the actual output driver, the output terminal 318 of the output driver
Appropriate drive capability can be obtained for fluctuations in power supply voltage / load.

This automatic correction circuit operates so as to constantly change the drive output and seek the best stable point.

However, in the automatic correction circuit described above (see FIG. 5), since the output driver is configured in a binary format (2 ⁿ times), there is a problem that a glitch occurs during the change. That is, even if the change is one step corresponding to the minimum resolution of the driving capability, there is a combination in which a glitch easily occurs depending on the change of the transistor driving the output terminal.

The generation of a glitch will be described with reference to the combination of the 4-bit variable drive capacity buffer shown in FIG.

Referring to FIG. 5, the case where the output terminal 417 outputs a low level voltage will be described. In this case, the high impedance control terminal 319 is at “1” level and the input terminal 3
20 is at the “1” level.

The high impedance control terminal 319 is "1"
When the input terminal 320 is "1", the AND gate 322
Outputs "1". The output of the AND gate 322 is supplied to the AND gates 310, 311, 31 by signals 330, 331, 332, 333 corresponding to each bit of the drive capability control signal 301.
Drive capability control signal 301 masked at 2, 313
Transistors 314, 31 corresponding to the bit of "1"
"1" level is output to the inputs of 5, 316 and 317. As a result, one of the transistors 314, 315, 316, 317 is turned on.

At the same time, the NAND gate 321 receives the signal obtained by inverting the input terminal 320 by the inverter 323 and the high impedance control terminal 319, and outputs “1” level to the signal line 324. The signal line 324 is a drive capability control signal 3
01 signal values 326, 327, 328, 329 and OR gates 302, 30
Masked at 3, 304, 305. However, since the signal line 324 is at "1" level, the OR gates 302, 303, 304, 3
All outputs of 05 become “1” level, and transistors 306,
307, 308 and 309 are all turned off.

As a result, the output terminal 318 is at "0" level,
That is, it is driven to a low level voltage.

Here, as an initial state, the transistor 31
4, 315, 316 are on. After that, when the drive capability changes by one step, the transistor
314, 315 and 316 are turned off, and the transistor 317 is turned on.

Here, if all the transistors are turned on and off at the same time, a smooth change in drive capability should appear at the output terminal 318.

However, consider an operation in the case where the time until the transistor is turned on is early and the time until the transistor is turned off is later, for example. This assumption can actually occur in terms of output buffer variation or skew. Referring to FIG. 8, a change in the output voltage of output terminal 318 will be described in detail below.

1. Transistors 314, 315, 316 on, 3
17 is in the off state, and the output is driven with the drive capacity 7 (see 701 in FIG. 8).

2. The drive capability control signal changes from 7 to 8.

3. Immediately after the change, transistors 314, 315, 31
6 remains on, while 317 changes to on (see 702 in FIG. 8).

4. Transistors 314, 315, 316 are off, 3
17 settles on (704 in FIG. 8).

FIG. 7 shows an output waveform generated at the output terminal 417 of the dummy output buffer in the actual worst case. This is an example in which the drive capability control terminal changes between drive capabilities 7 and 8. FIG. 7 is a waveform when the voltage at the output terminal is observed over time. Glitch when drive capability control signal changes between certain numbers
603 occurs.

Next, a case where the high impedance control terminal 319 is at "1" level and the input terminal 320 is at "0" level will be described.

In this case, the output 325 of the AND gate 322 becomes "0" level, and the bit mask
Masked by 0, 311, 312, 313, all outputs become "0" and the output drive transistors 314, 315, 316, 317 are turned off.

The output 324 of the NAND gate 321 is
It becomes “0” level, is masked by the OR gates 302, 303, 304, 305, and outputs “0” level to the input of the transistor corresponding to the “0” level bit of the drive capability control signal 301, and the transistor 306, 307, 308,
The corresponding one of 309 is turned on, and the output terminal 318 is driven to the “1” level.

When the high impedance control terminal 319 becomes "0", the signal line 324 is "1" and the signal line 325 is "0".
And all drive transistors 306, 307, 308, 3
09, 314, 315, 316, and 317 are turned off, and the output terminal 318 is set to a high impedance state.

[0055]

When the output buffer of the binary format as shown in FIG. 4 is used, the change of the drive capability can be controlled most easily. However, in the binary format, the drive capability is one step. Even in the case of a change, if the change has a predetermined relationship with the drive capability, a glitch occurs at the output terminal.

In particular, when the drive capability of the output circuit is controlled by using the control circuit as shown in FIG. 4, one step increase / decrease constantly occurs even in a stable state. When the driving ability is in a specific pattern, a glitch always occurs.

The glitch generated here becomes noise generated in the system, and may even cause a malfunction of the entire system.

Accordingly, it is an object of the present invention to solve the above-mentioned problem and to provide a circuit for suppressing glitches generated by switching output drivers in an output circuit with variable drive capability.

[0059]

In order to achieve the above object, the present invention relates to a control circuit for automatically correcting the drive capability of an output circuit having a variable drive capability, wherein a minimum drive capability of 2 ⁿ (n = ..) Are connected to a plurality of output transistors each having a plurality of output transistors having a drive capability of 0, 1, 2... Times, wherein the output transistor group includes at least two output transistors having the minimum drive capability. Provided is a drive capability control circuit configured to independently control a plurality of output transistors.

The present invention is also an output circuit having a variable driving capability, comprising an output transistor group for driving an output terminal, wherein the output transistor group has a minimum driving capability of 2 ⁿ (n = 0, 1, 2). ... The drive device according to claim 1, wherein a plurality of output transistors having twice the drive capability are connected in parallel, and at least two output transistors having the minimum drive capability are included, and the drive capability of the output terminal is equal to the drive capability. An output circuit corrected by a signal for controlling the plurality of output transistors provided in a capacity control circuit is provided.

The present invention further provides an output circuit having a variable drive capability, which is a preferred embodiment of a drive capability control circuit comprising an output transistor group, a comparator, a counter, and a gate means. 3 provides an output circuit as described below.

[0062]

The operation of the present invention will be described below. According to the present invention, in a drive capability automatic correction circuit for correcting the drive capability of an output circuit, a redundant bit is provided in a dummy output buffer and an output terminal driver so as to avoid a carry, so that a carry state is prevented. Can be suppressed from occurring.

That is, in the present invention, the output circuit includes output transistors having a drive capability of 2 ⁿ (n = 0, 1, 2,...) Times the minimum drive capability, a dummy output buffer and a comparator. , A drive capability control circuit composed of an up / down counter, a transistor having the minimum drive capability and the least significant bit of the counter being redundantly provided as at least two bits, and the counter being up / down in a range of at least + 1 / -1 Also, the use of a redundant driver corresponding to the least significant bit avoids carry, and suppresses glitches generated by binary switching for small changes in a stable state.

[0064]

Embodiments of the present invention will be described below with reference to the drawings.

[0065]

Embodiment 1 [Overview of Overall Embodiment] FIGS. 1 and 2 show an embodiment of the present invention.

FIG. 1 shows a low-level drive capability correction circuit, and FIG. 2 shows a high-level drive capability correction circuit. The low-level drive correction circuit and the high-level drive correction circuit shown separately in FIG. 1 and FIG.
k115 and a low-level drive capability control signal, which are connected to each other to constitute an output drive correction circuit as a whole.

In the drive capability correction circuit according to the present embodiment, the description of the entire configuration having the same configuration as that of the above-described conventional example will be omitted, and the features thereof will be described below.

FIG. 1 shows a correction circuit on the low level side of this embodiment. The output of the dummy output buffer 172 is connected to the power supply 168 via the dummy output resistor 167. Dummy output resistance 16
7 and the low-level voltage generated by the dummy output buffer 172 are filtered by the low-pass filter 107 and output from the comparator 109.
Is compared with a low-level reference voltage.

The low-level reference voltage is equal to the power supply voltage 177
Is divided by a resistor 101 and a resistor 102 into a desired voltage.

The comparator 109 outputs “1” when the low-level voltage is lower than the reference voltage, and outputs “0” when the low-level voltage is higher than the reference voltage.

This output is synchronized with the clock 115 by the edge trigger flip-flop 111 and input to the up / down control inputs of the redundant up / down counters 113 and 170.

That is, when the low level voltage output from the dummy output buffer 172 is lower than the reference voltage, the counters 113 and 170 count up according to the clock 115,
If it is higher than the reference voltage, count down. The counter output is input to the drive capacity control inputs 128, 129, 130, 131, 132 of the dummy output buffer 172 to control the output drive capacity.

Here, the dummy output buffer 172 which is a feature of the present invention will be described. This buffer has a drive capacity of 2 ⁿ times the minimum drive capacity (n = 0, 1,
2, a single transistor having the minimum drive capability is redundantly provided.

[0074] In practice, when the transistor 153, 154 is a driving ability or 1 times the drive capability of the minimum unit, preparative <br/> transistor 152 is twice, the transistor 151 is four times, Trang <br/> register 150 Will be set to have eight times the drive capacity.

FIG. 2 shows a high-level drive capability correction circuit. A block 174 is a circuit similar to the dummy output buffer 172 of the low-level drive correction circuit, and is a low-level drive capability correction circuit that drives to the low voltage side with the corrected capability.

Block 173 is a dummy output buffer for driving on the high voltage side, and is used for correction on the high voltage side. In blocks 173 and 174, the voltages divided by the high-level / low-level drive are passed through the low-pass filter 108 in the same manner as the low-level correction circuit of FIG.
The reference voltage generated in step 4 is compared with the reference voltage by the comparator 110. Then, based on the output of the comparator 110, similarly to the low-level drive circuit, the output drive is corrected, and the high-level drive capability is determined.

[Dummy Buffer] The driver in this embodiment has a plurality of expressions for each drive capability. Table 2 shows combinations of transistors having a predetermined level of drive capability. In Table 2, it means that the transistor corresponding to the signal name described in the column of combination becomes active.

[0078]

[Table 2]

The buffer according to the present embodiment is characterized in that the occurrence of glitches can be suppressed when a change between adjacent drive capabilities (for example, 7 and 8) repeatedly occurs.

As described above, in the conventional circuit, a glitch occurs when a carry occurs in the binary number of the drive capability control terminal.

In the present invention, the occurrence of glitches is suppressed by providing the drive capability control terminal with redundancy to avoid carry. If the output of the drive capability control terminal greatly changes, glitches may still occur, but the occurrence of glitches due to the carry described in the above conventional example is suppressed. A glitch that occurs in a stable state in which one step of variation is repeated across the reference voltage is suppressed.

[Counter Control Circuit] Next, a counter for driving the dummy output buffer will be described. This counter has a redundant bit as the least significant bit.

Table 3 shows a transition table of the counter redundancy section 170. In the transition table of Table 3, from the input terminal up / down, the current state Q × 1A, Q × 1B, to the next state N × 1A,
N × 1B, carry is determined.

[0084]

[Table 3]

Next, Table 4 shows a transition table of the normal counting section 113 of the counter.

[0086]

[Table 4]

[Operation Example of Counter] Here, the operation of the entire counter will be described based on an example. First, it is assumed that the correction circuit is in a stable state.

It is assumed that the drive capacity is stable between 7 and 8, and the drive capacity at a certain point in time is 7. The state at that time is Q × 8, Q × 4, Q × 2,
Q × 1A, Q × 1B = 0, 1, 1, 1, 1, 0.

When the drive capability changes to 8, the up / down input is brought up, and in the next clock, Q × 8,
Q × 4, Q × 2, Q × 1A, Q × 1B = 0, 1, 1, 1, 1,
Can be changed to 1.

Next, the correction circuit changes the up / down input to the down state and controls the drive capability to change to 7. Here, the counters are Q × 8, Q × 4, Q × 2, Q
Return to × 1A, Q × 1B = 0, 1, 1, 1, 0.

At this time, the only transistors that are actually switched are the transistors corresponding to Q × 1B.
The transistor 154 corresponding to Q × 1B has the minimum unit driving capability, and the change of the output terminal due to turning on / off of the transistor 154 is a minimum voltage step.

By controlling the counter in this manner, a change in the output transistor of the drive stage due to the carry is suppressed, and the occurrence of glitch is prevented.

[Output Driver] The drive capability control input of the output terminal is controlled by being connected in parallel with the control input terminal of the dummy output buffer. As a result, all output terminals of the integrated circuit can be driven with the most appropriate driving capability for the resistive load connected to the dummy output buffer.

[0094]

As described above, according to the present invention,
In a drive capability automatic correction circuit for correcting the drive capability of an output circuit having a variable drive capability, a redundant bit is provided in a dummy output buffer and an output driver, and a configuration is made to avoid carry, so that the output driver Glitch generation at the time of switching can be suppressed.

Further, in the present invention, the least significant bits of the output driver and the counter having the minimum drive capability are provided redundantly, and even if the counter is up / down in the range of at least + 1 / −1, the least significant bit is handled. The use of the redundant driver described above has an advantage of suppressing glitches caused by carry in a stable state.

Further, the present invention has an advantage that all output terminals of the integrated circuit can be driven with the most appropriate driving capability for the resistive load connected to the dummy output buffer.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a low-level drive capability correction circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a high-level drive capability correction circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a drive output of a standard TTL.

FIG. 4 is a diagram showing a configuration of a variable drive capability output driver.

FIG. 5 is a conventional drive capability automatic correction circuit diagram.

FIG. 6 is a timing chart showing a process of adjusting the output drive capability of the variable drive capability driver.

FIG. 7 is a diagram showing how glitches occur in the output voltage of the variable drive capability output driver.

FIG. 8 is a diagram showing an output voltage of a variable drive capability output driver.

[Explanation of symbols]

101, 102, 103, 104 Internal circuit resistance 105, 107, 106, 108 Low-pass filter 109, 110 Comparator 111, 112 Edge-triggered D-type flip-flop 113, 114 3-bit up / down counter 118, 119, 120 , 121, 122 Low-level voltage drive capability output terminal 128, 129, 130, 131, 132 Low-level voltage drive capability control input terminal of dummy output buffer 133, 165, 166 Ground 135, 136, 137, 138, 139 Two-input AND Gate 140, 141, 142, 143, 144 2-input OR gate 145, 146, 147, 148, 149 2-input AND gate 150 N-channel output driver (drive capacity x 8) 151 N-channel output driver (drive capacity x 4) 152 N-channel output driver (drive capacity x 2) 153, 154 N-channel output driver (drive capacity x 2)
1) 155 P-channel output driver (drive capacity x 8) 156 P-channel output driver (drive capacity x 4) 157 P-channel output driver (drive capacity x 2) 158, 159 P-channel output driver (drive capacity x
1) 160 N-channel output driver (drive capacity x 8) 161 N-channel output driver (drive capacity x 4) 162 N-channel output driver (drive capacity x 2) 163, 164 N-channel output driver (drive capacity x
1) 167 Dummy output impedance setting external resistor 168, 169 Power supply 170, 171 Redundant up / down counter 172, 173, 174 Dummy output buffer 177 Power supply voltage 201 TTL integrated circuit 202, 203 NPN transistor 204 Load resistance 205 Load capacitance 206 Output terminal 207 Resistance 208 Diode 301 Drive capacity control input 302, 303, 304, 305 2-input OR gate 306 P-channel output driver (drive capacity x 1) 307 P-channel output driver (drive capacity x 2) 308 P-channel output driver (drive capacity x 4) 309 P-channel output driver (drive capacity x 8) 310, 311, 312, 313 2-input AND gate 314 N-channel output driver (drive capacity x 1) 315 N-channel output driver (drive capacity x 2) 316 N-channel output Driver (drive capacity x 4) 317 N-channel output driver (drive capacity x 8) 318 Output terminal 319 High impedance control terminal 320 Output buffer input terminal 321 2-input NAND gate 322 2-input AND gate 326, 327, 328, 329 High level drive capability control signal 330, 331, 332, 333 Low level drive capability control signal 401 , 402 Resistance 403 Oscillation circuit 404, 405 Filter 406 Voltage comparator 407 Up / down counter 408 Edge trigger D type flip-flop 409 N-channel output driver (drive capacity x 8) 410 N-channel output driver (drive capacity x 4) 411 N-channel Output driver (drive capability x 2) 412 N-channel output driver (drive capability x 1) 413 Dummy resistor 414 Power supply 415 Ground 416 Drive capability control output 501 Output voltage 502 Reference voltage 503 Dummy buffer output voltage 504 Adjustment circuit lock start point 505 Reference voltage change 506 Re-stabilization 507 Counter up / down input 5 08 Clock 601 Voltage 602 Drive control input 603 Glitch 701 Output drive 7 voltage 702 Change to output drive 15 703 Change to output drive 8 704 Stable at output drive 8

Claims (5)

(57) [Claims] 1. A control circuit for automatically correcting the drive capability of an output circuit having a variable drive capability, wherein an output transistor having a drive capability of 2 ⁿ (n = 0, 1, 2,...) Times the minimum drive capability at an output terminal. A plurality of output transistors connected in parallel, the output transistor group including at least two output transistors having the minimum drive capability, and a drive configured to control the plurality of output transistors independently. Capability control circuit. 2. An output circuit having a variable drive capability, comprising an output transistor group for driving an output terminal, wherein the output transistor group has a minimum drive capability of 2 ⁿ (n
= 0,1,2...), A plurality of output transistors having a driving capability twice as large as each other, and at least two output transistors having the minimum driving capability. Item 2. An output circuit corrected by a signal for controlling the plurality of output transistors provided in the drive capability control circuit according to Item 1. 3. A plurality of output transistors for driving an output terminal in an output circuit having a variable drive capability, the plurality of outputs having a drive capability of 2 ⁿ (n = 0, 1, 2,...) Times the minimum drive capability. An output transistor group including at least two output transistors having the minimum drive capability and connected in parallel, gate means for individually driving the plurality of output transistors, and correcting the drive capability of the output terminal A counter having one input terminal connected to the output terminal of the output driver, and the other input terminal connected to a predetermined reference voltage. A first counter for counting up or counting down bits; and a second counter for controlling least significant bits. Printer consists output transistor as many at least two bits having the minimum drivability,
Connected to gate means for controlling the output transistor having the minimum drive capability, wherein the output of the first counter controls the output transistor having a drive capability of 2 ⁿ times (where n is not 0) the minimum drive capability. The comparator has an output connected to an up / down control input terminal of the counter, compares the drive capability of the output terminal with the reference voltage, and outputs the output signal of the comparator. An output circuit which counts up or down the counter to correct the drive capability of the output terminal. 4. The second counter is composed of a plurality of registers.
When all the registers are in the set state, all the registers are reset, and the first counter is counted up. At the time of the countdown, the registers are reset one by one, and all the registers are reset. 4. The output circuit according to claim 3, wherein when in a state, all the registers are set and the first counter is counted down. 5. An output transistor having a lower drive capability from a gate means for controlling an output transistor having the highest drive capability of the output transistor group from the most significant bit side to the lower bit side of the output of the first counter. 4. The output circuit according to claim 3, wherein the output circuit is connected to the gate means for controlling the power supply.