JP2602238B2 - Rotating head digital signal reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing an audio PCM signal recorded on a magnetic recording medium by a rotating head on one oblique track per unit time. More particularly, the present invention relates to a rotary head type digital signal reproducing apparatus which shortens a PLL pull-in time at the time of high-speed search and improves data reading accuracy.

[Technical background of the invention and its problems]

In an R-DAT (rotating head digital audio tape recorder), an audio PCM signal and a subcode signal are digitally recorded together with a clock required to reproduce these signals, and a modulated signal is reproduced at the time of reproduction. And a self-clock system that can extract the clock from the audio PCM signal and the subcode signal based on the clock.

The above clock is extracted by the PLL circuit.
It takes some time for the circuit to be pulled into the recovered clock and locked. Therefore, before the recording area (PCM area or SUB-1, SUB-2 area) of the audio PCM signal and the subcode signal as the information to be originally recorded and reproduced,
A clock recording area (PLL area or margin area) is provided, and the original information recording area is reproduced after the PLL circuit locks to the reproduction clock.

The data required for high-speed search consists of sub-code areas (SUB-1, SUB-
It is recorded in 2). Each block is 288 as shown in the subcode block format of FIG.
Consists bit, the header portion of the SYNC, 16 bits of 8 bits (W _1, W _2), is composed of 8-bit parity and 256 bits of sub-code data, the 8-bit 8-
10 modulated and recorded.

W ₁ contains the frame address to identify the 1 PCM interleaved block, and W ₂ contains the block address to identify each block and a bit to identify whether it is a subcode block or a PCM block. In.
P is a simple parity for W ₁ and W ₂ , and is checked at the time of reproduction to determine whether the data of W ₁ / W ₂ is correct. That, W ₁ / W ₂ can distinguish the type of data which follows by checking, it is possible proper precise data synchronization at a high speed search based on the identification of the data.

By the way, when a subcode signal such as a start identification signal (ST-ID) is searched at a high speed, the magnetic tape runs at a speed of, for example, 200 times the normal recording / reproducing speed.
At this time, a drum servo is applied to the rotating drum based on the clock extracted by the PLL circuit, and the relative speed between the head mounted on the rotating drum and the magnetic tape is substantially the same as the relative speed during normal recording and reproduction. Is controlled so that

However, the two heads arranged at 180 ° angular intervals on the rotating drum have different azimuths, and due to this azimuth difference, the head is reproduced from the normal azimuth A head at the time of FF. The clock frequency is about 2% lower than normal (ie, 9.408 × 9
8 / 100MHz). On the other hand, the frequency of the negative azimuth B head increases by about 2% (ie, 9.408 × 102/100 MHz).
z). Conversely, at the time of REW, the frequency of the A head increases by about 2%, and the frequency of the B head increases by about 2%.
%. Therefore, the time until the PLL circuit locks the phase becomes longer than in the case of normal recording and reproduction.

Conventionally, if the clock is not recorded in the margin area before the PLL area, or even if it is recorded, if the reproduction is not sufficiently performed by a head touch or the like, the sub code There is a problem that the signal reading rate is reduced.

[Object of the invention]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-described conventional problems, and provides a rotary head type digital signal reproducing apparatus in which a clock is reliably extracted even at the time of high-speed search and data reading accuracy is improved. It is intended to be.

[Summary of the Invention]

The present invention detects a frequency difference between the PLL clock and the system clock every half rotation of the rotary drum, and supplies a difference signal based on the frequency difference to the PLL circuit as an error signal during the next half rotation of the rotary drum. In addition, the pull-in time of the PLL is shortened by bringing the free-run frequency closer to the frequency at the time of the high-speed search, thereby reliably extracting the clock at the time of the high-speed search and improving the data reading accuracy.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment according to the present invention.

In the figure, 1 is a mechanism block including a tape running system, 2 is a rotating drum mounted with two heads A and B, which are arranged at an angular interval of 180 ° and have different azimuths,
Reference numeral 3 denotes a magnetic tape which runs around the rotating drum 2 while being wound in a 90 ° angular range section, for example.

Reference numeral 4 denotes a head switch which switches the scanning period of the two heads A and B based on the head switching pulse HSWP (/ B). Reference numeral 5 denotes a head which is picked up from the magnetic tape 3 by the heads A and B via the head switch 4. Amplifier for amplifying the reproduction RF signal supplied alternately to the optimum level for reproduction processing; 6 is a frequency characteristic of the heads A and B and the magnetic tape 3 for accurately demodulating recording data from the reproduction RF signal. Equalizer circuit that compensates for waveform equalization,
Reference numeral 7 denotes a PLL circuit for extracting a clock from the reproduced RF signal via the equalizer circuit 6.

Reference numeral 8 denotes a decoder to which the reproduction RF signal from the equalizer circuit 6 and the PLL clock extracted from the reproduction RF signal by the PLL circuit 7 are supplied, and an 8-10 demodulator 8A,
It comprises a sync address detection circuit, an error correction circuit for performing average value interpolation and the like on data with a flag, a subcode decoder for reading subcode information, and the like.
10 Signal processing at the time of reproduction, such as demodulation, error correction, and interpolation, is performed.

Reference numeral 9 denotes a crystal oscillator that generates a system clock of 9.408 MHz, which is the transmission rate of R-DAT channel bit data. Reference numeral 10 denotes a frequency comparison circuit including a counter and the like. And a system clock generated by the crystal oscillator 9. The frequency of the two clocks is compared based on a flag indicating the result of the parity check from the decoder 8, and an error signal based on the frequency difference is output from this output. Is taken out.
Reference numeral 11 denotes an average value circuit which fetches an error signal from the frequency comparison circuit 10 a predetermined number of times based on a flag indicating the result of the parity check from the decoder 8 and outputs an average value, and 12 denotes a D / A converter or a pulse. A converter composed of a generator, etc., and uses the above average value from the average value circuit 11 as a deviation amount of the PLL clock from the system clock.
This is fed back to the circuit 7.

Reference numeral 13 denotes a D / A converter for converting a digital audio signal from the decoder 8 into an analog signal, and reference numeral 14 denotes a low-pass filter (LPF) for extracting only an analog signal component included in an original signal. Reference numeral 15 denotes a system control circuit that controls the operation of the mechanism block 1 and the entire system according to various modes.

Next, the operation of the device having the above configuration will be described.

The relative speed between the tape and the head during the high-speed search is controlled so as to match the relative speed between the tape and the head during normal reproduction. That is, the relative speed between the tape and the head is controlled so that the frequency of the signal becomes the same as in the normal reproduction even during the high-speed search, and the data recorded on the magnetic tape is intermittently read.

In order to make the relative speed at the time of high-speed search coincide with the relative speed at the time of normal reproduction, for example, a method of applying a servo to the drum motor by detecting the frequency of the reproduction signal (130 KHz), or detecting the envelope frequency (In this case, the number of rotations of the drum motor is constant), a method of applying servo to the reel motor or the like is adopted.

At this time, since the head traces each track one after another, the reproduced RF signal is as shown in FIG.
In FIG. 3, (a) shows the relationship between the head switching pulse and the reproduced RF signal at the time of REW, and (b) shows the relationship between the head switching pulse and the reproduced RF signal at the time of FF. In this case, 1
Since one head traces alternately across the same azimuth track and the reverse azimuth track, the reproduced RF signal output at this time is large while tracing the same azimuth track and small during tracing the reverse azimuth track. The output form is as shown in the figure.

Generally, a high-speed search is performed by reading a sub-code signal recorded in a sub-code area. Then, the SYNC of the subcode block format shown in FIG. 4 is detected, and a parity check is further performed, and the data determined to be correct is loaded into the RAM.

By the way, as described above, when a high-speed search at 200 times speed is performed, the running direction of the magnetic tape (FF direction or REW direction)
Direction), the frequency of the reproduced RF signal is shifted by approximately ± 2%, so that the frequency where there is no PLL signal is, for example, 9.4%.
When the frequency is roughly adjusted to 08 MHz, the output of the low-pass filter in the PLL circuit is approximately as shown in FIG.
The pull-in time is inevitably required due to the frequency difference of%. FIG. 2A shows a head switching pulse,
(B) shows the envelope waveform of the reproduced RF signal,
The tape running direction is shown as the FF direction.

When the tape speed is kept almost constant by applying the reel servo (when the tape speed fluctuation can be ignored)
The frequency of the reproduced RF signal obtained every half rotation of the rotating drum is 9.408 MHz as long as the signal is present and the PLL is locked
The value is almost symmetric about.

For example, the present invention is applied to a case in which the PL on the A head side is searched during the search in the FF direction.
Set the recovered clock of L to a predetermined width (oscillation frequency of crystal oscillator 9.4
Counts the free-run frequency at the next half rotation of the rotating drum based on the amount of deviation from the system clock generated by the crystal oscillator.
By shifting the 408 MHz by a predetermined amount (for example, + 2%), the pull-in time of the PLL is shortened.

Thus, at the time of high-speed search, the mechanism block 1 and necessary circuits constituting the system are controlled to the high-speed search mode (including the direction of FF and REW) based on the command signal from the system control circuit 15. The reproducing RF signal picked up from the magnetic tape 3 by the two heads A and B every half rotation of the rotary drum 2 is alternately reproduced by a reproducing amplifier 5 via a head switching switch 4 switched by a head switching pulse. , And is supplied to a PLL circuit 7 through an equalizer circuit 6.

The PLL circuit 7 receives the reproduction R supplied from the equalizer circuit 6.
From the F signal, only a clock necessary for reliably reproducing the audio PCM signal and the subcode signal is extracted and supplied to the decoder 8 and the frequency comparison circuit 10 as a PLL clock. In this frequency comparison circuit 10,
The frequency comparison between the PLL clock from the PLL circuit 7 and the system clock from the crystal oscillator 9 is performed based on a flag indicating the result of the parity check supplied from the decoder 8. An error signal based on the frequency difference is output.

That is, since there is a portion where no signal is recorded on the tape on which recording has been performed by the user himself, in order to detect that the signal is present and the PLL is locked,
The result of the parity check is used, and the frequency of the PLL clock and the frequency of the system clock in the vicinity determined to be correct as a result of the parity check are compared, and this comparison result is used as an error signal.

The error signal from the frequency comparison circuit 10 is supplied to an averaging circuit 11, from which the error signal is fetched a predetermined number of times based on a flag indicating the result of the parity check from the decoder 8 and averaged. The value is output. That is, at the time of high-speed search, since the noise bar comes in one after another, the above-mentioned SYNC is erroneously detected, and the parity check may be judged to be correct. Therefore, these detected results are taken a predetermined number of times, and the average value is taken. The configuration is adopted.

The above average value output from the average value circuit 11 is supplied to a converter 12 composed of a D / A converter or a pulse generator, etc., and the output therefrom is used as a shift amount of the PLL clock with respect to the system clock. And the free-run frequency at the time of high-speed search is set. As a result, the output of the low-pass filter in the PLL circuit 7 becomes as shown in FIG. 2D, and the output is obtained by counting a predetermined number of times based on the flag indicating the result of the parity check shown in FIG. The free run frequency is shifted by a predetermined amount (for example, ± 2%) with respect to the A and B heads by the average value.

In the above-described embodiment, the phase comparison of the PLL is not shown, but is performed by the envelope detection circuit only at the position where the reproduced RF signal exists. The magnetic tape 3
The detection control of the traveling direction is performed by the system control circuit 15, and in the REW direction,
For example, when + 2% is detected on the A head side, it is -2% on the B head side.

〔effect〕

According to the present invention described above, a frequency difference between the PLL clock and the system clock is detected every half rotation of the rotating drum, and a difference signal component based on the frequency difference is used as an error signal during the next half rotation of the rotating drum. Supply to the PLL circuit to make the free-run frequency close to the frequency at the time of high-speed search.
Since the pull-in time is shortened, a clock can be reliably extracted even during a high-speed search, and data reading accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the device according to the present invention, FIG. 2 is an operation waveform diagram for explaining the present invention, FIG. 3 is a diagram showing a reproduced RF signal at the time of high-speed search, FIG. The figure shows the sub-code block format in R-DAT. 7: PLL circuit, 10: Frequency comparison circuit, 11: Average value circuit, 12: Converter.

Claims (1)

(57) [Claims] 1. A rotary head type digital signal reproducing apparatus in which a relative speed between a tape and a rotary drum on which two heads are mounted during a high speed search is controlled so as to match a relative speed during normal reproduction. Reproduction RF from two heads every half rotation of the rotating drum
A signal is supplied alternately, and only a clock is extracted from the reproduced RF signal to output a PLL clock, and a frequency difference between the PLL clock and a system clock from the crystal oscillator is used as a flag indicating a result of a parity check. A frequency comparison circuit for comparing the error signals based on a frequency difference between the two clocks, and an average value circuit for fetching the error signal a predetermined number of times based on a flag indicating a result of the parity check and outputting an average value thereof And a converter that feeds back the average value output to the PLL circuit as a deviation amount of the PLL clock from the system clock, and detects a frequency difference between the PLL clock and the system clock every half rotation of the rotating drum, and An error signal based on the difference is supplied to the PLL circuit during the next half rotation of the rotary drum. Head type digital signal reproducing apparatus.