JP2602808B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, for example, a method for manufacturing a MOS capacitor on a silicon substrate having a three-dimensional shape.

[Conventional technology]

MOS dynamic memory (dRAM) devices are being miniaturized and highly integrated in accordance with the proportional reduction rule. The MOS capacitor which is a component of the dRAM is no exception, and the gate oxide film thickness tox and the area S are being reduced. Assuming that the scaling factor is α, the gate oxide film thickness is tox / α and the area is S / α ² . The capacitance C of a MOS capacitor is expressed by
Since C = εS / tox, the capacitance C ′ after proportional reduction becomes C ′ = C / α, which is reduced to 1 / α. When the capacitance of the MOS capacitor is reduced in this way, a soft error due to the alpha ray is likely to occur, and the ratio to the capacitance of the bit line is reduced to reduce the sensing margin, resulting in malfunction. Thus in general the area of the MOS capacitor is not the S / alpha ^2, was done to stop the reduction of S / alpha. However, the size reduction is progressing with each generation, and obtaining a highly reliable dRAM is approaching its limit.

The use of an insulating film having a large dielectric constant, for example, a Ta ₂ O ₅ film as a means for increasing the capacity of the MOS capacitor has been studied, but has not been put to practical use yet. Also, the use of highly reliable silicon oxide film with a thickness of 10 nm or less is being considered, but this also requires extremely high-purity pure water and chemicals, and requires a clean room with high cleanliness. Is not practical.

Therefore, at present, as an effective method for increasing the capacitance of a MOS capacitor, a method of digging a groove in the surface of a semiconductor substrate to substantially increase the capacitor area without increasing the occupied area is being studied. However, when such grooves are formed with vertical side walls by an anisotropic etching method such as reactive ion etching (RIE), the following problems occur. That is, the corners (corners) at the top or bottom of such grooves (recesses) have extremely small radii of curvature.
When the gate film is formed by thermal oxidation, the thickness of the oxide film is smaller at the corners than at the flat portions. This phenomenon is explained as follows. When silicon is oxidized, the volume of the formed oxide film is about 2.3 times that of the original silicon. For this reason, as oxidation progresses, a compressive stress acts on the oxide film side at the silicon-silicon oxide film interface, and the concentration of stress occurs at the above-mentioned corners, so that oxidation is considered to be suppressed.

When the oxide film thickness at the bottom or upper corner of the groove is thinner than the flat portion, the withstand voltage becomes lower at this portion, which causes a large leak current to flow at a low electric field. If the thickness of the gate oxide film is increased in order to keep the leakage current at the working voltage sufficiently small, the thickness becomes too large in the flat portion, and the effect of increasing the capacity by enlarging the area by digging the groove is reduced.

According to the present invention, an oxide film having a uniform thickness, for example, a gate oxide film is formed on the surface of a semiconductor substrate on which a concave portion or a convex portion is formed, so that the reliability of a MOS capacitor or the like can be improved. It is an object to provide a method for manufacturing a semiconductor device.

[Means for solving the problem]

The present invention exposes the surface of the semiconductor substrate on which the concave portions or the convex portions are once formed in an oxidizing atmosphere containing a fluorine compound,
Forming a thermal oxide film on the semiconductor substrate; Thereafter, the thermal oxide film is removed by etching to make the shape of the concave portion or convex portion on the silicon surface round, and then a new oxide film is formed on the silicon surface.

[Action]

 Next, the operation will be briefly described.

When a fluorine compound such as NF ₃ gas is added to an oxidizing atmosphere, NF ₃ is thermally dissociated on the silicon surface to form a fluorine radical such as NF, NF ₂ , F or F ₂ . Fluorine atoms have a higher electronegativity than silicon, and the bond energy of Si-F bonds is larger than that of Si-Si bonds.Therefore, the state of Si and F bonded by the arrival of a fluorine compound and the state of dangling bonds of Si on the Si surface To form In a dangling bond, silicon is easily bonded to oxygen. Further, since the Si-F bond has a much higher electronegativity of F than silicon, the silicon atom is an ionic bond having a positive charge. Therefore, bonding with oxygen molecules having negative ions becomes easier.

Thus, the arrival of fluorine at the silicon surface makes the silicon more oxidizable and, on average, increases the interfacial reaction rate in the oxidation.

For example, when the silicon surface is oxidized at 700 ° C. in dry oxygen to which 100 ppm of NF ₃ is added, the linear law oxidation coefficient B / A and the parabolic law oxidation coefficient B are 2.6 × 10 ⁻² μm / h and 4.9 × 10
^-4 μm ² / h, and in the case of oxidation in dry oxygen at the same temperature, B / A = 2.6 × 10 ⁻⁴ μm / h, B = 3.6 × 10 ⁻⁴ μm ² / h,
B / A is two orders of magnitude higher than NF ₃ addition. From now on, the A value that is a measure of the transition from the linear law region to the parabolic law region is
It can be seen that the addition of NF ₃ reduces the temperature from 1.4 μm to 190 °.

In other words, in the case of dry oxygen to which NF ₃ has been added, the transition from thinner film thickness to oxidation by diffusion control occurs as compared to the case of oxidation in dry oxygen alone.

As a result, for example, the corner portion of the convex portion has a thinner oxide film due to the action of stress than the flat portion other than the corner portion of the convex portion, but diffusion control is faster than in the case where the fluorine compound is not added by the arrival of fluorine. Oxidation due to the Si / SiO ₂ interface is rounded because oxidation due to diffusion control can be suppressed at the corners of the concave part, while oxidation is suppressed at the corners of the concave part. It is considered to be formed in

〔Example〕

FIGS. 7A to 7E show a dRAM as an embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of a cell. First, FIG. 1 (a)
As shown in the figure, a p-type Si substrate with a specific resistance of about 10Ω / cm (1)
Next, a field oxide film (2) of about 100 to 1000 nm is formed. The field oxide film (2) is formed by, for example, a LOCOS method using a nitride film as a mask, a method of forming an oxide film on the entire surface and selectively etching the oxide film, or a method of digging a groove in the field region in advance and embedding the oxide film in the groove. And the like. Thereafter, a groove (3) is formed in the MOS capacitor region of the dRAM cell as shown in FIG. 1 (b).
The groove (3) is formed by, for example, a RIE method using a gas containing CF ₄ , SF ₆ , CCl ₄ or the like as a main component or a gas containing H therein. Since the mask in the RIE process may be lost by etching itself with a normal photoresist, it is preferable to use, for example, a SiO ₂ / Si ₃ N ₄ / SiO ₂ film by CVD.

Thereafter, as shown in FIG. 1 (c), an oxide film (4) (rounded oxide film) is once formed in oxygen containing 50 ppm of NF ₃ at 800 ° C. for 30 minutes, and then this oxide film (4) Is removed by etching. Thereafter, as shown in FIG. 1 (d), a gate oxide film (5) having a thickness of 15 nm is formed in dry oxygen at 900 ° C. by a well-known method. 6) is formed.

Thereafter, as shown in FIG. 1 (e), the polycrystalline silicon (6) of FIG. 1 (d) is patterned to form a capacitor electrode (6 '), and then a new gate is formed in the switching MOSFET region (9). An oxide film (5 ") is formed, a gate electrode (6") is formed thereon, and n ^{+ -type} layers (7) and (8) of source and drain regions are formed. )
Is completed.

The effects of the above embodiment will be described below. A MOS capacitor having a gate oxide film formed according to the above embodiment, including 100,000 grooves, and having a common capacitor electrode, was dried in a dry oxygen atmosphere by a conventionally used method.
MOS of similar structure with gate oxide film formed at ℃
Capacitor leakage current (gate voltage Vg-current Ig characteristics)
Were compared. FIG. 2 shows the comparison data. As is clear from the figure, in the present embodiment, the league current is significantly reduced as compared with the conventional method.

Thus, according to the present embodiment, the gate oxide film can be formed with a uniform thickness without causing stress concentration at the corners of the groove during oxidation, and without increasing the leakage current of the MOS capacitor. A large capacitance can be obtained by reducing the gate oxide film thickness.

In the above example, oxidation of NF ₃ was performed at 800 ° C., 50 ppm, NF ₃
Although 30 minutes was performed in the / O ₂ atmosphere, the conditions are not limited to this example.

For example, the literature (M. Morita, et.al.appl.Phys.Lett., Vol. 4
5, No. 12, P. 1312 “Fluorine-enhanced thermal oxidati
If the addition of on of silicon in the presence of NF 3 " increase in oxide film thickness as described in (1984)) is NF ₃ is a trace amount, the higher the oxidation temperature, is remarkable. Further, NF ₃ since the addition amount of etching of the oxide film is also simultaneously proceed in accordance with increases, the oxide film thickness is substantially constant relative to the NF ₃ amount. therefore, a desired oxide film NF ₃ amount and the oxidation temperature as a parameter The thickness may be appropriately formed.

In this embodiment, the oxide film (4) formed by adding NF ₃ is removed by etching, and then a gate oxide film (5) is newly formed. However, the oxide film (4) formed by adding NF ₃ is used as it is as the gate oxide film. Is also possible.

〔The invention's effect〕

According to the present invention, it is possible to form a gate oxide film having a uniform thickness on the surface of a semiconductor substrate having a three-dimensional shape such as a concave portion or a convex portion. This is because, according to the conditions of the present invention, the variation in the integral value of the stress remaining in the growing oxide film in the film thickness direction (that is, the integration of the stress in the flat portion and the corner portion of the concave portion or the convex portion in the film thickness direction). Value difference) is kept at about 10% or less, and as a result, stress concentration is effectively prevented. Therefore, using this gate oxide film, for example, a MOS capacitor having a large capacitance and a small leak current can be formed. Also, if a highly integrated dRAM is configured using this MOS capacitor, the probability of a malfunction due to a soft error in the dRAM can be reduced, and the operation margin of the sense amplifier can be increased.

Further, in general, the relaxation of the stress concentration in the oxide film becomes remarkable from about 950 ° C. or more in an oxidizing atmosphere, and it is practically difficult to reduce the stress concentration below the temperature.

However, in the present invention, when the surface of a semiconductor substrate having a three-dimensional shape such as a convex portion or a concave portion is rounded by oxidation (rounding oxidation), a fluorine compound is added to an oxidizing atmosphere so that the substrate surface can be sufficiently heated even at 800 ° C. or less. It is possible to perform rounding oxidation having an effect of rounding the three-dimensional shape by a low-temperature treatment.

[Brief description of the drawings]

1A to 1E are cross-sectional views showing a manufacturing process of a dRAM cell as one embodiment of the present invention, and FIG. 2 shows a leakage current characteristic of a gate oxide film for explaining an effect of the embodiment. It is a characteristic view shown in comparison with a conventional example. DESCRIPTION OF SYMBOLS 1 ... P-type Si substrate, 2 ... Field oxide film, 3 ... Groove, 4 ... Rounded oxide film, 5, 5 ', 5 "... Gate oxide film, 6 ... Polycrystalline silicon gate electrode, 6 ', 6 "... Polycrystalline silicon gate electrode, 7,8 ... n ⁺ type layer.

Claims (4)

(57) [Claims] A step of etching a substrate having a surface made of silicon to form a groove in the surface; and a step of etching the substrate surface including a corner at the upper end of the groove in an oxidizing atmosphere to which a fluorine compound gas is added. Forming a thermal oxide film by thermal oxidation;
Forming a device on the surface of the substrate. 2. The method according to claim 1, wherein the step of forming the thermal oxide film rounds a corner at an upper end of the groove. 3. After forming a thermal oxide film in an oxidizing atmosphere to which the fluorine compound gas is added, the thermal oxide film is removed by etching, and a desired oxide film is formed on the surface of the substrate from which the thermal oxide film has been removed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a semiconductor device is formed. 4. The process for producing the fluorine compound gas is a semiconductor device of Claims preceding claim, characterized in that the NF _3.