JP2603982B2 - Multiprocessor coupling device for video signal processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to a digital video signal processing system used for broadcast signal processing equipment such as a broadcasting station, for example, for connecting a plurality of multiprocessors. The present invention relates to a multiprocessor combining device of a video signal processing system suitable for a computer.

(Prior Art) Generally, in a digital video signal processing system, individual processing units are created according to the purpose of processing a video signal.

The purpose of video signal processing is A, image quality correction: γ correction, color correction, noise reduction B, video effect: dissolve, super, wipe, image reduction, enlargement, rotation, chroma key C, video processing: luminance color separation, etc. Yes.

Conventionally, dedicated units are respectively created for performing the above-described signal processing, and a specific unit corresponds to one specific process. For this reason, as the type of the specific processing increases, the number of units also increases, and the whole apparatus becomes large. Accordingly, a great deal of labor is required for designing, maintaining, and constructing processing functions by combining units.

(Problems to be Solved by the Invention) As described above, the conventional apparatus requires a great deal of labor for design, maintenance, combination of units, and the like, and improvement of this point is desired. In particular, when combining independent units, the wiring work is laborious, and once wired, it is almost impossible to use the unit for other purposes of signal processing.

Furthermore, when a plurality of multiprocessors (arithmetic processing units) are used to cause each processor to share signal processing, the arithmetic operation of another processor may be performed after waiting for the arithmetic result from a specific processor. In such a case, a line for transmitting the operation result (flag) is required.
However, for this reason, it is wasteful to standardize the processors and to provide dedicated lines for each processor in the case where unused lines occur. When a flag is sent to another processor, the other processor requires a control circuit for determining the content of the flag.

Therefore, the present invention does not require a physical connection work according to the purpose of processing a video signal, can be freely and flexibly supported, is extremely flexible, and does not require an extra line between a plurality of arithmetic processing units. It is another object of the present invention to provide a multiprocessor combining device of a video signal processing system which is effective for standardizing each multiprocessor.

[Constitution of the Invention] (Means for Solving the Problems) The present invention relates to a plurality of programmable arithmetic processing units that receive a plurality of video inputs, perform an arithmetic processing on the inputs in accordance with a rewritable program, and derive a result thereof. Receiving the outputs of the plurality of programmable arithmetic processing units and a plurality of video inputs from the outside, and supplying this input to the plurality of programmable arithmetic processing units in a programmable manner;
And a network unit for outputting any input.
And it is provided in the programmable operation processing unit,
By switching and deriving at least two register outputs with a flag according to the result of the arithmetic processing unit, and returning the register output to the network unit as the output of the programmable arithmetic processing unit, the input data of another programmable arithmetic processing unit is obtained. It is provided with a means that can be treated as.

(Operation) By setting the processing contents (for example, multiplication, addition, comparison, etc.) of the programmable operation processing section by the above means, various video signal processing functions can be provided.
Moreover, since the connection order and form of the plurality of programmable arithmetic processing units can be set, a final output video signal that has passed through a plurality of video signal processing functions can be obtained comprehensively. The arithmetic processing unit is provided with a means for switching and deriving the register output by a flag, and the register output is used as it is as an input to the arithmetic processing unit, which is effective for standardizing each arithmetic processing unit. It is not necessary to newly provide a flag transmission path and a determination function, and efficient use is possible.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 (a) shows a basic configuration according to an embodiment of the present invention, and FIG. 1 (b) shows a use example of the present invention, for example, a construction example of a video synthesizing unit for performing super display.
The video signal processing system according to the present invention is configured as shown in FIG. 2, and one arithmetic processing unit in FIG. 2 is configured as shown in FIG.

In FIG. 1, for example, two video signals A2 and B2 are input to the calculation unit 33. The format of this video signal will be described with reference to FIG. The operation unit 33 compares the magnitudes of the two video signals A2 and B2, and outputs the comparison result as a flag. The flag is supplied to the control end of the switching unit 34. The switching unit 34 selects and derives one of the data in the registers 42 and 43 according to the content of the flag.

As shown in FIG. 1 (b), the operation unit 33 and the switching unit 34
The registers 42 and 43 are integrated into one arithmetic processing unit 21 (01) (to be described in detail in FIGS. 2 and 3).
The output of the switching unit 34 is derived as the output of the arithmetic processing unit 21 (01), and is output via the network unit 20 (described in FIGS. 2 and 3) to the similar arithmetic processing units 21 (02) and 21 (02). 03). The arithmetic processing units 21 (02) and 21 (03) operate as multipliers by the programmable switching. That is, the arithmetic processing unit 21 (02) multiplies the register output from the arithmetic processing unit 21 (01) by the video signal A2, and
Is the register output from the arithmetic processing unit 21 (01) and the video signal B2
Multiply by However, the arithmetic processing unit 21 (03) is
The register output from 21 (01) is inverted to perform multiplication processing.

With this construction, for example, the input video signal
When attempting to super-display a character signal given as an input video signal B2 to A2, the registers 42 and 43 store gain control data for each video signal when a character is inserted and when it is not. I just need.

At the timing of inserting a character, the flag becomes “1” because the level of the character signal is large. As a result, the multiplier of the register 42 is selected, and the arithmetic processing units 21 (02) and 21 (0
3) is supplied in the same way as a normal input. Arithmetic processing unit 21 (0
In 2), the level of the video signal A is reduced by the multiplier. In the arithmetic processing unit 21 (03), the multiplier is inverted and provided to the arithmetic unit, so that the character signal is emphasized. Since the flag becomes "0" after the character insertion period, the output of the register 43 is input to each of the arithmetic processing units 21 (02) and 21 (03), and only the video signal A2 is controlled to a predetermined level. Output.
The outputs of the arithmetic processing units 21 (02) and 21 (03) are also input to the arithmetic processing unit 21 (04) through the network unit 20.

As described above, in this embodiment, instead of sending a flag of a certain arithmetic processing unit to the next arithmetic processing unit, data itself is selected by the flag and sent to the next arithmetic processing unit. Therefore, all of the arithmetic processing units have a structure of two inputs and one output, and can be made uniform. Further, there is no need to judge the flag content in the next arithmetic processing unit.

In the above description, the character signal insertion processing has been described. However, the two video signals A2, B
When 2 is input, if the contents of the register are alternately varied in time, a video effect such as dissolve can be provided.

FIG. 2 is an embodiment showing the network unit 20 described above.

Two 17-bit external video signals A1 and B1 can be input to the network unit 20. In addition, a 17-bit input unit is prepared, and there are 32 in total.

The network unit 20 has a plurality (for example, 48 systems) of 17-bit output units. For example, two sets of the 17th to 48th output units are grouped together and each set is programmed by the programmable operation processing unit 21.
(01) to 21 (16). The outputs of the programmable operation processing units 21 (01) to 21 (16) are connected to, for example, the 17th to 32nd input units of the network unit 20, respectively. The network unit 20 is provided with an output unit for obtaining a final video output. A plurality of output units (for example, first to 16th) are provided, and can be connected to a similar network unit at the next stage.

Reference numeral 22 denotes a main control unit, which supplies a control signal to each control unit of the network unit 20 and the arithmetic processing units 21 (01) to 21 (16).

The input digital signal format handled by the above system is
As shown in FIG. 3B, the total is 17 bits, of which 1 bit is used as synchronization signal information, and the remaining bits are video signal data or synchronization signal data. When the synchronization signal information is “1”, the remaining 16 bits are the synchronization signal data, and when the synchronization signal information is “0”, the remaining 16 bits are the video signal data.

Further, the network unit 20 is configured by, for example, nine LSIs provided on one board, and a 17-bit input unit and an output unit are each assigned to each LSI by two bits,
Wiring connection to one LSI is facilitated. The network section 20 has a built-in network control section, and can switch its input / output connection system in a programmable manner according to a command from the main control section 22 or the arithmetic processing section.

FIG. 3 shows one of the arithmetic processing units, for example, 21 (01).

Depending on the control state, the network unit 20 sends a pair of the external video signals A1, B1 or the video signal fed back from another arithmetic processing unit to the arithmetic processing unit 21 (01) as a pair. 01) or only one video signal.

The arithmetic processing unit 21 (01) receives the video signals A2 and B2.
It has an input unit, and each input unit is connected to the synchronization separation units 31A and 31B. The synchronization signals separated by the synchronization separation units 31A and 31B are input to the sequencer 37 and used as a reference for determining the operation timing of the arithmetic processing unit 21 (01), or as a video signal.
Used for time adjustment of A2, B2.

The 16-bit video data separated by the sync separation units 31A and 31B can be input to the multiplication unit 32 and the calculation unit 33.
The multiplying unit 32 can multiply two video signals or multiply one video signal by a constant or a variable value. The arithmetic unit 33 can add, subtract, or compare two input video signals, add or subtract a certain value to one video signal, and perform comparison processing with a certain value.

The outputs obtained by the multiplication unit 32 and the calculation unit 33 can be further supplied to one input of each other, and also supplied to the switching unit 34.

The switching unit 34 selects and outputs one of the inputs, and the output is derived via the synchronization adding unit 35. The synchronization adding section 35 can add or stop a synchronization signal.

The arithmetic processing unit 21 (01) further includes a synchronization signal processing unit 3
6. An address generator 38 is provided. Further, a control memory 41 is built in along with the external program memory. The control memory 41 includes an arithmetic processing unit
21 (01) When each internal data processing unit performs its own assignment processing, a program unique to each data processing unit must be stored in advance so that all instructions do not need to be read from the program memory each time. Can be done.

FIG. 4 shows an example in which video signals are synthesized using the above system. In this case, the network unit 20 can obtain an output obtained by adding and synthesizing the external video signals A1 and B1 by setting the connection form of the arithmetic processing units 21 (01) to 21 (03) as shown in the figure. The video signal A1 is input to the multiplier of the arithmetic processing unit 21 (01) and multiplied by α, and the video signal B1 is input to the multiplier of the arithmetic processing unit 21 (02) and multiplied by (1−α). The output of each multiplier is input to the arithmetic processing unit 21 (03), and is added and processed by the arithmetic unit to be derived.

Network unit 20 and arithmetic processing units 21 (01) to 21 (16)
Can be switched to various forms according to the processing purpose.

FIG. 5 is a block diagram showing processing functions that can be realized by further combining the system shown in FIG. In this example, the processing unit 401 separates one composite video signal into luminance and color, and outputs the output color signal and the luminance signal to the next processing unit.
The matrix is derived at 402 to derive R, G, B signals. And
The R, G, and B signals are γ-corrected by the processing unit 403, and the resulting R, G, and B signals are
G and B signals are subjected to inverse matrix processing. Further, the luminance signal and the chrominance signal thus obtained are encoded by the processing unit 406 to obtain a composite video signal output.

FIG. 6 is an example in which a color correction system is realized using the system of FIG.

The input luminance signal Y 'and the chrominance signal C' are
It is supplied to the arithmetic processing units 21 (01), 21 (02) and 21 (03) through 20. Arithmetic processing unit 21 (01), 21 (02), 21 (03)
In the matrix operation is performed. Arithmetic processing unit 21 (0
2) and 21 (03) obtain an R 'signal and a B' signal, the operation processing unit 21 (01) obtains an R 'signal, and the R' signal is further processed by an operation processing unit 21 for matrix operation. (04). Here, matrix processing is performed on the (B'-Y ') signal, and as a result, a G' signal is obtained. The G ', R', and B 'signals are processed by an arithmetic processing unit 21 for color correction.
(05), 21 (06), and 21 (07). The G 'and R' signals which have been subjected to processing such as coefficient multiplication are processed by the arithmetic processing unit 21 (08).
The signal is converted into a luminance signal Y via 21 (09). Further, the luminance signal Y is output after its level has been adjusted by the arithmetic processing unit 21 (10). The arithmetic processing units 21 (11) and 21 (12) obtain a color difference signal (RY) signal and a (BY) signal using the luminance signal and the R signal, and the luminance signals Y and B, respectively. Can be Then, in the arithmetic processing units 21 (13) to 21 (16), the arrangement of the color signal (RY) signal and the (BY) signal and the hue adjustment are performed again, and the signals are passed through the filter 21 (17). Is derived. The basic structure of the filter 21 (17) is the same as that of the arithmetic processing unit.

The luminance signal Y 'and the chrominance signal C' have a data arrangement relationship as shown in FIG. 4B, and the color difference signals (R'-Y ') and (B'-Y') are shifted in time. Therefore, the first stage arithmetic processing units 21 (02) and 21 (03) take in input data every other cycle of one clock.

FIG. 7 shows a state in which the network unit 20 has been switched to obtain the above-described color correction system. FIG. 2, FIG.
The same parts as those in the drawings are denoted by the same reference numerals. If the number of arithmetic processing units is insufficient for one unit, another similar unit is used. In this embodiment, the network unit 20
The unit with (02) is used.

As described above, the present system can freely perform various kinds of video processing comprehensively by programming the connection form of the arithmetic processing unit by the network unit and the processing function of each arithmetic processing unit. When the functions as shown in FIG. 5 are realized, the functions can be further realized by combining and constructing an arithmetic processing unit having a plurality of network units. To realize a processing system like this,
The processing program may be written once from the host control unit into the control unit incorporated in each arithmetic processing unit and the network unit. When the processing purpose changes, the function can be freely changed by writing a predetermined program from the host control unit again, and the time is short.

[Effects of the Invention] As described above, the present invention provides an extremely flexible digital video signal processing system that does not require a physical connection operation according to the purpose of processing a video signal, is capable of responding freely in a programmable manner. Can be provided.

[Brief description of the drawings]

FIG. 1 is a structural explanatory view showing a main part of an embodiment of the present invention,
FIG. 2 (a) is a configuration explanatory view showing the entire device using the present invention, FIG. 2 (b) is a view showing a signal format, and FIG. 2 (c) is a view shown for further explaining a network unit. FIG. 3 is a block diagram showing the configuration of the arithmetic processing unit of FIG. 2, FIG. 4 is an explanatory diagram showing an example of a signal processing mode according to the present invention, and FIG. 5 shows an example of use of the system of the present invention. FIG. 6 is a block diagram for each function, FIG. 6 is an explanatory view showing an example of a signal processing form in a use example of the present invention, and FIG. 7 is a view showing a connection form of a connection circuit of FIG. 6 in a network unit. 20 Network section, 21 (01) to 21 (17) Calculation processing section, 22 Main control section, 31A, 31B Synchronization separation section, 3
2 Multiplier, 33 Calculation unit, 34 Switching unit, 35
Synchronization addition unit, 36 ... Synchronization signal processing unit, 37 ... Sequencer, 38 ... Address generation unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ryoichi Yajima 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Research Institute (72) Inventor Kiyomasa Kanai 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (72) Inventor Shigemi Mikami 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (72) Inventor Nobuyuki Sasaki 1 No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture In the Toshiba Komukai Plant (72) Koji Hoshino 1 in Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture In the Toshiba Komukai Plant (72) Inventor Kazuhiro Harukawa Komukai-Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa No. 1 Inside the Komukai Plant of Toshiba Corporation (56) References JP-A-60-31364 (JP, A) JP-A-61-61579 (JP, U)

Claims (1)

(57) [Claims] A plurality of programmable arithmetic processing units for receiving a plurality of video inputs, performing arithmetic processing on the input in accordance with a rewritable program, and deriving a result thereof; an output of the plurality of programmable arithmetic processing units; Receiving a plurality of video inputs from the CPU and programmatically supplying the inputs to the plurality of programmable arithmetic processing units, and a network unit for outputting any of the inputs; and a network unit provided in the programmable arithmetic processing unit. The output of at least two registers is switched and derived by a flag according to the result of the section, and the register output is fed back to the network section as the output of the programmable operation processing section so that it can be treated as input data of another programmable operation processing section. And a video signal processor. Multiprocessor coupling device of the system.