JP2604550B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bipolar transistor.

[0002]

2. Description of the Related Art A recent bipolar transistor generally has an external base region outside an intrinsic base region in order to reduce a base resistance.

FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.

[0004] As shown in FIG.
A field oxide film 2 comprising an N ⁺ type buried layer 12 and an N ⁻ type epitaxial layer 13 formed thereon and formed by selectively oxidizing the surface of the N ⁻ type epitaxial layer 13.
And a collector region 1 separated by a P ⁺ type buried layer 14 provided on the lower surface of field oxide film 2, a silicon oxide film 3 provided on the upper surface of collector region 1, and a P-type film formed on the upper surface of collector region 1. ^{A +} type external base region 15;
A P ⁻ type base (intrinsic base) region 4 provided on the upper surface of the collector region 1 connected to the external base region 15, an N ⁺ type emitter region 6 provided on the upper surface in the base region 4, and a silicon oxide film An emitter electrode 6, a base electrode 8, and a collector electrode 16 are respectively connected to the emitter region 6, the external base region 15, and the collector region 1 via the contact holes provided in the semiconductor device 3.

[0005]

In this conventional semiconductor device, it is necessary to form the external base region at a high concentration and deeply in order to reduce the base resistance.

When the external base region is formed at a high concentration and deep, the lateral expansion is correspondingly increased, and the area occupied by the external base region is increased, so that there is a problem that miniaturization of the element is limited. .

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A base region of the opposite conductivity type formed on the surface of the collector region of one conductivity type; an opening provided in the collector region including an end of the base region to expose a side surface of the base region; and a side surface of the base region A base electrode that forms an ohmic contact with the base region by bonding to the base region; and an emitter region formed on a surface in the base region.

[0008]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 1A, an N ⁺ -type buried layer and an N ^-- type epitaxial layer are sequentially formed on a P-type silicon substrate (not shown), and the surface is selectively oxidized. An N-isolated element is separated by a field oxide film 2 of about 1 μm and a P ⁺ -type diffusion layer provided on the N ⁻ -type epitaxial layer.
A silicon oxide film 3 having a thickness of 50 nm is formed on the surface of the collector region 1 of the mold. Next, acceleration energy 30 keV,
Boron ions are selectively implanted into the upper surface of the collector region 1 through the silicon oxide film 3 under the condition of a dose amount of 5 × 10 ¹³ cm ⁻² , annealing is performed at a temperature of 900 ° C. for 30 minutes, and the junction depth is reduced to about 0. A 3 μm P ⁻ -type base region 4 is formed.

Next, as shown in FIG. 1B, the surface of the collector region 1 including the end of the base region 4 is etched to a depth of 0.2 to 0.25 μm by reactive ion etching to form an opening. A portion 5 is formed to expose a side surface of the base region 4 and an upper surface of the collector region 1.

Next, as shown in FIG. 1C, the side surface of the exposed base region 4 and the upper surface of the collector region 1 are thermally oxidized to form a silicon oxide film 3a, and the acceleration energy 5
Arsenic ions are selectively implanted into the upper surface of the base region 4 through the silicon oxide film 3 under the conditions of 0 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , and annealing is performed at a temperature of 950 ° C. for 50 minutes to form an N ⁺ type emitter. A region 6 is formed.

Next, as shown in FIG. 1D, the silicon oxide films 3, 3a are selectively etched to form a base region 4.
And a contact hole for the emitter region 5, and an Al film or Al /
A TiN / Ti laminated film is deposited and patterned to form each of the emitter electrode 7 and the base electrode 8. In order to form an ohmic contact between the base region 4 and the base electrode 8 made of Al, boron ions are applied to the exposed side surfaces of the base region 4 at an acceleration energy of 30 keV and at an acceleration energy of 30 keV.
The P ⁺ -type contact layer 9 may be formed by ion implantation under the conditions of a dose of 5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² .

Before the formation of the contact holes, a silicon oxide film, a silicon nitride film, a PSG film, or the like may be deposited on the surface including the silicon oxide films 3 and 3a by the CVD method.

[0015]

As described above, according to the present invention, a base electrode to be joined to a side surface of a base region exposed from an opening formed by etching the upper surface of a contact region including an end of the base region is formed. Accordingly, the base electrode can be connected without increasing the base resistance, so that the area occupied by the external base region in the conventional example can be reduced, and the element can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Collector region 2 Field oxide film 3, 3a Silicon oxide film 4 Base region 5 Opening 6 Emitter region 7 Emitter electrode 8 Base electrode 9 P ⁺ type contact layer 11 P type silicon substrate 12 N ⁺ type buried layer 13 N ^- epitaxial Layer 14 P ⁺ buried layer 15 External base region 16 Collector electrode

Claims (1)

(57) [Claims] 1. An opposite conductivity type base region formed on a surface of a collector region of one conductivity type; an opening provided in the collector region including an end of the base region to expose a side surface of the base region; A semiconductor device comprising: a base electrode that is joined to a side surface of the base region to form an ohmic contact with the base region; and an emitter region that is formed on a surface in the base region.