JP2604644B2 - External master clock abnormality detection circuit of clock device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external master clock abnormality detecting circuit of a clock device used in a system such as a digital private branch exchange, and more particularly, to an internal system clock synchronized with an external master clock. The present invention relates to an external master clock abnormality detection circuit of a clock device that generates an error.

[0002]

2. Description of the Related Art FIG. 15 is a block diagram showing the configuration of a conventional general slave clock system. An external master clock EMC is input to the clock device 1.
External master clock EMC is PLO (Phase-Locked Oscilla
tor) circuit 2 is provided to a VCXO (voltage controlled crystal oscillator) 3 built in the circuit 2, and the VCXO 3 is an external master clock.
Generate internal system clock ISC based on EMC.
This internal system clock ISC is supplied as an internal clock to a system such as a digital private branch exchange.

[0003]

In such a conventional clock device 1, when the external master clock EMC exceeds the frequency tracking range of the VCXO 3, the external master clock EMC and the internal system clock ISC are asynchronous. State. Further, even when the external master clock EMC is within the tracking range of the VCXO 3, the phase fluctuation or clock instantaneous change may occur due to a change in the environment surrounding the distribution path of the external master clock EMC to the clock device 1 or a failure in the transmission device. Disconnection can occur.

Since such an abnormality in the external master clock EMC interferes with the normal operation of the system to which the external master clock EMC is supplied, for example, a digital private branch exchange, it is necessary to monitor the state of the external master clock EMC to detect the abnormality. There is. The present invention has been made in view of such circumstances, and provides an external master clock abnormality detection circuit of a clock device that can quickly detect an abnormality in an external master clock EMC and generate an alarm when an abnormality occurs in the external master clock EMC. With the goal.

[0005]

FIG. 1 is a block diagram showing the basic configuration of an external master clock abnormality detection circuit according to the present invention.

In FIG. 1, an external master clock EMC as an input clock is supplied to a PLO circuit 2 and an external master clock.
It is provided to the phase comparator 41 of the clock fluctuation detecting section 4. Together with the internal system clock ISC is the output clock of the PLO circuit 2 is supplied to the system such as is not shown for example a digital private branch exchange, external master
It is provided to the phase comparator 41 and the flip-flop 42 of the clock fluctuation detecting section 4.

The external master clock fluctuation detecting section 4 is provided with the phase comparator 41 and the flip-flop 42 as described above, and the phase comparator 41 uses an exclusive OR (EXOR) circuit. The clock terminal CK of the flip-flop 42 receives the internal system clock ISC, the data terminal D receives the output (EXOR output) of the phase comparator 41, and the reset terminal R
Is supplied with a reset signal RS. In addition,
The output signal from the output terminal Q of the flip-flop 42 is given to the counting section 5.

The counting section 5 is provided with the flip-flop 42
The number of times that the level of the output signal from the output terminal Q changes from low level to high level is counted, and the count value is output to the number comparison section 6. The counting unit 5
Is also supplied with a reset signal RS.

[0009] The number-of-times comparing section 6 is supplied with the output of the count value of the above-mentioned counting section 5 and a preset number-of-times setting value SN, and outputs the comparison result to the alarm sending section 7.

The alarm sending section 7 receives the output of the comparison result of the number comparing section 6 and outputs an alarm signal when they match.
Output AS.

[0011]

FIG. 2 shows the external master clock EMC, the internal system clock ISC, the output signal of the phase comparator 41 and the flip-flop 42 of the external master clock abnormality detecting circuit of the present invention shown in the block diagram of FIG. Output terminal Q
5 is a time chart showing the waveform of an output signal from the external master clock EMC and the internal system clock ISC.

In the time chart of FIG. 2, the external master clock EMC shown in FIG. 2A and the internal system clock ISC shown in FIG. 2B are in a synchronized state. The phase difference φ is kept constant.

The internal system clock ISC is normally output due to the free-running frequency of the VCXO3. When the phase difference between the internal system clock ISC and the external master clock EMC is calculated by the phase comparator 41 with reference to the internal system clock ISC, FIG. As shown, in the synchronous state, a state of only a phase advance or a phase delay of a constant width is maintained. Accordingly, the flip-flop 42 latches the level of the output of the phase comparator 41 at the rising edge of the internal system clock ISC input to the clock terminal CK and outputs it as an output signal from the output terminal Q. As shown in (1), the output signal from the output terminal Q of the flip-flop 42 always maintains the high level.

On the other hand, FIG. 3 shows an external master clock EMC, an internal system clock ISC, and a phase comparator 41 as in FIG.
5 is a time chart showing the waveforms of the output signal of the flip-flop 42 and the output signal from the output terminal Q of the flip-flop 42, in which the external master clock EMC and the internal system clock ISC are not synchronized.

In the time chart of FIG. 3, the external master clock EMC shown in FIG. 3A is not synchronized with the internal system clock ISC shown in FIG. 3B. The phase difference is undefined.

As in the case of FIG. 2, when the phase difference between the external master clock EMC and the external master clock EMC is determined by the phase comparator 41 with reference to the internal system clock ISC, as shown in FIG. Indicates that the state of phase advance and the state of phase delay are mixed. Therefore, flip-flop 42
As shown in FIG. 3 (d), the output signal from the output terminal Q changes in level when phase advance and phase delay occur alternately.

As described above, the external master clock abnormality detection circuit of the present invention uses the number of times of level change of the output signal from the output terminal Q of the flip-flop 42 when the external master clock EMC and the internal system clock ISC are not synchronized. Is counted, and when it exceeds a predetermined value, for example, the permissible value of the number of abnormal occurrences of the external master clock EMC of the system, an alarm signal AS is generated from the alarm sending section 7.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 4 is a circuit diagram showing a configuration example of a specific embodiment of the external master clock abnormality detection circuit of the present invention.

In FIG. 4, an external master clock EMC which is an input clock is supplied to a PLO circuit 2 and an external master clock.
A clock terminal CK of a flip-flop (FF) 44 constituting the phase comparator 41 of the clock fluctuation detecting section 4 is provided. Also
Internal system clock which is the output clock of PLO circuit 2
The ISC is supplied to a system such as a digital private branch exchange (not shown ),
The clock terminal CK of the flip-flop (FF) 43 constituting the phase comparator 41 of the lock fluctuation detecting section 4 and the external master clock
This is supplied to a flip-flop (FF) 42 of the clock fluctuation detecting unit 4.

The external master clock fluctuation detecting section 4 is provided with the phase comparator 41 and the flip-flop 42 as described above, and the phase comparator 41 is composed of the two flip-flops 43 and 44 and the two-input EXOR gate. It is composed of 45.
These flip-flops 43 and 44 divide the frequency of the internal system clock ISC and the external master clock EMC by そ れ ぞ れ, and input them to both inputs of the EXOR gate 45.
The EXOR gate 45 has both inputs, that is, both flip-flops 43 and 44.
, The phase difference between the internal system clock ISC and the external master clock EMC is detected, and the result is output to the flip-flop 42. Note that a reset signal RS is supplied to the reset terminals R of the flip-flops 43 and 44.

The internal system clock ISC is input to the clock terminal CK of the flip-flop 42, and the output of the EXOR gate 45, which is the output (EXOR output) of the phase comparator 41, is input to the data terminal D as described above. , And latches the level of the output signal of the EXOR gate 45 in synchronization with the internal system clock ISC. Further, a reset signal RS is given to a reset terminal R of the flip-flop 42. The output signal from the output terminal Q of the flip-flop 42 is given to the counting section 5.

The counting section 5 are both Q _A, Q _B, the Q _C, Q _D 4
It is composed of two counters 51 and 52 having bit outputs, counts the number of times the output signal from the output terminal Q of the above-mentioned flip-flop 42 changes from low level to high level, and compares the count values. The signal is output to an 8-bit input selector 61 which is the unit 6. Note that both counters
The reset signal RS is also applied to the 51 and 52 reset terminals CLR.
Is given.

The number-of-times comparing section 6 is specifically composed of an 8-bit input of bits 0 to 7 and a 3-bit input of bits A to C.
It comprises a selector 61 for comparing with a bit code input. 8 of bits 0 to 7 of the selector 61
The 4-bit output of each of the counters 51 and 52, which is the output of the count value of the above-described counting unit 5, is input to the bit input, and the number of detections of the 3-bit output is set to the 3-bit code input of bits A to C. A preset number of times SN set by the switch 8 is input, and when the comparison results match, a high-level signal is output from the output terminal W to the alarm sending unit 7.

The alarm sending section 7 is specifically composed of a flip-flop (FF) 71, and the output of the comparison result of the number comparing section 6 is input to the set terminal S of the flip-flop 71. Accordingly, when the output signal of the number comparison unit 6 changes to high level, the flip-flop 71 of the alarm transmission unit 7 sets the alarm signal AS, which is the output signal, to high level. The flip-flop 71 of the alarm sending section 7
The reset signal RS similar to that described above is supplied to the reset terminal R of.

FIG. 5 is a time chart showing the waveforms of the signals at various parts of the external master clock abnormality detection circuit of the present invention shown in the block diagram of FIG. 4 described above, and shows the relationship between the external master clock EMC and the internal system clock ISC. This shows a state in which synchronization is established.

In the time chart of FIG. 5, the external master clock EMC shown in FIG. 5A and the internal system clock ISC shown in FIG. The phase difference φ is kept constant while the master clock EMC has a phase delay with respect to the internal system clock ISC.

FIG. 5 (c) shows the output of the flip-flop 44, which is supplied with the external master clock EMC shown in FIG. 5 (a).
FIG. 5D shows the output of the flip-flop 43, which is a waveform obtained by dividing the internal system clock ISC shown in FIG. 5B by 1/2. Has become.
Therefore, the output signal of the EXOR gate 45 becomes a high-level signal corresponding to the phase difference between the two, as shown in FIG.

Since the flip-flop 42 latches the output signal of the EXOR gate 45 in synchronization with the rising edge of the internal system clock ISC, the output signal from the output terminal Q is shown in FIG. 5 (f). Thus, the low level is maintained. Therefore, the outputs of Q _A and Q _B of the lower counter 51 shown in FIGS. 5 (g) and 5 (h), respectively, both maintain the low level (“0”). The alarm signal AS which is the output signal of the flip-flop 71 of the alarm sending section 7 shown in (i) also maintains the low level.

On the other hand, FIGS. 6, 7, 8, 9, 10 and 11 are time charts showing the case where the external master clock EMC goes out of the frequency tracking range of the PLO circuit 2 and becomes asynchronous. . 6, 7, 8, 9, 10
11 and FIG. 11 show that when an internal system clock ISC which is an output clock of the PLO circuit 2 is used as a trigger and observed by an oscilloscope, an external master clock EMC which is an input clock of the PLO circuit 2 flows without stopping on a screen of the oscilloscope. 6, FIG. 7, FIG. 8, FIG. 9, and FIG.
10 and FIG. 11 are waveforms displayed on the oscilloscope screen at a certain moment, and the time axis changes in the order of the figure numbers.

In the time charts of FIGS. 6, 7, 8, 9, 10 and 11, the external master clock EMC shown in each figure (a) and each figure (b) are shown. The state is not synchronized with the internal system clock ISC, and the phase difference is indefinite as can be seen from the output of the EXOR gate 45 shown in FIG. In such a case, for example, as shown in FIG. 8, FIG. 9, FIG. 10 and FIG.
When the output of the gate 45 is at the high level, a state occurs in which the internal system clock ISC changes to the high level, and the level of the output signal of the flip-flop 42 changes from the low level to the high level. The change in the level of the output signal of the flip-flop 42 is counted by both counters 51 and 52 of the counting section 5. Is set to alarm signal
AS turns to high level.

The time chart of FIG. 12 shows a state in which the external master clock EMC shown in FIG. 12A is synchronized with the internal system clock ISC shown in FIG. 12B. This shows a case where the PLO circuit 2 cannot completely follow the jitter or wander of the external master clock EMC which is the input clock, and the phase difference φ fluctuates with time.

In this case as well, the EX shown in FIG.
During the period when the output signal of the OR gate 45 is at the high level, FIG.
The state where the internal system clock ISC rises to the high level shown in FIG. 12B occurs, and as a result, the output signal level of the flip-flop 42 shown in FIG. 12F changes. Therefore, as shown in FIGS. 12 (g) and 12 (h), the output of the count values of both counters 51 and 52 of the counting section 5 changes.
As shown in FIG. 12 (i), when the number reaches the number set by the number-of-times-of-detection setting switch 8, the alarm sending section 7 outputs a high-level alarm signal AS.

The time chart of FIG. 13 shows a state in which the external master clock EMC shown in FIG. 13A is synchronized with the internal system clock ISC shown in FIG. 13B. This shows a case where an instantaneous interruption occurs at a position indicated by BP in the external master clock EMC which is an input clock.

In this case as well, the EX shown in FIG.
During the period when the output signal of the OR gate 45 is at the high level, FIG.
The state where the internal system clock ISC rises to the high level shown in FIG. 13B occurs, and as a result, the output signal level of the flip-flop 42 shown in FIG. 13F changes. Therefore, as shown in FIGS. 13 (g) and (h), the count value output of both counters 51 and 52 of the counting section 5 changes, and when this reaches the number set by the detection number setting switch 8, FIG. As shown in (i), a high-level alarm signal AS is output from the alarm sending section 7.

FIG. 14 is a block diagram showing a configuration example in which the external master clock abnormality detection circuit of the present invention as described above is incorporated in a clock device in a system such as a digital private branch exchange.

In this configuration example, the external master clock EM
C # 0 and # 1 are fed into the system from the external clock transmission device 70, and they are connected to the selector of the clock device 50.
One of them is selected as an input clock and input to the PLO circuit 2 and the external master clock abnormality detection circuit 52 of the present invention. The alarm signal AS, which is the output signal of the external master clock abnormality detection circuit 52 of the present invention, is output to the processor bus 56 after being held in the STR (status register) 53.

The clock device 50 is provided with a CTR (control register) 54, and various instructions from an MPR (management processor) 58 of the control device 57 are given via a processor bus 56. The CTR 54 is provided to the external master clock abnormality detection circuit 52 of the present invention by setting the number setting value SN by the number-of-detection setting switch 8, resetting by giving a reset signal RS, and controlling two external systems by controlling the selector 51. Controls input switching of the master clock EMC, etc.

Note that the reset signal RS from the CTR 54 is combined with the power-on-clear signal POC at the same time as the OR gate 55 (negative logic).
External master clock abnormality detection circuit 52 of the present invention
Has been given to. The power-on clear signal POC is a signal for clearing the external master clock abnormality detection circuit 52 of the present invention to an initial state when the entire clock device incorporating the external master clock abnormality detection circuit 52 of the present invention is powered on. And transmitted from the power-on-clear circuit 60.

For example, if "0" is set to the input switching bit of the CTR 54, the selector 51 selects # 0 of the two systems as the external master clock EMC and sets
It is input to the LO circuit 2 and the external master clock abnormality detection circuit 52 of the present invention. In this case, the internal system clock ISC
Follows the external master clock EMC # 0.

When an abnormality occurs in the external master clock EMC # 0, the external master clock abnormality detection circuit 52 of the present invention detects the abnormality as described above and outputs an alarm signal AS
Is output to STR53. The alarm signal AS output in this manner is transmitted to the control device via the STR 53 and the processor bus 56.
57 is input to MPR58. When the alarm signal AS is input, the MPR 58 rewrites the input switching bit of the CTR 54 to "1". As a result, the selector 51 selects the # 1 of the two external master clocks EMC # 1 and # 2 and supplies the selected # 1 to the PLO circuit 2 and the external master clock abnormality detection circuit 52 of the present invention.

The reset bit of the CTR 54 is used for resetting the external master clock abnormality detecting circuit 52 of the present invention as described above. More specifically, the reset bit is continuous when the external master clock EMC is monitored for a certain period. The presence or absence of the alarm signal AS is stored for each of the three periods, and the alarm signal AS is determined by a majority decision in the three periods.
It is also possible to temporally perform software control of the external master clock abnormality detection circuit 52 of the present invention by employing a method of determining the presence / absence of the error.

The number-of-times setting bit of the CTR 54 is provided for controlling detection accuracy in order to cope with various changes of the external master clock EMC due to environmental changes such as temperature or radio wave environment. By adopting software control as in the example, automatic adjustment can be performed without manual intervention.

[0043]

As described in detail above, according to the present invention, it is possible to easily detect an abnormality of an external master clock supplied to the system, and to provide a system having a clock device employing a slave synchronization system. Reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an external master clock abnormality detection circuit according to the present invention.

FIG. 2 is a time chart of the basic configuration of the circuit of the present invention when the external master clock and the internal system clock are synchronized.

FIG. 3 is a time chart of the basic configuration of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 4 is a circuit diagram showing a configuration example of a specific embodiment of the external master clock abnormality detection circuit of the present invention.

FIG. 5 is a time chart of the embodiment of the circuit of the present invention when the external master clock and the internal system clock are synchronized.

FIG. 6 is a time chart of the embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 7 is a time chart of the embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 8 is a time chart of the embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 9 is a time chart of the embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 10 is a time chart of the embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 11 is a time chart of the embodiment of the circuit of the present invention when the external master clock and the internal system clock are not synchronized.

FIG. 12 is a time chart of the embodiment of the circuit of the present invention when the external master clock has jitter or wander.

FIG. 13 is a time chart of the embodiment of the circuit of the present invention when an instantaneous interruption occurs in the external master clock.

FIG. 14 is a block diagram showing a configuration example in which an external master clock abnormality detection circuit of the present invention is incorporated in a clock in a system.

FIG. 15 is a block diagram showing a configuration of a conventional general slave synchronization type clock device.

[Explanation of symbols]

1 Clock device 4 External master clock fluctuation detecting unit 5 Counting unit 6 Number comparing unit 7 Alarm sending unit EMC External master clock ISC Internal system clock AS Alarm signal

Claims (1)

(57) [Claims] 1. A external master clock to the slave synchronization method for generating an internal system clock to slave synchronization clock <br/> instrumentation external master clock abnormality detection circuit of location, the external master clock and the internal system clock
Is compared with the phase comparator, and the phase difference output is
Latch in flip-flop with system clock
External master clock to the internal system clock.
An external master clock change that detects the occurrence of a lock change
Comparison to compare the motion detecting unit, a counting unit for counting the number of times of detection by the external master clock variation detection unit, a predetermined value a count value according to the count unit
And parts, the comparison unit in accordance comparison result, and characterized in that the count value by the counting unit is equipped with an alarm sending unit for <br/> output the No. alarm signal when the said predetermined value or more External clock abnormality detection circuit of the clock device.