JP2605481B2 - Clock disconnection detection circuit for device group - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a clock loss occurring in a device group consisting of a plurality of devices operating based on one clock.

[Conventional technology]

FIG. 2 shows an example of this kind of conventional clock loss detection circuit. This circuit is provided in a device group including devices 206 and 207. The devices 206 and 207 are specifically packages forming a transmission device for performing digital communication, for example. Then, the input terminal 206a of the apparatus 206 master clock c of frequency f ₀ is input, the clock is output to the device 207 from the output terminal 206b through the internal wiring of the device 206. The device 206 is provided with a one-shot multivibrator 201 that outputs a low-level pulse having a time width determined by the time constant of the resistor R and the capacitor C, triggered by a clock input to the input terminal 206a. The output of the multivibrator 201 is output to the control unit 202 and also to the device 207 via the signal line 203.

The input terminal 207a of the device 207 is connected to the output terminal 206b of the device 206, and the clock input from the input terminal 207a is output from the output terminal 207b through the internal wiring. apparatus
207 is provided with a one-shot multivibrator 213 which is triggered by a clock input to the input terminal 207a and outputs a low-level pulse having a time width determined by the time constants of the resistor R and the capacitor C. The output of the multivibrator 213 is input to one input terminal of the AND circuit 204. The output of the multivibrator 201 input through the signal line 203 is input to the inversion circuit 212, and the output is input to the other input terminal of the AND circuit 204. The output of the AND circuit 204 is input to the control unit 202.

The control unit 202 recognizes that a clock break has occurred in the device 206 when a high-level signal is input from the device 206, and recognizes that the clock has occurred in the device 206 when a high-level signal is input from the device 207.
Recognizes that a clock break has occurred.

Here, for example, if a clock loss occurs in the device 206, the multivibrator 201 is not triggered by the clock, and as a result, the multivibrator 201 uses the high-level logic signal as the clock loss detection signal as the control unit 202 and the device 207. Is output to the inversion circuit 212. The inverting circuit 212 thereby outputs a low-level signal.
At this time, since no clock is input to the device 207, the multivibrator 213 also outputs a high-level logic signal. However, since a low-level signal is supplied to the other input terminal of the AND circuit 204 from the inverting circuit 212, a high-level signal from the multivibrator 213 is blocked by the AND gate 204 and sent to the control unit 202. Is not given. As a result, the control unit 202 recognizes that a clock interruption has occurred in the device 206.

[Problems to be solved by the invention]

However, in such a conventional clock loss detection circuit, when a clock loss occurs in the device 206 and at that time, a clock loss also occurs in the device 207, the multivibrator
The high-level signal indicating the occurrence of the clock interruption generated by the signal 213 is blocked by the AND gate 204. That is, when the clock disconnection occurs in a plurality of devices at the same time, the control unit 202 is not notified of the clock disconnection occurring in the downstream device.

When the signal line 203 that transmits the clock disconnection detection signal of the upstream device 206 to the downstream device 207 is disconnected, the inverting circuit
The input of 212 is at a high level and therefore the output is at a low level, and one input of the AND circuit 204 is at a low level. Therefore, when the clock is cut off, the multivibrator 213
Is always blocked by the AND circuit 204, making it impossible for the device 207 to detect a clock cut.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, detect a clock loss in a plurality of devices, and detect a clock loss detection signal output from an upstream device to a downstream device. It is an object of the present invention to provide a clock disconnection detection circuit of a device group which solves the problem that the disconnection of the line makes the detection of the clock disconnection impossible due to the disconnection.

[Means for solving the problem]

The present invention relates to a clock disconnection detection circuit in which a master clock of the same frequency is supplied in series over two or more packages, and an oscillator that outputs a transmission output different from the master clock to a specific package among the packages; A changeover switch for switching the output of
A detecting unit for detecting the disconnection of the master clock in the specific package, and switching the switch according to the disconnection detection signal of the master clock to supply the clock signal of the oscillator to a package downstream from the specific package and receive the signal to the package Frequency identification means for identifying the frequency of the clock signal to be generated.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock disconnection detection circuit according to the present invention. This circuit is provided in a device group including the devices 106 and 107. The devices 106 and 107 are specifically packages forming a transmission device for performing digital communication, for example. Then, the master clock c of frequency f ₀ is input to the input terminal 106a of the apparatus 106, the clock transmission circuit 1 this clock to internal wiring and below the device 106
The signal is output from the output terminal 106b to the device 107 through the terminal 09. The device 106 includes a one-shot multivibrator 101 that is triggered by a clock input to the input terminal 106a and outputs a low-level pulse having a time width determined by the time constant of the resistor R and the capacitor C. When the clock is cut off and no clock is input, the multivibrator 101 uses the high-level logic signal as a clock cutoff detection signal to control section 102 and clock sending circuit 109.
And output to Oscillator 108 generates a different frequency f ₁ clock and the master clock c, the clock transmission circuit 10
Output to 9. The clock transmission circuit 109 outputs the clock from the input terminal 106a to the output terminal 106b, and outputs the clock from the oscillator to the output terminal when the multivibrator 101 outputs the clock disconnection detection signal.

The input terminal 107a of the device 107 is connected to the output terminal 106b of the device 106, and the clock input from the input terminal 107a is output from the output terminal 107b through the internal wiring. apparatus
The 107 is provided with a one-shot multivibrator 113 that outputs a low-level pulse having a time width determined by the time constant of the resistor R and the capacitor C, triggered by a clock input to the input terminal 107a. When the clock is cut off and no clock is input, the multivibrator 113 outputs a high-level logic signal to the control unit 102 and the OR circuit 112 as a clock cutoff detection signal. Frequency identification circuit 110 is for identifying the frequency of the input from the input terminal 107a clock, when the frequency of the clock is different from the frequency f ₀ of the master clock outputs a high level signal to the OR circuit 112. Malfunction prevention circuit 11
When a clock loss occurs in the device 107, or when a clock loss occurs in the device 106 and a clock having a frequency different from the master clock is input, the device 10
7 is a circuit to prevent malfunctions.
When a high-level signal is supplied from, a predetermined operation necessary for preventing malfunction is performed.

The control unit 102 recognizes that a clock interruption has occurred in the device 106 when a high-level signal is input from the device 106,
When a high level signal is input from the device 107, the device 1
At 07, it is recognized that a clock break has occurred.

Next, the operation will be described. First, when a clock loss occurs in the device 106 and the clock is not input to the multivibrator 101, the multivibrator 101 is not triggered, and outputs a high-level clock loss detection signal to the control unit 102.
The signal is output to the clock transmission circuit 109. Clock sending circuit 1
09 thereby outputs a clock of a frequency f ₁ that the oscillator 108 is output to the output terminal 106b. This clock is
Is supplied to the multivibrator 113 through the input terminal 107a of the, the multivibrator 113 is triggered, and therefore does not output the clock loss detection signal. as a result,
Since a high-level clock loss detection signal is input to the control unit 102 only from the device 106, the control unit 102 recognizes that a clock loss has occurred in the device 106.

At this time, the frequency identification circuit 110 determines that the clock frequency is f
_Since it is ₁ , a high-level signal is output, which is input to the malfunction prevention circuit 111 through the OR circuit 112. Then, the malfunction prevention circuit 111 performs a predetermined operation in order to prevent a malfunction due to no input of the master clock.

Next, when a clock interruption occurs in the device 107, the multivibrator 113 outputs a high-level clock interruption detection signal to the control unit 102 and the OR circuit 112. Meanwhile, the device
Since 106 multivibrators 101 are triggered by the master clock and do not output a clock loss detection signal,
The control unit 102 recognizes that a clock interruption has occurred in the device 107.

At this time, since the high-level signal output from the multivibrator 113 is also input to the malfunction prevention circuit 111 through the OR circuit 112, the malfunction prevention circuit 111 performs a predetermined operation in order to prevent malfunction due to the absence of the master clock. The operation is performed.

Next, when the clock disconnection occurs simultaneously in both the devices 106 and 107, first in the device 106, the multivibrator 101 outputs the clock disconnection detection signal to the control unit 102 and the clock transmission circuit 109 as described above. In 107, the multivibrator 113 sends the clock disconnection detection signal to the control unit 102,
Output to the OR circuit 112. That is, in this case, since the clock loss detection signal is output from both devices 106 and 107, control unit 102 recognizes that the clock loss has occurred in both devices.

At this time, the high-level signal output from the multivibrator 113 is output to the malfunction prevention circuit 1 through the OR circuit 112.
Since it is also input to 11, the malfunction prevention circuit 111 performs a predetermined operation in order to prevent a malfunction due to no master clock being input.

As described above, the clock disconnection detection circuit of the device group of the present invention can detect each clock disconnection even when the clock disconnection occurs in two devices at the same time, and outputs the clock disconnection detection signal output from the upstream device to the downstream device. Since a dedicated signal line for transmitting the clock signal is not used, the problem that the disconnection does not hinder the detection of the clock disconnection does not occur.

In this embodiment, two devices 106 and 107 have been described. However, the number of devices is not limited to two.
The present invention can be applied even when three or more devices are connected. For example, when another device is connected downstream of the device 107, an oscillator 108 and a clock transmission circuit 109 provided in the device 106 are added to the device 107, and a device downstream of the device 107 is connected to the device 107. Multivibrator 1
13 and a frequency identification circuit 11 to prevent malfunction.
0, the OR circuit 112, and the malfunction prevention circuit 111 may be provided.

〔The invention's effect〕

As described above, in the clock disconnection detection circuit of the device group of the present invention, when a clock disconnection occurs in the upstream device, the clock from the oscillator provided in that device is supplied to the downstream device instead. Therefore, the downstream device can detect the clock interruption by this clock. Therefore, even if clock cuts occur in a plurality of devices at the same time, they can be detected.

Further, since a dedicated signal line for transmitting the clock loss detection signal output from the upstream device to the downstream side is not used, there is no problem that the disconnection hinders the detection of the clock loss unlike the related art. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a clock loss detection circuit of a device group according to the present invention, and FIG. 2 is a block diagram showing an example of a clock loss detection circuit of a conventional device group. 101,113 one-shot multivibrator 102 control unit 106,107 device 106a, 107a input terminal 106b, 107b output terminal 108 oscillator 109 clock transmission circuit 110 frequency identification circuit 111 malfunction Prevention circuit 112 …… OR circuit

Claims (1)

(57) [Claims] 1. A clock disconnection detection circuit to which a master clock of the same frequency is supplied in series over two or more packages, comprising: an oscillator outputting a transmission output different from the master clock to a specific package among the packages; A changeover switch for switching the output of the oscillator; a detection unit for detecting the disconnection of the master clock in the specific package; and a switch downstream of the specific package by switching the changeover switch in accordance with the master clock disconnection detection signal. And a frequency identification means for supplying a clock signal of the oscillator to the package and identifying a frequency of the clock signal to be received by the package.