JP2605664B2 - Small electronic calculator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a small electronic computer having a screen editor function.

[Prior art and its problems] Conventionally, in a small-sized electronic computer having a screen editor function, that is, a function of correcting data in units of logical lines (continuous data lines), it is necessary to go to a place where data is already displayed. When new data is input and calculation is performed, the calculation result is displayed on the next line.If data longer than the calculation result is displayed on the line where the calculation result is displayed, the calculation result is displayed. There is a problem that the calculation results are not displayed correctly due to overlapping.

[Object of the Invention] In the present invention, an arithmetic expression and an arithmetic result expression can be displayed by fully using a display unit capable of displaying a plurality of lines, and display data longer than the arithmetic result is already displayed on a line where the arithmetic result is displayed. It is an object of the present invention to provide a small-sized electronic computer capable of correctly displaying calculation result data even when it is displayed.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a case where the present invention is applied to a small electronic calculator having a display unit of 4 rows × 16 columns. In the figure, reference numeral 10 denotes a key input unit, which is a numerical key 1, an operation key 2, an EXE key 3 for instructing execution of an operation, an EDIT key 4 for specifying a screen editor function, and a cursor key for instructing left, right, up and down cursor movement. 5a to 5d are provided. The data input from the key input unit 10 is sent to the control unit 11. The control unit 11 stores an RO that stores various control data.
The main unit M is configured to operate in accordance with input data from the key input unit 10 to control operation of each circuit unit. That is, the control unit 11 performs address designation and data transmission / reception to the data storage unit 12 via the address bus AB1 and the data bus DB1, and the control unit 11
While inputting the operation signal of IT key 4 to AND circuit 13,
An operation command signal for the operation of the EXE key 3 is input to the set terminal S of the flip-flop 14, the reset terminal R of the flip-flop 15 and the operation unit 16, and a key input signal other than the EDIT key 4 is input to the reset terminal R of the flip-flop 14. To enter. The output signal of the flip-flop 14 is input to the set terminal S of the flip-flop 15 via the AND circuit 13, and the output signal of the flip-flop 15 is sent to the control unit 11 as an operation end signal. The control unit 11
Transmits / receives data to / from the operation unit 16 via the data bus DB2, and inputs the operation data input by key to the input buffer 17 via the data bus DB3. Then, the data held in the input buffer 17 is sent to the data storage unit 12 and the display data storage unit 18 via the data bus DB4. This display data storage unit 18
For example, it has a capacity capable of storing display data of 8 rows × 16 digits, and the storage data is stored in a data judgment unit as needed.
19, it is determined whether or not “null” is present, and the determination result is sent to the control unit 11. Further, the control unit 11 supplies a clear command signal to the display data storage unit 18 and controls the count of the row address counter 21 and the digit address counter 22 according to the operation of the cursor keys 5a to 5d or the data input. That is, the control unit 11 sends the “+1” signal to the row address counter via the OR circuit 23 by operating the cursor key 5 d (moving instruction in the downward direction) or inputting data.
In response to the operation or processing of the cursor key 5c (upward movement instruction) or a processing operation, a "-1" signal is input to the "-1" of the row address counter 21 via the OR circuit 24.
Input to terminal. Further, the control unit 11 controls the cursor key 5a.
Input a "+1" signal to the "+1" terminal of the digit address counter 22 by operating (moving instruction to the right) or inputting data, and input a signal by operating the cursor key 5b (moving instruction to the left). Input to the "-1" terminal of the address counter 22. Further, the control unit 11 provides a reset signal to the row address counter 21 and the digit address counter 22 and a preset signal to the digit address counter 22. The row address counter 21 is, for example, an octal counter. When a "+1" signal is input after the count value becomes "3", a display scroll signal (+) is output to the control unit 11, and the count value is " When a “−1” signal is input after the value becomes “0”, a display scroll signal (−) is output to the control unit 11. The digit address counter 22 is, for example, a hexadecimal counter. When a “+1” signal is input after the count value becomes “15”, the count value is set to “0” and the OR circuit 23 is added to the row address counter 21. When the "-1" signal is input after the count value becomes "0", the count value is set to "15" and the OR circuit 24 is connected to the row address counter 21. And outputs a "-1" signal. The count value of the digit address counter 22 is preset to “15” when a preset signal is given from the control unit 11. The count values of the row address counter 21 and the digit address counter 22 are stored in the address control unit.
At the same time, the count value of the row address counter 21 is sent to the address stack memory 26. The address stack memory 26 stacks the count value of the row address counter 21 according to a stack instruction from the control unit 11, and sets stack data in the row address counter 21 according to a read instruction from the control unit 11. The address control unit 25 includes a row address counter 21 and a digit address counter.
The address of the display data storage unit 18 is specified according to the count value of 22, and the address data is output to the cursor display control unit 27. The display data storage section 18 outputs the stored data to the character generator 28 in accordance with the address specification of the address control section 25. The character generator 28 generates a character pattern according to the character data from the display data storage unit 18 and outputs the character pattern to the display buffer 29. This display buffer 29 has a display unit 30 of 4 rows × 16 digits according to the character pattern from the character generator 28.
Is displayed, and a cursor is displayed on the display unit 30 under the control of the cursor display control unit 27.

Next, the operation of the above embodiment will be described with reference to the flowchart of FIG. Now, for example, it is assumed that the calculation of 10.759 / 8 is performed first, and then the above-described division calculation is corrected to the multiplication calculation of 10.795 * 8 by operating the EDIT key 4. Then, the control unit 11
Is in a standby state until a key input is performed as shown in step A1 of FIG. 2. When a key input is performed, a key determination is made in step A2, that is, a numerical key 1, an EXE key 3, an EDIT key 4. It is determined which of the cursor keys 5a to 5d has been operated. As described above, when the operation data (including the mathematical formula command) is input by operating the numerical key 1 or the operation key 2, the process proceeds to step A3, where the key input data is input to the input buffer 17, and then the input is performed at step A4. The contents of the buffer 17 are transferred to the display data storage unit 18. The data stored in the display data storage unit 18 is read out by a character generator 28, converted into a character pattern, sent to a display buffer 29, and
Appears on 30. Then, the control unit 11 returns the digit address counter 22 to “+1” as shown in step A5, and then returns to step A1. Thereafter, the same operation is repeated every time data is input. When the key input operation of “10.795 / 8” is performed as described above, “10.795958” is displayed on the display unit 30 as shown in FIG. / 8 "is displayed.

After inputting the calculation data, the EXE key 3 is operated to execute the calculation.
Judged in A2, proceed to step A6, digit address counter
Preset “15” to 22. Next, the process proceeds to step A7, where the last digit data of the row specified by the row address counter 21 is read from the display data storage section 18 to the data determination section 19, and it is determined whether or not the data is "null". In this case, the space display using the space key is processed as if there is data. As described above, from the data of the last digit of the designated line, it is determined whether or not the data of the line is continuous to the next line, and the result of the determination is output to the control unit 11. Then, the above step A8
In step A9, if the data read from the display data storage unit 18 is not "null", that is, if it is determined that the data is continuous,
After “+1” is added to the content of 21, the process returns to step A 7, where the last digit data of the next line is read from the display data storage unit 18 by the data judgment unit.
Read to 19 to determine whether it is "null". Hereinafter, the same operation is repeated to detect a logical row (a row of continuous data). If it is determined in step A8 that the data read from the display data storage unit 18 is “null”, the process proceeds to step A10. As described above, the calculation data `` 10.
If you enter "795/8", the last digit of the line is "null"
Therefore, the process immediately proceeds to step A10. This step A
At 10, the count value of the row address counter 21 at that time is stacked in the address stack memory 26. Next, in step A11, the count value of the row address counter 21 is set to "-1". Then, as shown in step A12, the last digit data of the next higher row is read out from the display data storage unit 18 to the data judgment unit 19, and step A13 is executed. Is determined to be "null", and if not "null", the flow returns to step A11 to repeat the same operation. When a "null" row is detected, the process proceeds to step A14, where the content of the row address counter 21 is incremented by "1" to return to the original logical row, that is, the address specifying the "10.795 / 8" row. . Then, in step A15, the storage data “10.795 / 8” in the display data storage unit 18 specified by the row address counter 21 is read out to the data storage unit 12.

Thereafter, the control unit 11 sets the address data stacked in the address stack memory 26 in the row address counter 21 as shown in step A16, and
After the content of the row address counter 21 is incremented by "1" as shown in (1), it is determined in step A18 whether the operation end signal output from the flip-flop 15 is "1" or "0". If the operation end signal is "0", the process proceeds to step A19 to reset the digit address counter 22, outputs an operation instruction signal from the control unit 11 as shown in step A16, sets the flip-flop 14, and sets the flip-flop. 15 is reset, and a calculation operation is commanded to the calculation unit 16. At this time, the control unit 11 reads the data stored in the data storage unit 12 and provides the data to the calculation unit 16. As a result, the arithmetic unit 16 performs step A2
Operation processing is performed as shown in 1 and the operation result "1.34937
"5" is written to the data storage unit 12 via the control unit 11 as shown in step A22. Then, in step A23, the contents stored in the data storage unit 12, that is, the calculation result, are written into the display data storage unit 18 based on the count values of the row address counter 21 and the digit address counter 22, and are shown in FIG. 3 (b). Thus, the calculation data and the calculation result are displayed on the display unit 30. Thereafter, the process proceeds to step A24, where the row address counter 2
In step A25, the digit address counter 22 is reset, and the process returns to step A1.
In this state, as shown in FIG. 3 (b), the cursor is displayed at the first digit of the line following the calculation result display line.

In the above state, when the EDIT key 4 is operated to correct the above arithmetic expression, the process proceeds from the step A1 to the step A26 via the key judgment step A2 to reset the row address counter 21 and the digit address counter 22. ,
Return to step A1. As a result, the cursor changes to FIG.
Move to the first digit of the first line as shown in FIG. Also,
By operating the EDIT key 4, an EDIT key signal is output from the control unit 11, the flip-flop 15 is set, and an operation end signal is sent to the control unit 11. Then, from this state, the cursor is moved to the correction digit by operating the cursor keys 5a to 5d. When the cursor key 5a is operated, the digit address counter 22 is incremented by 1 in step A27, and
When 5b is operated, the digit address counter 22 is decremented by "-1" in step A28. When the cursor key 5c is operated, the row address counter 21 is set to "-1" at step A29, and when the cursor key 5d is operated, the row address counter 21 is set to "+1" at step A29.
In this example, the cursor is moved to the position of the division symbol "/" by operating the cursor key 5a, and the division operation is corrected to the multiplication operation by operating the "x" key. As a result, the division symbol "/" is corrected and displayed on the display unit 30 as the multiplication symbol "*" as shown in FIG. Next, the EXE key 3 is operated to execute the calculation of "10.795 * 8".

When the EXE key 3 is operated, key determination is performed in step A2, and after executing the above-described processing in steps A1 to A17, it is determined in step A18 whether the operation end signal is "1" or "0". . At this point, the flip-flop 15 is set as described above, and the operation end signal is set to “1”.
Therefore, the process proceeds to step A31, where the count value of the row address counter 21 is stacked in the address stack memory 26, and then, as shown in step A32, based on the count value of the row address counter 21, the display data storage unit
The stored data (last digit) of 18 is read out to the data judgment unit 19,
In step A33, it is determined whether or not “null” is set. If it is not `` null '', it means that the data of that row is continuous to the next row, so go to step A34 to clear the row specified by the row address counter 21 of the display data storage unit 18,
Then, after the content of the row address counter 21 is incremented by "1" in step A35, the process returns to step A32 and the same operation is repeated. Then, after the processing of the above steps A34 and A34, or when the processing proceeds from step A31 to step A33 via step A32, if it is determined that the data read from the display data storage unit 18 is `` null '', the processing proceeds to step A36. Then, the data of the row specified by the row address counter 21 of the display data storage unit 18 is cleared. In this example, step A3
When the process proceeds from step 1 to step A33 via step A32, it is determined that the read data from the display data storage unit 18 is "null", and in step A36, the operation result "1.349375" for the operation expression before correction is cleared. Next, the process proceeds to step A37, where the address data stacked in the address stack memory 26 is set in the row address counter 21. Thereafter, the process returns to step A19, and steps A19 to A2
The multiplication of “10.795 * 8” is performed by the processing of 2, and the calculation result “86.36” is written in the data storage unit 12. And
The calculation result stored in the data storage unit 12 is stored in step A23.
As shown in (1), the data is transferred to the display data storage unit 18 based on the count values of the row address counter 21 and the digit address counter 22. Then, the data stored in the display data storage unit 18 is sent to the character generator 28, and the calculation result together with the correction calculation expression is displayed on the display unit 30, as shown in FIG. 3 (e). That is, after erasing the operation result “1.349375” before the operation data correction, the operation result “86.36” after the operation data correction is correctly displayed. afterwards,
In step A24, the content of the row address counter 21 is incremented by "1", and in step A25, the digit address counter 22 is reset, and the cursor is moved to the first digit of the next row of the calculation result display row as shown in FIG. Go to
Then, the process returns to step A1, and waits until the next key input is performed. Hereinafter, similarly, input of operation data or correction of operation data, display processing of operation, and the like are performed.

[Effects of the Invention] According to the present invention, an arithmetic expression and an arithmetic result expression can be displayed by fully using a display unit capable of displaying a plurality of lines, and display data longer than the arithmetic result is displayed on a line where the arithmetic result is displayed. Even if is already displayed, the calculation result data can be correctly displayed by preventing the display data from overlapping, and reading errors of the calculation result can be eliminated.

[Brief description of the drawings]

1 shows an embodiment of the present invention. FIG. 1 is a block diagram showing a circuit configuration, FIG. 2 is a flowchart showing operation contents, and FIGS. 3 (a) to 3 (e) show display for key input operation. It is a figure showing a change of a state. 1: Numeric key, 2: Calculation key, 3: EXE key, 4: EDIT
Keys, 5a to 5d: cursor keys, 10: key input unit, 11: control unit, 12: data storage unit, 14, 15: flip-flop,
16 arithmetic unit, 17 input buffer, 18 display data storage unit, 19 data determination unit, 21 row address counter, 22
Digit address counter, 25: address control unit, 26: memory for address stack, 27: cursor display control unit, 28: character generator, 29: display buffer, 30: display unit.

Claims (1)

(57) [Claims] 1. A small electronic computer having a display unit capable of displaying a plurality of lines, wherein, when executing an arithmetic process based on the displayed arithmetic expression, a line to which the arithmetic expression is displayed is detected. Arithmetic expression detecting means, designating means for designating a line next to the line detected by this means as a computation result display row, and computing result data of the computation processing in the computation result display line designated by the designating means Calculation result display means for displaying, and display data detection for detecting up to which line of display data already displayed on the calculation result display line is displayed prior to display of calculation result data by the calculation result display means Means for erasing display data from the calculation result display row to the row detected by the display data detection means. Calculation machine.