JP2607301B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a mixed signal semiconductor integrated circuit in which an analog signal processing circuit and a digital signal processing circuit are mounted on one chip.

[Conventional technology]

FIG. 5 is a block diagram showing an A / D converter which is a conventional mixed signal semiconductor integrated circuit described in a data sheet of a microprocessor compatible 12-bit A / D converter manufactured by BURR-BUROUN. As shown in the figure, a digital signal processing circuit comprising a control logic 1, a clock 2, a successive approximation register 3, and a tristate buffer 4, a comparator 5, a 12-bit DAC 6,
An analog signal processing circuit consisting of a 10V reference 7 is mixed in the same chip, and an analog signal obtained from the outside, 20V range input S3 or 10V range input S4
Is input to the comparator 5 via the input terminal, and the parallel data output S8, which is a digital signal, is output to the outside via the output terminal. In FIG. 5, S1 is a control input, S2 is a bipolar offset input, S5 is a reference input, S6 is a reference output, and S7 is a status output.

In the A / D converter having such a configuration, the operation of the clock 2 and the successive approximation register 3 are controlled under the control of the control logic 1 based on the control input S1. on the other hand,
Analog signal processing circuits such as comparator 5 are not under the control of control logic 1.

FIG. 6 is a block diagram showing a conventional mixed signal semiconductor integrated circuit D / A converter described in a data sheet of a microprocessor compatible 16-bit D / A converter manufactured by BURR-BUROUN. As shown in the figure, a digital signal processing circuit including an input latch 11, a D / A latch 12, and a control circuit 14 and an analog signal processing circuit including a ladder resistor network 13 (including a current switch) and an operational amplifier 15 are the same chip. Are mixed in.

In such a configuration, data inputs D0 (LSB) to D15 (MSB), which are digital signals obtained from the outside, are taken into the input latch 11 via the input terminals. And D / A
A plurality of current switches are each turned on in the ladder resistance network 13 based on the data input D0~D15 obtained via the latch 12, to vary the DC current I _DAC through resistor R _F by turning off. The output of the operational amplifier 15 changes based on the current change of the DC current _IDAC , and the output of the operational amplifier 15 is output to the outside as an analog signal output _VOUT through an external terminal, thereby realizing D / A conversion. ing.

In this D / A converter, the control circuit 14 is controlled by the input latch, which is a digital signal processing circuit.
11 and a D / A latch 12. In FIG. 6, ▲
▼ and ▲ ▼ are latch enable signals, ▲
▼ is a clear signal and ▲ ▼ is a write signal.

[Problems to be solved by the invention]

Conventional mixed-signal semiconductor integrated circuits such as A / D converters or D / A converters are configured as described above, and the operation of the digital signal processing circuit is controlled by the control circuit. Can be deactivated.

On the other hand, since the analog signal processing circuit is not under the control of the control circuit, if the power is turned on and the digital signal processing circuit becomes inactive, the digital signal processing circuit must be inactive unless the power is turned off. Can not.

Generally, the power consumption of an analog signal processing circuit is larger than that of a digital signal processing circuit, and the main factor is that there are many current paths that always flow from the power supply to the ground level in the analog signal processing circuit.

FIG. 7 is a circuit diagram showing the internal details of the operational amplifier 15 of FIG. As shown in the figure, Pch transistors Q1 to Q8,
Nch transistors Q11 to Q15 and phase correction capacitor C1
The input terminals P1 and P2 which are the gate inputs of the transistors Q5 and Q4 forming a differential pair
15 are set to NON-INVERT input and INVERT input, and an output signal OUT is output from an output terminal P3 connected between the drain of the transistor Q8 and the drain of the transistor Q14. The operational amplifier 15 having such a configuration always has four current paths flowing from the power supply to the ground level,
I _REF , constant current I ₀ , constant current I _S , and bias current I _BIAS always flow, causing an increase in power consumption.

In the D / A converter shown in FIG. 6, the control circuit 14 based on the latch enable signals 信号 and 、, the clear signal ▼ and the write signal ▼
Controls the data inputs D0 to D15 to the input latches 11 and D
/ A Although the latch can 12 be latched into the output DC current I _DAC ladder resistance network 13 continues to flow until a change in data latched by the D / A latch 12. This DC current _{IDAC is} also a current flowing from the power supply to the ground level in the analog signal processing circuit, and causes an increase in power consumption.

As described above, the analog signal processing circuit has a large number of current paths that always flow from the power supply to the ground level. Therefore, there has been a problem that low power consumption of the mixed signal semiconductor integrated circuit is prevented.

The present invention has been made to solve the above problems, and has as its object to obtain a mixed signal semiconductor integrated circuit with low power consumption.

[Means for solving the problem]

A semiconductor integrated circuit according to the present invention includes a digital signal processing circuit for processing a digital signal, an analog signal processing circuit for transmitting and receiving a signal to and from the digital signal processing circuit and processing an analog signal, and an active circuit for the digital signal processing circuit. And a control circuit for outputting a first control signal for instructing inactivation and outputting a second control signal for instructing activation / inactivation to the analog signal processing circuit, wherein the analog signal processing circuit comprises: Upon receiving the second control signal instructing inactivation, the control circuit includes a current path cutoff unit that cuts off a current path flowing from a power supply to a ground level in the circuit, wherein the control circuit includes the digital signal processing circuit and The deactivation instruction by the first and second control signals is issued to the analog signal processing circuit at the same timing, and the deactivation instruction is changed from the deactivation to the activation. Instructing than the first control signal is performed at the timing is advanced toward the second control signal.

[Action]

The analog signal processing circuit according to the present invention includes a current path cutoff unit that cuts off a current path flowing from the power supply to the ground level in the circuit when receiving the second control signal indicating inactivation from the control circuit. When the second control signal for instructing activation is input, power consumption is reduced by the amount of current flowing through this current path.

〔Example〕

FIG. 1 is a block diagram showing a mixed signal semiconductor integrated circuit according to one embodiment of the present invention. As shown in the figure, a digital signal processing system clock circuit 21 and a digital signal processing circuit 22 (broadly speaking, the clock circuit 21 is also included in the digital signal processing circuit 22) and an analog signal processing circuit 23 are mixed. ing. Then, the control signals SC1 and SC2 are supplied from the control circuit 24 to the analog signal processing circuit 23, and the control signal SC3 is supplied to the clock circuit 21 and the digital signal processing circuit 22. As shown in Table 1, the H and L levels of these control signals SC1 to SC3 change during normal operation and during temporary suspension. The clock circuit 21 supplies a clock φ to the digital signal processing circuit 22, the analog signal processing circuit 23, and the control circuit 24, and the activation / inactivation of the clock φ is controlled by the H / L level of the control signal SC3.

FIG. 2 is a timing chart showing the operation of the mixed signal semiconductor integrated circuit shown in FIG. Hereinafter, the operation will be described with reference to FIG. As shown in the figure,
Before time t1, the control signals SC1 to SC3 indicate H, L, H and normal operation, the clock circuit 21 outputs an active (oscillating) clock φ, and the digital signal processing circuit 22 and the analog signal processing The circuit 23 is active and performs a normal operation.

Then, at time t1, the control signals SC1 to SC3 change to L, H, and L, and when a pause operation is instructed, the clock φ becomes inactive and is fixed at L level. At this time, the digital signal processing circuit 22 functions to hold the state immediately before the time t1.
Since this function can be realized by an existing technology using a latch or the like, its details will not be described here.

On the other hand, in the analog signal processing circuit 23, all the current paths from the power supply to the ground level are cut off, as will be described in detail later. Therefore, when the analog signal processing circuit 23 is in the inactive state, unnecessary power consumption is not performed.

Then, at time t2, the control signals SC1 and SC2 change to the H and L levels (SC3 maintains the L level), and the analog signal processing circuit 23 is activated. Then, at time t3, the control signal SC3
Changes to the H level and the clock φ restarts oscillating to activate the digital signal processing circuit 22.

The reason for returning the analog signal processing circuit 23 from the inactive state to the active state prior to the digital signal processing circuit 22 is as follows.

The analog signal processing circuit 23 is in a stable state immediately after activation, that is, when the digital signal processing circuit 22
Therefore, if the analog signal processing circuit 23 and the digital signal processing circuit 22 are simultaneously activated when transitioning from the paused state to the normal operation state again, even if the digital signal processing circuit 22 becomes stable, There is a period in which the analog signal processing circuit 23 is in an unstable state, and there is a problem that the power consumption of the digital signal processing circuit 22 in this period is completely wasted. To avoid this problem, the analog signal processing circuit 23 is returned to the active state a predetermined time before the digital signal processing circuit 22, so that the two circuits 22, 23 become stable at substantially the same time. Note that the predetermined period may be set in advance in the control circuit 21 based on a delay time of the analog processing circuit 23 with respect to the digital processing circuit 22 required to be in a stable state after activation.

FIG. 3 is a block diagram showing an example in which the mixed signal semiconductor integrated circuit shown in FIGS. 1 and 2 is applied to a D / A converter. This figure shows only the features of the present invention, and the overall configuration is the same as that of the conventional example shown in FIG.

As shown in the figure, control signals SC1 and SC2 are obtained from a control circuit 30 obtained by improving the conventional control circuit 4.
Is supplied to a ladder resistance network 33 and an operational amplifier 31 which are analog processing circuits, and a control signal SC3 is supplied to a D / A latch 32 which is a digital processing circuit. The D / A latch 32, the ladder resistor network 33 and the operational amplifier 31 respectively control the control signal SC1 from the conventional D / A latch 12, the ladder resistor network 13 and the operational amplifier 15.
It has been improved to correspond to ~ SC3.

In such a configuration, the control signals SC1 to SC3 are L, H, L
Next, and instructs to pause, D / A latch 32 provides a fixed value in the number of current paths is minimized as the raw genesis of DC current I _DAC clears the latch on the ladder resistance network 33. At the same time, the ladder resistor network 33 functions to cut off the current path.

Further, the operational amplifier 31 also interrupts a current path that constantly flows from the power supply to the ground level based on the control signals SC1 and SC2.

FIG. 4 is a circuit diagram showing the internal details of the operational amplifier 31 shown in FIG. As shown in the figure, a Pch transistor Q9 and Nch transistors Q16 and Q17 are added to the configuration of the conventional example shown in FIG. The control signal SC1 is applied to the gate of the transistor Q9, the source is connected to the power supply, and the drain is connected to the gates of the transistors Q1, Q3 and Q6. The control signal SC1 is applied to the gate of the transistor Q16, the source is grounded, and the drain is connected to the source of the transistor Q11. The control signal SC2 is applied to the gate of the transistor Q17, the source is grounded, and the drain is connected to the gates of the transistors Q7 and Q14. The other configuration is the same as that of the conventional example shown in FIG.

In such a configuration, when the control signals SC1 and SC2 become L and H, respectively, and instruct a temporary stop, the transistor Q9
And Q17 turn on, and transistor Q16 turns off. When the transistor Q9 is turned on, the gate potentials of the Pch transistors Q1, Q3 and Q6 become H level, so that the transistors Q1, Q3 and Q6 are all turned off. On the other hand, when the transistor Q17 turns on, the gate potentials of the Pch transistor Q7 and the Nch transistor Q14 are led to L level, so that the transistor Q7 turns on and the transistor Q14 turns off. Transistor Q7
Is turned on, the gate of the Pch transistor Q8 is led to the L level, so that the transistor Q8 is turned on. The potential of the output terminal P3 becomes H with the turning on and off of the transistor described above.
Fixed to level.

As a result, the reference current I _REF , the constant current I ₀ , the constant current I _S and the bias current I
_Since the transistors Q16, Q3, Q6 and Q14 interposed in the _BIAS current path are turned off, all of these current paths are cut off.

Thus, the operational amplifier 31 is controlled based on the control signals SC1 and SC2.
Cuts off all the current paths inside, so that the power consumption of the operational amplifier 31 during the temporary stop can be greatly reduced. Note that the function of interrupting the current path in the ladder resistor network 33 is performed based on the same principle as that of the operational amplifier 31.

In the D / A converter shown in FIGS. 3 and 4,
Consider a case in which a transition from the paused state to the normal state occurs. First,
The control signals SC1 and SC2 change from the L and H levels to the H and L levels (SC3 maintains the L level).
C3 changes to H level. The predetermined time may be set in advance in the control circuit 30 based on the delay time of the analog processing circuit with respect to the digital processing circuit required to be in a stable state after activation.

By changing the timing at which the analog processing circuit changes from the inactive state to the active state between the analog processing circuit and the digital processing circuit, the digital processing circuit and the analog processing circuit are simultaneously set to be in a stable state. It is possible to prevent waste of power consumption caused by the circuit becoming stable early.

〔The invention's effect〕

As described above, according to the present invention, the analog signal processing circuit cuts off the current path flowing from the power supply to the ground level in the circuit when receiving the second control signal indicating inactivation obtained from the control circuit. Since the current path cutoff means is provided, there is an effect that when the second control signal indicating inactivation is input, power consumption can be reduced by the amount of current flowing through this current path.

In addition, the control circuit instructs the digital signal processing circuit and the analog signal processing circuit to deactivate by the first and second control signals at the same timing, and issues an instruction from deactivation to activation to the first control signal. Since the second control signal is performed at a timing earlier than that of the second control signal, by returning the analog signal processing circuit to the active state earlier than the digital signal processing circuit, both the analog and digital signal processing circuits are stabilized almost simultaneously. State, and as a result, wasteful power consumption can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a mixed signal semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation thereof, and FIG. 3 is a mix diagram shown in FIGS. This is a specific example of a signal-signal semiconductor integrated circuit.
FIG. 4 is a block diagram showing a D / A converter, FIG. 4 is a circuit diagram showing the internal details of the operational amplifier shown in FIG. 3, FIG. 5 is a block diagram showing a conventional A / D converter, and FIG. FIG. 7 is a block diagram showing a D / A converter, and FIG.
FIG. 3 is a circuit diagram showing internal details of the operational amplifier shown in FIG. In the figure, 21 is a clock circuit, 22 is a digital signal processing circuit, 23 is an analog signal processing circuit, 24 is a control circuit, 30 is a control circuit, 31 is an operational amplifier, 32 is a D / A latch, 33 is a ladder resistor network, Q1 Q9 to P9 are Pch transistors, and Q11 to Q17 are Nch transistors. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A digital signal processing circuit for processing a digital signal; an analog signal processing circuit for transmitting and receiving a signal to and from the digital signal processing circuit to process an analog signal; and activating / deactivating the digital signal processing circuit. A control circuit that outputs a first control signal for instructing the analog signal processing circuit and outputs a second control signal for instructing activation / inactivation to the analog signal processing circuit. Receiving the second control signal, a current path cutoff means for cutting off a current path flowing from a power supply to a ground level in the circuit, wherein the control circuit controls the digital signal processing circuit and the analog signal processing circuit. The deactivation instruction by the first and second control signals is performed at the same timing, and the instruction from deactivation to activation is made by the first control signal. And a timing at which the second control signal is earlier.