JP2608658B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a high-frequency high-power Ga having a PHS.
The present invention relates to an AsIC and a method for manufacturing the AsIC.

[0002]

2. Description of the Related Art FIG. 6 is a schematic cross-sectional view showing the structure of a conventional high-frequency high-power semiconductor device.
2 is a via hole in the semiconductor substrate 1, 2a is a metal layer formed in the via hole 2, 3 is a separation groove for separating a semiconductor chip into individual substrates, 3a is a metal layer formed in the separation groove 3, Numeral 4 denotes a power supply layer for electrolytic Au plating, numeral 5 denotes a plated heat sink (hereinafter, referred to as AuPHS) formed by Au electrolytic plating, symbol δ denotes a warpage amount of the chip, and l denotes a chip long side length. I have.

First, a manufacturing method will be described. FIG.
1A, an element portion 8 such as an FET, a via hole 2 and the like are formed on a first surface side of a semiconductor substrate 1 and a chip separation groove 3 is further provided. After forming the layers 2a and 3a, the second surface side of the semiconductor substrate 1 opposite to the first surface side is
This is a state in which polishing is performed until the thickness becomes about 30 μm, and then a power supply layer 4 for electrolytic Au plating is formed on the second surface of the substrate 1.

After that, about 40 μm
A thick AuPHS 5 is formed (FIG. 4 (b)), and then the semiconductor chip for high frequency and high output as shown in FIG.

In the above conventional semiconductor device, the PHS5
Can function as a heat radiator for releasing heat generated from the element portion 8 such as an FET formed on the first surface side of the semiconductor substrate 1 to the chip carrier side and easily handle the thin semiconductor substrate 1, that is, the chip. It has the function to do.

[0006]

In the conventional semiconductor device configured as described above, the warpage of the chip occurs due to the heating at the time of die bonding due to the difference in the linear expansion coefficient between the material of the substrate 1 and the AuPHS5. For example, about 1 substrate 3
GaAs and PHS5 having a thickness of 0 μm are converted to Au having a thickness of
Assuming that the heating temperature at the time of die bonding is 300 ° C., the relationship between the warpage amount δ and the chip long side length 1 is shown in FIG.
become that way. That is, in the conventional semiconductor device under the above conditions, if the chip long side length 1 is set to 2 mm or more, the chip cannot enter the assembly testable area (δ = 30 μm),
Die bonding during chip mounting on chip carrier,
In addition to the difficulty in wire bonding, the contact area between the chip and the chip carrier has been reduced, and the heat radiation characteristics have been significantly deteriorated, causing a problem that desired RF characteristics cannot be obtained.

[0007] Further, such chip warpage is difficult to control the amount of molten solder when mounting a chip and a chip carrier on a chip and a chip carrier using pellets of Au-Sn eutectic solder. The fact that chips are floating in the air was also a major cause of the occurrence.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a high-frequency high-power semiconductor device which prevents chip warpage and does not deteriorate heat radiation characteristics even when the chip size is increased, and a semiconductor device therefor. The purpose is to obtain a manufacturing method.

[0009]

In a semiconductor device according to the present invention, a layer made of a good heat conductive material by plating is provided only on a heat radiating portion on the back surface of a substrate corresponding to a heat generating portion of a chip provided on the surface of the substrate. In addition, a honeycomb-like layer formed by laminating fine particles made of a good heat conductive material so as to form voids is provided on the other back surface of the substrate.

In a method of manufacturing a semiconductor device according to the present invention, an element is formed on a first surface side of a semiconductor substrate, and a power supply layer for electrolytic plating is formed on the entire second surface of the substrate.
A first layer made of a material having good thermal conductivity is formed by electrolytic plating only in a region on the second surface which is aligned with the heat generating portion of the element, and a first layer on the second surface of the substrate is formed. Spherical fine particles made of a material having good thermal conductivity are deposited in an area other than the formation area, and the substrate surface is brought into close contact with the fine particles or the fine particles by electrolysis at a low current density to form a honeycomb-shaped second layer. And a good heat conductive material for reinforcing the first and second layers on the first layer and the honeycomb-shaped second layer formed on the second surface of the substrate. The third layer is formed.

Further, according to the semiconductor device and the method of manufacturing the same of the present invention, a layer made of a good heat conductive material by plating is provided only on a heat radiating portion on the back surface of the substrate corresponding to a heat generating portion of a chip provided on the surface of the substrate. The other side of the substrate is formed with a graphite fiber composite plating for preventing warpage. Also, Au is formed on the upper layer of the composite plating.
The Sn alloy solder layer is formed by electrolytic plating.

[0012]

In the present invention, the gap between the fine particles constituting the honeycomb-shaped good heat conductive material layer is formed between the substrate material and the good heat conductive material layer provided on the back surface of the substrate during chip stabilization bake or die bonding. The stress of the good thermal conductive material layer on the substrate material caused by the difference in the coefficient of thermal expansion is reduced, and the warpage of the chip is reduced.

Further, in the present invention, warpage can be prevented by forming the graphite fiber composite plating in a combination and a composition ratio in which the signs of stress on the substrate material cancel each other. Further, by forming the Au—Sn alloy solder layer by electrolytic plating, the amount of solder can be kept constant without controlling the amount of molten solder during mounting.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a configuration of a first that by the example semiconductor device for high frequency and high output of the present invention. FIG. 2 is the main showing an example of a method of manufacturing a semiconductor device according to a first embodiment It is sectional drawing. In the figure, 1 is a semiconductor substrate, 2 is a via hole, 2a is a metal layer provided in the via hole 2, 3
Is a separation groove for separating semiconductor chips into individual substrates,
3a is a metal layer provided in the separation groove 3, 4 is a power supply layer for electrolytic Au plating, and 5 is a PH formed by Au electrolytic plating.
S and 6 are Au fine particles, 66 is a honeycomb-shaped Au film made of Au fine particles 6, 7 is AuPHS5 and honeycomb-shaped Au.
The reinforcing Au film is formed so as to cover the film 66.

First, the manufacturing method will be described. First, an element portion 8 such as an FET, a via hole 2 and a chip separation groove 3 are formed on the first surface side of the semiconductor substrate 1.
After forming the metal layers 2a and 3a in the chip separation groove 3, respectively, the second surface side of the semiconductor substrate 1 opposite to the first surface side is polished until the thickness of the substrate 1 becomes about 30 μm. Then, a power supply layer 4 for electrolytic Au plating is formed on the polished second surface of the substrate 1.

Thereafter, only a portion of the substrate 1 on the second surface side opposite to the first surface side, which is aligned with the element heat generating portion such as the FET and the via hole portion 2, is selectively plated by electrolytic plating. After the AuPHS 5 having a thickness of about 40 μm is formed, the second surface of the substrate 1 is placed upward in a sulfurous acid-based Au electrolytic plating solution, and the sulfurous acid-based Au electrolytic plating solution is added by adding a trace amount of acid. Is decomposed to a particle size of about 0.5 to 1
2 μm spherical Au fine particles 6 are generated, and the spherical Au fine particles 6 are settled on the substrate (FIG. 2A).

Then, the Au fine particles 6 are deposited on the second surface of the substrate 1 by at least 50 μm or more (FIG. 2B).
Thereafter, the substrate surface and the fine particles or the fine particles are brought into close contact with each other by pulse current plating at a low current density to form a honeycomb-shaped Au film 66. Subsequently, the honeycomb-shaped Au film 66 formed on the second surface of the substrate 1 is polished to a thickness of about 40 μm (FIG. 2C).

Thereafter, AuPHS5 and honeycomb-shaped Au
A reinforcing Au film 7 having a thickness of about 3 μm is formed on the film 66 by electrolytic plating, and the chip is separated by dicer cutting at the chip separating groove 3 to obtain a semiconductor device as shown in FIG.

In the semiconductor device having the above-described structure, the gap between the honeycomb-shaped Au film 66 and the substrate material and the Au film are stably formed when the semiconductor device, that is, the semiconductor chip is subjected to stabilization baking or die bonding. It has an effect of relaxing the stress of the Au film on the substrate material caused by the difference in expansion.

Therefore, according to the present embodiment, the warpage of the chip during stabilization baking and die bonding is suppressed,
Die bonding and wire bonding can be easily performed when mounting a chip on a chip carrier. Furthermore, even if the chip size is increased, the contact area between the chip and the chip carrier can be increased, so that the heat radiation characteristics can be improved and a device having desired RF characteristics can be obtained. In the present embodiment, Au plating is used as the PHS, but other metal materials or alloys having good heat conductivity, such as Cu, may be used.

FIGS. 3 and 4 are sectional views showing the structure of a high-frequency high-power semiconductor device according to a second embodiment of the present invention.
It is a principal sectional view showing the manufacturing method. In the figure, 1
Is a GaAs substrate, 8 is an element portion such as an FET, 2 is a via hole, 4 is a first Au plating layer, 10 is an Au-graphite composite plating layer, 10a is a graphite fiber, 10b
Denotes a plating metal layer, 5 denotes an AuPHS, and 11 denotes an Au-Sn alloy plating layer.

FIG. 3 shows the FE on the first surface side of the semiconductor chip.
AuPHS5 having a thickness of about 40 μm is formed on a portion of the chip on the second surface side opposite to the first surface side, which is aligned with the element heat generating portion such as T8 and the via hole portion 2; About 40 μm on the second surface side portion of the substrate
In this example, the Au-graphite composite plating layer 10 is provided. The linear expansion coefficients at room temperature are 6 for GaAs, 14.2 for Au, and 3.1 for graphite ([× 10
^-6 ° C. ^-1 ] The unit is omitted here), so that the plating metal 10b is Au, and the graphite fibers 10a and Au in the dispersion plating layer 10 have a composition ratio of about 7: 3, respectively. By doing so, the signs of the stress on the substrate material 1 cancel each other, and chip warpage can be reduced.

In the graphite composite plating 10, the plating metal layer 10b is made of Ni (linear expansion coefficient 13.4).
The same effect can be obtained when the composition ratio of the graphite fiber 10a and the plating metal 10b is set to about 13: 7. However, in this case, in order to minimize the conductor loss of the microstrip line, it is necessary to adopt a structure in which the first Au plating layer 4 having a thickness of about 1 to 2 μm and having good electric conductivity is disposed below the dispersion plating 10.

FIG. 4 shows a structure A of the structure of the second embodiment.
A on the upper layer of uPHS5 and graphite composite plating layer 10
The u-Sn composite plating layer 11 is provided.

Next, the forming process flow will be described. FIG. 5A shows an element portion 8 such as an FET and a via hole 2.
In this state, the second surface of the GaAs substrate 1 on which the first Au plating layer 4 is formed is polished to about 30 μm. Thereafter, AuPHS having a thickness of about 40 μm is formed by selective electrolytic plating using the first Au plating layer 4 as a power supply layer and a photoresist as a mask (FIG.
(b)). In this state, a fiber 10a of about 6 to 8 μm thick graphite wire whose surface has been previously coated with electroless Ni plating or the like is stuck to the second surface of the substrate 1 with the surface tension of water so as to avoid the PHS. At the same time, it is physically fixed so that the position does not shift (FIG. 5C). Thereafter, electrolytic plating of Au, Cu, Ni, or the like is performed to bring the two into close contact. At this time, the plating solution penetrates between the graphite fibers, but the plating reaction is diffusion-controlled, so that pulse plating is preferable as the plating method. Thus, the Au-graphite composite plating layer 10 is obtained (FIG. 5D).
). The state where the composite plating layer 10 is flattened (FIG. 5E).
3), the structure shown in FIG. 3 is obtained.

If chip separation is performed after the state of FIG. 5 (e) with the Au-Sn alloy plating layer 11 formed (FIG. 5 (f)), the structure of FIG. 4 is obtained. The Au—Sn alloy plating layer 11 is formed by adjusting the plating current density so that the composition ratio is Au: Sn = 8: 2.

In the semiconductor device configured as described above, AuP is provided on the second surface side of the substrate opposite to the first surface, which is positioned at the element heat generating portion such as an FET.
Since HS is formed, and the other portion of the second surface of the substrate is provided with a graphite fiber composite plating having a thermal expansion coefficient matched to the substrate material, chip warpage during mounting is reduced.

Further, by forming the Au—Sn alloy solder by electrolytic plating, the chip can be stuck to the chip carrier in a flat state without controlling the amount of solder during mounting.

In this embodiment, Au plating is used as the PHS, but other metal materials or alloys having good heat conductivity, such as Cu, may be used. Ga as a semiconductor substrate
Although the As substrate is used, a semiconductor substrate or a ceramic substrate such as a Si substrate, an InP substrate, or a substrate obtained by epitaxially growing a GaAs layer on a Si substrate may be used. Further, although graphite fibers are used, any fibers made of a material having a linear expansion coefficient of about 3 × 10 ⁻⁶ may be used.

[0030]

As described above, according to the present invention, the portion of the substrate positioned on the element heat generating portion such as the FET on the second surface side opposite to the first surface side is preferably plated. Since a layer made of a heat conductive material is formed, and a layer made of a honeycomb-shaped good heat conductive material is arranged on the other portion of the second surface of the substrate, voids of the fine particles constituting the honeycomb layer are formed. The part relaxes the stress of the good heat conductive material layer on the substrate material caused by the difference in the coefficient of thermal expansion between the substrate material and the good heat conductive material layer at the time of die bonding of the chip, thereby radiating heat from the element heating part. There is an effect that the chip warpage can be reduced without impairing the effect, and the chip size can be increased.

Further, according to the present invention, the portion of the second surface opposite to the first surface of the substrate, which is positioned at the element heat-generating portion such as an FET, has good thermal conductivity by plating. Since a layer made of a material was formed, and a second layer formed by graphite fiber composite plating having a thermal expansion coefficient matched to that of the substrate material was disposed on the other portion of the second surface of the substrate, the element generated heat. Chip warpage can be reduced without impairing the heat radiation effect from the part, and the chip can be made larger.

Further, by forming the Au—Sn alloy solder by electrolytic plating, the chip can be stuck to the carrier in a flat state without controlling the amount of solder at the time of mounting, and there is an effect that chip warpage can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a high-frequency high-power semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a high-frequency high-power semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a configuration of a high-frequency high-power semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a configuration of a high-frequency high-power semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view illustrating a method for manufacturing a high-frequency high-power semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a conventional high-frequency high-power semiconductor device.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional high-frequency high-power semiconductor device.

FIG. 8 is a diagram showing the relationship between the amount of warpage and the long side length of a conventional high-frequency high-power semiconductor chip.

[Explanation of symbols]

 Reference Signs List 1 GaAs substrate 2 Via hole 4 First Au plating layer 5 AuPHS 8 Element part such as FET 10 Au-graphite fiber composite plating layer 10a Graphite fiber 10b Plated metal in composite plating 11 Au-Sn alloy solder plating layer δ Chip warpage l Chip long side length

Claims (5)

(57) [Claims] 1. An element is formed on a first surface side of a substrate,
In a semiconductor device having a heat radiating means on a second surface side opposite to the first surface side, the heat radiating means is a region on a second surface of the substrate which is aligned with a heat generating portion of the element. A first layer made of a good heat conductive material formed by plating; and a spherical layer made of a good heat conductive material on a portion other than the first layer forming region on the second surface of the substrate. A semiconductor device comprising a honeycomb-shaped second layer formed by laminating fine particles so that voids are formed between the fine particles. 2. An element on a first surface side of a substrate, wherein the first
A method of manufacturing a semiconductor device having a heat radiating means on a second surface side opposite to a surface side of a semiconductor device, comprising: forming an element on a first surface side of a semiconductor substrate; and an entire surface of the second surface of the substrate. Forming a power supply layer for forming an electrolytic plating on the first layer; and forming a first layer made of a material having good thermal conductivity by electrolytic plating only in a region on the second surface which is aligned with a heat generating portion of the element. And depositing spherical fine particles made of a material having good thermal conductivity in a region other than the first layer forming region on the second surface of the substrate,
The substrate surface and the fine particles or the fine particles are brought into close contact with each other by electrolytic plating at a low current density, and a second honeycomb-shaped substrate is formed.
Forming a first layer and a second layer on the first layer and the honeycomb-shaped second layer formed on the second surface of the substrate. Forming a third layer made of a good heat conductive material. 3. An element is formed on the first surface side of the substrate,
In a semiconductor device having a heat radiating means on a second surface side opposite to the first surface side, the heat radiating means is a region on a second surface of the substrate which is aligned with a heat generating portion of the element. The substrate material and the linear expansion coefficient were matched to the first layer made of a good thermal conductive material formed by plating, and the portion other than the first layer forming region on the second surface of the substrate. A semiconductor device comprising a second layer formed by graphite fiber composite plating. 4. The method according to claim 3, wherein an Au—Sn alloy plating film is formed on the composite plating film by an electrolytic plating method so as to be a eutectic alloy having a composition ratio of 8: 2. Semiconductor device. 5. A method of manufacturing a semiconductor device having an element on a first surface side of a substrate and a heat radiating means on a second surface side opposite to the first surface side, comprising: Forming an element on the first surface side, forming a power supply layer for electrolytic plating over the entire surface of the second surface of the substrate, and positioning the power supply layer on the second surface in a heating portion of the element. Forming a first layer made of a material having good thermal conductivity by electrolytic plating only in the combined region; and metal-coating a region other than the first layer formation region on the second surface of the substrate. Electrolytic plating in a state in which the graphite fibers are pressed, and a step of bringing the graphite fibers into close contact with each other while filling the gaps between the graphite fibers, and a step of polishing and flattening the second surface of the substrate. Semiconductor device manufacturing method.