JP2608680B2 - CPU execution method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to digital computers, and more particularly to a virtual management system for a CPU running multiple processors.

BACKGROUND OF THE INVENTION Simplified instruction set processor chips for implementing virtual memory management systems are known. In such a system, a virtual address is translated into a physical address before executing a memory reference, and this physical address is used for accessing the main memory. This physical address is stored in the page table indexed by the virtual address,
Therefore, every time a virtual memory exists, the memory management system refers to the page table to find a physical address. The process running on such a machine at a given time uses only a few pages and therefore holds the page table entries used for these maximum likelihoods in a translation buffer within the CPU chip itself, thereby fetching the page table entries using memory references Try to eliminate the need to The page table entries contained in the translation buffer include other information used by the memory management system, such as privilege information, access rights, etc., to provide integrity and robust operation. Before allowing a message reference, the current state of the processor and the characteristics of the memory reference are checked against the information in the page table entries to confirm that the memory reference is preferred.

Many processes (tasks) can be executed in a time-division manner on the CPU at a given time, and each of these processes has its own area of virtual memory. The actuation system itself contains a number of pages that need to be referenced by each of these processes. Thus, pages so divided by the process are preferably held in main memory rather than swapped out, and the page table entries for such pages are preferably held in a translation buffer. The reason is that these entries are referred to continuously. However, the translation buffer is usually flushed by invalidating all entries when a context switch is performed.

A mechanism using so-called "address space numbers" is implemented in the processor to reduce the need to disable cache address translation in the translation buffer for a process-specific address when a context switch occurs. Load the address space number (process tag) for the current process into the processor's registers so that it becomes part of the current state. That is, this loading is performed by a privileged instruction from the message process-specific block. This causes each process to associate it with an address space number, which is an arbitrary-assign number generated by the operating system. This address space number is kept as part of the machine state and is also stored in the translation buffer for each page entry belonging to this process. If a memory reference is made as part of the tag match in the translation buffer, the current address space number is compared with the translation buffer entry to see if there is a match. To accommodate the splitting of entries, an address space matching function can be added to the above comparison; that is, a request to match the address space number by the "match" bit in the entry can be turned on or off. . When this bit is turned on, the entry "matches" whether the address tag matches regardless of the address space number.
Because of this, the operating system loads certain page table entries with this match bit so that these pages are split by all processes.

In operating a CPU using virtual machines, each virtual machine functions as if it were an independent processor,
And each virtual machine has a virtual machine operating system and multiple process running when only one CPU is functioning. The virtual machine is described in "Composition of Computers: Principles and Examples" by C. Biolec et al., Published by McGraw-Hill, 1982, pp. 227-228.
To run these virtual machines, run a virtual machine monitor (another execution level). As previously mentioned,
There are pages used by the operating system used by all of the processors in the virtual machine. When a context switch is provided between processes or between virtual machines, the performance is improved if page entries are held in the translation buffer.

Several virtual machines and virtual machine memories running on the CPU need to have separate and separated memory spaces, while maximizing system performance. For this purpose, the virtual machine and the virtual machine monitor need to be able to use the same virtual address for other purposes. However, when the context switches from one virtual machine to another, or to a virtual machine monitor, or when switching from a virtual machine monitor, by unnecessarily flushing the entry into the translation buffer used for the new context. Try to impose a performance penalty. For this reason, it is important to offer off both address space numbers and matching characteristics when running a virtual machine.

SUMMARY OF THE INVENTION The present invention is a method of operating a processor comprising a translation buffer for translating a virtual address to a physical address, the translation buffer comprising a plurality of pages each including a page frame number indexed by a virtual address tag. The translation buffer also stores an address space number and an address space match entry for each page table entry, wherein the address space number corresponds to a process executed on the processor. The matching entry has a value indicating that the address space numbers need to be matched and a flag having another value indicating that the address space numbers need not be matched. A condition that the processor must store the current number as a value reflecting the state of the processor and that the matching entry needs to be disabled and another condition that does not need to be disabled. Storing the third match value, and comparing the virtual address tag with a field of a virtual address generated by the processor, comparing the address space number with the current number, and comparing the virtual address tag with the virtual address tag. If the comparison of the field of the virtual address is consistent; the match occurs by comparing the address space number with the current number, and if the matching entry is the certain value, the page relative to a memory reference Using a frame number; and even if the matching entry is the other value, Third
If the match value indicates the condition, the method includes using a page frame number for memory reference regardless of whether the address space number matches the current number.

The present invention also relates to a processor system having a CPU and a memory, comprising: a) fetching an instruction from the memory in the CPU, decoding the instruction in the CPU,
Means for executing instructions for accessing a memory of read and write data within; b) means for generating virtual addresses for use in said instruction fetch means and data memory access means within said CPU; c) said memory A page table including a plurality of page table entries each having a page frame number referring to a different page of the memory; and d) including a translation buffer for storing a number of the page table entries; Means for translating a virtual address to a physical address; and e) means for addressing a memory using a page frame number from said translation buffer and using a portion of the virtual address; f) said translation buffer comprising: Each page Storing the address space matching entry stores the address tag and the address space number for table entries, wherein said address space number is the CPU
And a value indicating that the address space numbers need to be matched, and another value indicating that the address space numbers do not need to be matched. And the translation buffer also stores a matching disable indicator for each page table entry and is held as part of a state of the CPU by means for storing a current value in the CPU. G) comparing the address tag with a field of the virtual address generated by the CPU in a translation buffer and maintaining the address space number and a portion of the state of the CPU. With means for comparing also with the current number; When both of the comparing operations by the comparing unit generate a match and the matching entry is the certain value, the address specifying unit uses a certain page frame number for memory reference; If a match occurs due to a comparison with a field and if the match entry is the other value, setting the disable match indicator will determine whether the address space number matches the current number. Regardless, the address designating means uses the page frame number for the memory reference.

According to one embodiment of the present invention, a CPU executing a virtual memory management system uses an address space number characteristic to cause an entry to remain in a translation buffer of a currently unexecuted process and be shared by individual processes or operating systems. Reuse the translation buffer entry for such a page of referenced memory. To do this, an "address space match" entry is used in the page table entry signal that can use the translation buffer content when the addresses match, even if the address space numbers do not need to match. When executing a virtual machine with this CPU, the address space matching property is used in the virtual machine, but it is impossible to execute the address space matching property for all the address space numbers for the virtual machine monitor using an additional entry. I do. In another example, additional entries are used in the translation buffer to limit address space matching properties to the address space associated with a single virtual machine or virtual machine monitor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an electrical circuit of a computer system having a CPU that may employ features of the present invention; FIG. 2 is a block of instruction units of the CPU of FIG. FIG. 3 is a block diagram of an integer execution unit of the CPU of FIG. 1, ie, an electric circuit of the E-box. FIG. 4 is an addressing unit of the CPU of FIG.
FIG. 5 is a floating-point execution unit of the CPU of FIG.
FIG. 6 is a block diagram of an electric circuit of the F-box; FIG. 6 is an explanatory diagram showing a time diagram of pipelining in the CPU of FIGS. 1 to 5; FIG. FIG. 8 is an explanatory diagram showing a diagram of a format of a virtual address used for the CPU shown in FIGS. 1 to 5; FIG. 9 is an explanatory diagram showing a diagram of a format of a virtual address used for the CPU shown in FIGS. FIG. 10 is an explanatory diagram showing a diagram of an address translation mechanism used for the CPU of FIGS. 1 to 5; FIG. 11 is an explanatory diagram showing a diagram of virtual-to-physical address mapping used for the system of FIGS. 1 to 5; FIG. 13 is an explanatory diagram showing a diagram of a process control processor used in the system of FIGS. 1 to 5; FIG. 13 shows the system of FIGS. Illustration showing a table of address space numbers for a working example; FIG. 14 shows a diagram of a translation buffer entry evaluation machine using features of the invention; FIG. 15 shows a translation buffer for another example of the invention; FIG. 4 is an explanatory diagram showing a diagram of an entry.

BEST MODE FOR CARRYING OUT THE INVENTION As shown in FIG. 1, a computer system according to an embodiment of the present invention includes a CPU 10 connected to a main memory 12 by a system bus 11, and a disk memory 13 accessed via the system bus 11. Equipped. In this example, the computer system uses a single CPU, but may have a multiprocessor configuration. In this case, many CPUs 14 also access the main memory 12 via the system bus 11.

Although the CPU 10 is a single-chip integrated circuit device, according to the present invention, the CPU 10 may be a processor configured in an integrated circuit device mounted on a board. A single chip CPU includes an integer execution unit 16 (also referred to as an "E-box") and a floating point execution unit 17 (also referred to as an "F-box"). Fetch and decode instructions are performed in the instruction unit 18 or "I-box". The address unit or "A-box" 19 performs the functions of address generation, memory management, write buffering and bus interface. That is, the virtual address system and the translation buffer according to the present invention are realized by the address unit 19. The memory is hierarchical with on-chip instructions and the data cache is included in the instruction unit 18 and address unit 19 as an example, while the large second level cache 20 is off-chip controlled by the cache controller of address unit 19. Type.

The CPU 10 employs an instruction set in which all instructions have a fixed size, in this case, 32 bits, that is, a single word. Memory references are generally aligned (synchronized) quadwords,
Bytes, words, doublewords and quadwords of the integer data type are processed internally. As used in this example, 1
A byte is 8 bits, a word is 16 bits, ie, 2 bytes, a double word is 32 bits, ie, 4 bytes, and a quadword is 64 bits, ie, 8 bytes. The data paths and registers within CPU 10 are generally 64 bits,
Given the size of a quadword, the main memory 12 and cache use quadwords as the basic unit of transfer. Performance is increased by allowing only quadword or double word loads and memory.

Instruction unit 18, the I-box, is shown in detail in FIG. The primary function of the instruction unit 18 is E-box 16, A-box 16.
Box 19, and F-Box 17. The instruction unit 18 includes an instruction cache 21 for storing 8K bytes of instruction stream data, and loads the instruction stream data into the instruction register 22 in each decoding cycle. In one example, two instructions are decoded in parallel. The instruction is decoded by decoder 23, generating a register address on line 26 and a control bit on microcontrol bus 28.

Instruction unit 18 includes an address generation circuit 29 including a branch prediction circuit 30 in response to instructions in the instruction stream to be loaded into register 22. The branch address is predicted using the branch prediction circuit 30, and the instruction generation circuit 29 prefetches a pre-necessary instruction stream. The previous address generation circuit 29 generates an address of instruction stream data including a virtual PC (program counter) 33.

Also, the instruction unit 18 is provided with a completely associative translation buffer (TB) 36 to cache the latest used instruction stream address translation and protection information for 8 Kbyte pages. A 64-bit address is usually possible, but in practice a 43-bit address is preferred. A virtual program counter 33 is provided for the instruction stream TB36 for each cycle. Page table entry related to address from virtual PC (PT
When E) is cached in the instruction stream TB36, the address translation and access check are completed by the instruction unit 18 using the page frame number (PFN) and the protection bits of the page including the virtual PC. In this way, a physical address is provided to the address input 37 of the instruction cache 21 or, in the event of a cache miss, this instruction stream physical address is provided by the bus 38 to the cache 20 or the main memory 12 via the address unit 19.

The execution unit or E-box 16 is described in detail in FIG. The execution unit 16 is a logical operation device (AL
U) 64 including 40, barrel shifter 41, and integer multiplier 42
Provides a bit integer execution data path. Execution unit 16 also includes a 32-register, 64-bit wide register file 43 including registers R0-R31, all of which are hardwired to zero. This register file
43 has four read ports and two write ports that source (sink) operands (results) to both the integer execution data path and the address unit 19. The bus structure 44 allows two of the read ports of the register file 43 to be applied to the selected input of the shifter 41 or the multiplier 42 as specified by the control bits of the decoded instruction on line 28 from the instruction unit 18. And the output of the appropriate function is connected to one of the write ports of the register file to store the result. That is, the address field from the instruction unit is provided on line 26 to select the register that needs to be used to execute the instruction, and the control bit
The operation of the ALU etc. is specified by 28 and the bus structure 44
Which internal bus should be used.

The A-box or address unit 19 will be described in more detail with reference to FIG. The A-box 19 has five functions: address translation using a data path translation buffer 48, a load silo 49 for inputting data, a write buffer 50 for outputting write data, an interface 51 for a data cache,
And an external interface 52 to the bus 11. This address translation data path has a displacement adder 53 that generates a valid address by accessing the register file 43 via a second set of read and write ports, and data TB48 that generates a physical address on an address bus 554. .

The data path translation buffer 48 has a large number (for example, 3
2) Cache the most recently used data stream page table entry. Each entry supports any of the four granularity hints and a detector 55 is passed from the virtual address bus 56 to the physical address bus 54 in response to the granularity hints described in U.S. Pat. No. 5,47,630. The number of low-order bits of the address is changed.

For read and store instructions, a valid 43 bit virtual address is present on TB 48 via bus 56. When the PTE of the supplied virtual address is cached in the TB 48, the protection bits for the page including the PTE and the address are used in the address unit 19 to complete the address transduction and the access check.

As shown in detail in FIG. 5, the on-chip pipelined floating point unit 17, ie, the F-box
And IEEE floating-point instructions. The floating-point unit 17 has floating-point registers F0 to F3
It comprises a 32-entry 64-bit floating-point register file 61 having a 1 and a floating-point logical operation unit 62. The division and multiplication are performed by the multiplication / division circuit 63. Bus structure 64
Interconnects the two read ports of the register file 61 to the appropriate functional circuits, as directed by the control bits of the decoded instruction on line 28 from the instruction unit 18. The register selected for operation is defined by the output bus 26 from the decoded instruction. Floating point unit 17 receives instructions every cycle, except for floating point divide instructions, which can be received every few cycles. Provide a wait time of at least one cycle for all floating-point instructions,
During this latency, the integer unit can continue to execute many instructions.

In one example, CPU 10 has an 8 kbyte data cache 59 and an 8 kbyte instruction cache 21, the size of which depends on the available chip area. The on-chip data cache 59 is a write-through linear map read allocate physical cache and has 32 byte (1-hexaword) blocks. Accordingly, the system can maintain the data cache 59 in synchronization with the main memory 12 by using an invalid bus (not shown).

Instruction cache 21 can be 8 kbytes or 16 kbytes, or can be larger or smaller depending on the area of the semiconductor IC chip. In the places mentioned above
Although physical addressing by the TB 36 is used, this can be used as a virtual cache. In this case, there is no means for maintaining synchronization with the main memory 12. When the cache 21 is a physical address cache, the chip is provided with a main stage for maintaining synchronization with the main memory: (1) When an entry of the write buffer 50 is sent to the bus interface 52, the address is duplicated. Compare against tags in cache 21 and conditionally invalidate the associated block in instruction cache 21; (2) Invalidate bus connects to instruction cache 2).

The main data path and the register of the CPU 10 have a 64-bit width. Integer registers (also make up the register file)
Each of 43 and each of floating point registers 61 are 64-bit registers, and ALU 40 has 64-bit inputs 40a and 40b and 64-bit output 40c. In effect, the bus structure 44 of the execution unit 16 comprising one or more buses provides a 64-bit wide data path for transferring operands between the integer register (which also comprises the register file) 43 and the inputs and outputs of the ALU 40. Have. The instruction decoder 23 generates a register address output 26, and outputs these register address outputs to an integer register (which also forms a register file) 43 and / or
Alternatively, it is supplied to the addressing circuit of the floating-point register 61, which register operand is used as an input to the ALU 41 or 62, and which register 43 or 61 is used.
Selects the output destination of ALU (or multiple functional units).

The characteristics of the CPU 10 of FIGS. 1 to 6 in this example are its RISC characteristics. The instructions executed by the CPU 10 are always of the same size, in this case 32 bits, instead of being of variable length. These instructions will execute in an average of one machine cycle rather than a variable number of cycles (assuming they are pipelined and not disabled, as described below). The instruction set includes register-register logical operation type operation, or register-memory (or memory-register) load / store type operation, and there is no complicated memory addressing mode such as indirect. ALU40
The instructions that operate on always get their operands from register file 43 (or from their own files) and always write their results to register file 43; these operands are never obtained from memory, and the results are It is never written to the memory of the same instruction exhibiting ALU operation. The loading from the message is always performed to the register of the register file 43 or 61, and the writing to the memory is always performed from the register of the register file.

As shown in FIG. 6, CPU 10 has seven stage pipelines for integer operation and memory reference instructions. FIG. 6 is a pipeline diagram for the pipeline of the execution unit 16, the instruction unit 18 and the address unit 19. The floating point unit 17 defines a pipeline parallel to the pipeline of the execution unit 16, but typically uses more stages for execution. The seven stages are called S0-S6, and one stage needs to be executed in one machine cycle (clock cycle). The first four stages S0, S1, S2 and S3 are executed in the instruction unit 18 and the last three stages S4, S5 and S3
6 is an execution unit 16 or an address unit 19 depending on whether the instruction is one operation or one load / memory.
On one or the other.

The first stage S0 of the pipeline is an instruction fetch or
Instruction stage 18 during the IF stage
A new instruction is fetched from the instruction fetch 21 using the address 33 as a base. The second stage S2 is an evaluation stage in which two fetched instructions are evaluated to see if a double issue is possible.
The third stage S2 is a decoding stage in which the instructions are decoded by the decoder 23 and the control signals 28
And a register address. The fourth stage is a register file 43 for accessing the operation instruction stage and the instruction issue stage. The fifth stage S4 is cycle 1 of the calculation if an operation instruction is present (for example in the ALU 40), and the instruction unit 18 calculates a new PC 33 of the address generator 29; 19 calculates an effective data stream address using the adder 53. 6th stage
S5 is a cycle-2 of the calculation when there is an operation instruction (for example, in the ALU 40), and the data TB48 searches the memory reference stage. The last stage S6 is a write stage of an operation instruction having a register write, in which, for example, the output 40c of the ALU 40 is written to the register file 43 via the write port, and the data cache 59 or the instruction cache for the instruction stream or the data stream reference. 21 hit / miss decision points.

Various types of formats of the instruction set executed by the CPU 10 of FIGS. 1 to 7 are shown in FIG. By using the format of FIG. 7, the CPU of FIG. 1 executes an instruction set including nine types of instructions. These instruction sets are: (1) integer load and store instructions, (2) integer control instructions, (3) integer arithmetic, (4) logical shift instructions, (5) byte operations,
(6) Floating point load and storage, (8) Floating point arithmetic, (9) Others. This instruction set is described in detail in U.S. Pat. No. 5,47,630. 1
One type is a memory (ie, load and store) instruction 70, which is one 6-bit opcode in bits <31:26> and two 5-bit register address fields Ra and Rb in bits <25:21>. , One of bits <15: 0>
This is the displacement of the bit code. This instruction is used to transfer data between the register 43 and the memory (the memory 12 or the cache 59 or 20), load an effective address into the register of the register file 43, and use it for a subroutine jump. The displacement field <15: 0> is a byte offset; this is sign-extended and added to the contents of register Rb to form a virtual address. The virtual address is used as a memory load / store address or as a result value depending on the particular instruction. The branch instruction format 71 shown in FIG. 7 has one 6-bit operation code of bits <31:26>, one 5-bit address field of bits <25:21>, and one 21-bit of bits <20: 0>. This is the displacement of the sign. This displacement is treated as a doubleword offset, which is shifted 2 bits to the left to address the doubleword boundary, sign extended to 64 bits and forming the target virtual address in addition to the PC33 updates (overflow Means ignore).

Actuating instructions 72 and 73 are in the format shown in FIG. 7, where one format 72 has three register operands,
The other format uses two register operands and one literal. The working format is
Perform integer register operation and perform two source operands 1
One destination operand is used for an instruction permitted in the register file 43. One source operand can be a literal constant. Bit -12 indicates whether the operation instruction is for a two-source register operation or 1
Specifies whether one is for one source register and a literal. In addition to the 6-bit operation code of bits <31:26>, the operation format has a 7-bit function field of bits <11: 5> to provide a wide range of choices for logical operation. The source register Ra is specified in each case by bits <25:21> and the destination register R
c is selected by block bits <4: 0>. If bit -12 is zero, source register Rb is defined in bits <20:16>, but if bit -12 is one, the 8-bit zero-extended literal constant is the bit <20:16> of the instruction. 13>. This literal is interpreted as a positive integer in the range 0-255 and zero extended to 64 bits.

FIG. 7 also shows a floating-point operation instruction used for an instruction for operating the floating-point register 61. The floating-point operation instruction includes one 6-bit operation code of bits <31:26> and a bit as described above. <15: 5>. There are also three peland fields Fa, Fb and Fc, each of which specifies either an integer or an instruction defined floating point operand;
Register 61 only has operand fields Fa, Fb and Fc
, These registers may contain integers or floating point values. Literals are not supported. The floating-point conversion uses a subset of the floating-point operating format 74 of FIG. 7 and performs a register-to-register conversion operation; the source is specified by the Fb operand, and the Fa operand must be leg-31 (all zeros). .

The other instruction formats in FIG. 7 indicate for privileged architecture library (PAL or PAL code) instructions which are used for a particular extended processor function. In these instructions, bits <31:26>
Has a 6-bit operation code, and specifies operation by a 26-bit PAL code function field <25: 0>. PAL
Source and destination operands for code instructions are provided in fixed registers specified in the individual instruction details. Normal
PAL code instructions are stored in memory in format 70-7
The multiple instructions of 4 are used to form more complex instructions that are executed in privileged mode, for example, as part of an operating system.
^{26, that} is, 64 instructions are encoded by the 6-bit operation code field <31:26> in the instruction format of FIG. This limits the instruction set to 64 instructions. However, the "function" fields of the instruction formats 72, 73 and 74 allow the instructions having the same operation code in bits <31:26> to be changed. In addition, JS
Try to make a change like R or RET.

The format 76 of the virtual address assigned to the internal address bus 56 is shown in FIG. This address is 64 bits wide, but current practical implementations use addresses that are small enough. For example, a 43-bit address can provide an addressing range of 8 terabytes.
The format depends on the page size used and can include, for example, a byte offset 77 of 13 to 16 bits in size. When the page is 8 Kbytes, the byte-with-in-page field 77 has 13 bits, and for 16 Kbytes, the field 77 has 14 bits. The illustrated format 76 has three segments 78, 79 and 80 labeled Seg1, Seg2 and Seg3 of varying sizes depending on the implementation. For example, segments Seg1, Seg2 and Seg3 can be 10-13 bits. If the size of each segment is 10 bits
The segment length specified by Seg3 is 1K pages, the segment of Seg2 is 1M pages, and the segment of Seg3 is 1G pages. PTE page frame number (PF
N) Fields are always 32 bits; this increases the size of virtual and physical addresses as the size of the page increases.

Although the physical address is at most 32 bits, the processor can implement small addresses by not performing certain numbers of higher order bits. The two most significant execution physical address bits can select a cache strategy or an execution dependent address space. Different implementations may make different uses and restrictions of these bits as appropriate for the system. For example, for a workstation having a 30-bit <29: 0> physical address space, bits <29>
Selects between memory and I / O, and bit <28> is I / O
Cache operations in the space can be enabled or disabled and zeroed in the memory space.

Typically, in a multitasking system, since several processes reside in physical memory 12 (or cache) simultaneously, memory protection and multiple address spaces (using address space numbers) are used by the CPU to Avoid interfacing with any other processes or running systems. In order to further improve the reliability of software, memory access is controlled by four hierarchical access modes (privileged modes). These are privileged from top to bottom. I.e., kernel, run, supervisor and user are related to operating system modes and application programs. Protection is specified at the individual page level, where pages can be inaccessible, read-only, or read / write for each of the four access modes. Accessible pages can be restricted to have only data or instruction access.

The page table entry or PTE 81 stored in the translation table 36 or 48 or in the page table set by the operating system in the memory 12 is shown in FIG. PTE 81 is a quadword (64 bits) wide and has a 32-bit page frame number of bits <63:32>, i.e., PFN82 and software and hardware in field 83 with bits <15: 0> as shown in Table A. With control information, execute protection characteristics and the like.

Translation buffers 36 and 48 are associated with tags, each consisting of a higher order bit of the virtual address,
This PFN stores a number of page table entries 81 assigned by the operating system to this virtual address.
For example, a tag may be configured by fields 78, 79 and 80 for the Seg1, Seg2 and Seg3 values of virtual address 76 in FIG. In addition, it has a valid bit that indicates whether the entry was invalid when the TB was flushed. Conventionally, the TB is flushed to invalidate all entries when a context switch is formed; however, features of the present invention continue to use entries that are still valid, thus improving performance. . For this purpose, a translation buffer
36 and 48 add a 16-bit wide address space number field loaded from the process control block as described below. As shown in FIG. 10, a tag match for the PTE of the translation buffer is searched for using the virtual address 76 of the bus 56 (see FIG. 8), and if this cannot be found, the page table base register is called using the Seg1 field 78. Page table found at the base address stored in internal register 86 to be read
Index to 85. The entry 87 found in the Seg1 index of the table 85 is the base address for the second page table 88, and thus the Seg2 field
Use 79 as an index into entry 89. Entry 89
Points to the base of the third page table 90 and uses the Seg3 field 80 as an index into the PTE 91. The physical page frame number from the PTE 91 is combined with the byte offset 77 from the virtual address and the adder 92 to generate a physical address on the bus 54. As described above, the size of the page mapped by the PTE and the size of the byte offset 77 are changed depending on the granularity hint.

In addition to matching the tag field of virtual address 76 with the tag field of translation buffer 36 or 48, the address space number stored in the translation buffer is one of the internal processor registers.
This is compared with the address space number of the current state of the CPU 10 stored in the ASN register. If the address space match field (bit <4>, A) is cleared (zero), the current ASN and field 94 need to match for the PTE to be used, but the address space match field is set ( If it is a logical 1) no match is needed, ie the address space number will be ignored. However, a particular feature of the present invention is the additional matching disable bit 96 stored in each PTE, which allows the address space matching feature to be under certain conditions (ie, when the virtual machine monitor process is running). Disable.

A match disable bit need not be maintained in each entry of the translation buffer. Whether address space matching should be disabled is a function of the CPU's execution environment rather than the virtual address's execution environment. Address space matching is disabled when the virtual machine monitor is running (as described below); when a process with a virtual machine, ie, a VM, is executed, address space matching is enabled. . In another example of the invention, the match disable bit is stored globally in a translation buffer. In yet another example of the present invention, the match disable is maintained on the CPU itself. In each case, the value is from VMM to VM,
Or it changes at the transition from VM to VMM, and its current value must be used for the transition comparison logic of the translation buffer.

The CPU 10 first forms a virtual address 76 on the bus 56 and either represents the address within the entire virtual range 97 defined by the associated 43-bit address width as shown in FIG. 11, or the address width used by the operating system. Generate memory references by representing parts. Thus, the virtual address is translated to the physical address represented by the address map 98 by using the page tables 85, 88, 90 of the memory or by using the translation buffers 36 or 48;
Mandated by 12 sizes. Since the translation is performed for each page (for example, an 8K byte block), the virtual page address for the page 92 of the virtual memory map 97 is translated to the physical address 99 'for the page (referred to as a page frame) of the physical memory map 98. Is done. The page table is maintained in the memory 12 or cache 20 to translate between virtual and physical addresses, and the translation buffer contains the most recently used translation, including the CPU, and in most cases data A reference to the page table in memory 12 is not necessary to obtain the translation before making the reference; that is, the time required to make a reference to the page table in memory 12 is sufficient to obtain the translation from the translation buffer. It will be much longer than required. Only pages used by the currently executing task (and the actuation system itself)
Will be in the physical memory 12 at a given time: the translation to the address 99 'will be in the page table 8 for only those pages that actually exist in the physical memory 12.
5,88,90. If the page referenced by the CPU 10 is not found in the physical memory 12, a page fault is performed to initiate a swap operation where the page from the physical memory 12 is replaced with the desired page held in the disk memory 13, The exchange takes place under the control of the operating system. The physical memory 12 used by the operating system kernel or the page tables 85, 88, 90 themselves or the pages are in fixed locations and will not be swapped to disk 13 or will be moved to other page translations; Of the physical memory 12 can be moved freely by simply maintaining the updated page table.

A process (or task) is a basic entry planned for execution by the CPU 10. A process represents a single thread of execution and consists of an address space and both hardware and software contexts. The hardware context includes an integer register (which also forms a register file) 43, a floating-point register 61, a processor state included in an internal processor register, a program counter 33, four stack pointers, a page table base register 86, and an address space number 95. Other
It is specified by a value that depends on the CPU design. The software context of the process is defined by the operating system software and is system dependent. A process shares the same address space with other processes or has its own address space; however, this is not a separate address space for system software, so the operating system maps to each process's address space. There is a need. To be able to execute a process, its hardware context must be loaded into the integer registers (which also make up the register file) 43, floating point registers 61 and internal processor registers.
As the process runs, its hardware context is such that as various registers are loaded and written,
Updated continuously. If the process is not executed, its hardware context will be stored in memory 12.
Save the hardware context of the current process in memory,
Loading the hardware context of the new process is then called context exchange. Context exchange occurs as a process after being scheduled by the operating system for execution. The hardware context of a process is defined by privileged and unprivileged contexts. When the process is not being executed, this privileged portion is stored in the memory of the 128-byte block 100 as shown in FIG. 12, and the context is exchanged by the privileged instruction. One block for each process
There are 100.

As shown in FIG. 12, the context block 100 includes a field 101
Contains four stack pointers, which are stack pointers for the kernel, execution, supervisor and user. Page table base register
86 is in the field 102. The address space number for this process (to load into register 95) is in field 103. The other fields 104 are not used for these values. The location of this block 100 of memory is specified by the context block base register 105 for the current process. The swap context instruction supplies the privilege context of the current process to the context block identified by this register 105 and adds a new value to register 10
5 and then load the privilege context of the new process from the new block 100 into the appropriate hardware register (which also comprises the register file) 43, etc.

The architecture described above reduces the need for invalidating cached address translations in the translation buffer for process-defined addresses when the processor executes address space numbers (process tags) and context switches occur. The address space number for the current process is loaded into internal processor register 95 by a privileged instruction from field 103.

In FIG. 9 and page table entry 81 in Table A,
There is a field (bit <4>) called "Address Space Match". This feature causes the location of the system's virtual address space 97 to be shared by all processes by the operating system. Such virtual addresses will be associated with the same physical address in the address space of each process.

1-5 may employ a "virtual machine system", which uses a combination of hardware, firmware, and software mechanisms to operate independently, each running on the same physical computer. Simulated multi-computer or virtual computer illusions. A set of virtual machines (VMs) is similarly generated by the virtual machine system, and a set of independent user processes is generated by the time-sharing system. Virtualization via the architecture of FIGS. 1-5 requires that the virtual machine be provided with address-space-matching characteristics via hardware means from a performance and functional point of view.

A virtual machine is a CPU called a virtual machine monitor (VMM)
Generated by layers running on. The VMM is under hardware control and includes memory management (address translation and protection mechanisms) and page tables. Each virtual machine runs in a separate virtual address space in the range 97 and has a separate set of address space numbers assigned by the VMM. VMM itself runs on a separate set of virtual address spaces in the 97 range. It is an object of the present invention to reduce the performance of the system so that virtual machines can be run in kernel mode so that they can execute privileged instructions (otherwise traps for these operations must be used with a significant performance penalty). I do. That is,
For this purpose, VMM needs to suppress VMs. The problem required to implement the present invention is to keep the address space of several VMs and VMMs separated from each other, while at the same time maximizing system performance by providing matching functions in TB to VMs . Yet another limitation to solving the problem is that VMs and VMMs want to use the same virtual address for different purposes. Therefore, allocating an individual address area to the VMM from the address allocated to the VMs does not solve the problem.

1 shows an example of the present invention. 15 address spaces ASN used in software by hardware
0 to ASN-14N-14 shall be used by the VMM. The system in this example runs 5 user processes each 2
There are two virtual machines A and B. The possible allocation of address space to this virtual machine causes the address spaces ASN-1 to ASN-6, ASN-7, ASN-8, ASN-10 and ASN-11 to be directed to the VMB. This example is shown in FIG.

To ensure the safety and integrity of the system,
Two virtual machines need to be completely independent. This means that each of these memories cannot reference another memory. Similarly, the VMM memory needs to be independent of the virtual machine. However, within a virtual machine, the address space matching feature works correctly and shares memory with individual processes under the control of each VMs operating system.

Each address space is assigned to an address space number (hereinafter, referred to as ASN) by a proper translation buffer design. Part of the CPU status information is the currently executing entry or ASN assigned to the process register 95. TB entry is ASN of address space
Along with field 94, and these entries belong to this address space. In addition, TB (Table A, ASN bit <4>) has one bit or field,
This indicates that the entry matches any address space, effectively overriding the ASN94 tag.

This kind of TB can be used for virtual machine systems with a significant performance penalty. To make a memory isolation request, the TB must: (1) have any entry in the TB with a match field (bit <4>) indicating all matches; and (2) have any match in the next event. Need to flush completely when things happen. These events are: (a) the entry currently running on the real machine changes from one VM to the other,
(B) The entry currently executed in the real machine changes from a certain VM to a VMM, and (c) the entry currently executed in the real machine changes from a certain VMM to a VM. To minimize TB flash, and thus improve overall system performance, impose certain restrictions on the VMM and vary the TB configuration in accordance with the present invention. The limitation imposed on VMM is that it is necessary to use a disable matching property. This ensures address space matching characteristics for use by virtual machines, and VMM addresses are not mapped by TB, even with matching field sets.

The TB itself can be changed by adding another part of the so-called "disable matching" CPU state, field 96 of FIG. The VMM determines the value of the disable matching field 96 based on the pre-address space and supplies the current value to the TB. This field 96 is a flag that can be set or cleared. When the disable match field 96 is cleared, the TB matches the reference if the address is correct, and (1) TB
The ASN of the entry matches the current ASN of the CPU, and (2) the matching field of the TB entry is set.

As shown in FIG. 14, the logic performed in accordance with the present invention can be represented by the following relationship:

IF (ADDR.TAG = TB.TAG) & ((CPU.ASN = TB.ASN) | (TB.ASM & NOT TB.DIS) THEN MATCH where ADD.TAG is the tag field 78,7 of the virtual address 76
9,80, TB.TAG is the translation buffer tag 93, and CPU.ASN is the value stored in the processor register 95 from the control block field 103, TB.ASN
Is the address space number stored in the translation buffer field 94, and TB.ASM is the disable bit of the translation buffer field 96. These values are the logic circuit of the A-box in FIG.
A matching signal is provided to 106 to indicate whether the PTE selected by the TB needs to be used.

The logic of the form of the expression given in the previous section, implemented in circuit 106, can be represented by the following truth table. (In each case, the address tags match.) When disable match field 96 is set,
The TB matches the reference when the address is correct and the ASN94 of the TB entry matches the current ASN95 of the CPU. In effect, the disable match status bit 96 overrides the TB match field.

In order to use the modified design, the disable match bit 96 is added by the VMM to the VMM itself (ASN-0 in the example described above).
And set to all of the other ASNs directed to ASN-9 and disabled match bit 9 by the VMM.
Clear 6 for all other ASNs. As long as the CPU executes either the VMM or the same VM / process in the same context, one key feature of the disable match bit 96 is that its value remains constant. Therefore, the value of the bit need not be calculated during the memory reference. Instead, depending on the particular TB design, its value can be calculated and loaded when the TB entry is stressed or when the CPU changes context. The result of the change design according to the present invention is that the TB is
It only needs to be flushed when changing from one VM to the other.

In another example of the present invention, a multi-bit field for the virtual machine number VMN is added to each translation buffer entry as shown in FIG. 15 instead of the single-bit disable indicator as described above.
Similarly, the multi-bit virtual machine number VMN is added to the CPU state of the internal processor register and also to the ASN94 field. The translation buffer then comprises a logic portion that matches the virtual address of the tag and also has a logic portion that matches the ASN and matches by the virtual machine number as described above. The executed logic part is represented as follows.

IF (ADDR.TAG = TB.TAG) & (CPU.VMN = TB.VMN) & ((CPU.ASN = TB.ASN) | (TB.ASM) THEN MATCH CPU.VMN is stored here as machine state Is the virtual machine number, and TB.VMN is the VMN field of the translation buffer entry.

In this example, each VM is assigned to one (or more) VMNs, each holding the act of using the VMN individually. However, the translation buffer does not need to be cleared when the switching between the VMs is arbitrarily performed in the example described above. An additional advantage is that translation buffer entries can be shared during the process using address space matching for the virtual machine monitor. The disadvantage of this example is that it requires more bits for the translation buffer entry.

The invention is not limited only to the examples described above,
Various modifications or changes are possible without changing the sheet.

Table A Page Table Entry The page table entry fields are interpreted as follows.

Bit Decision <0> Valid (V)-Indicates the validity of PEN <1> Read failure (FOR)-Position read on page generated at trial other than FOR when set <2> Write failure (FOW)-FOW when set <3> Execution failure (FOE)-This PTE matches all address space numbers. VA, ASNha considered in all processes <4> Address space matching (ASM)
TE matches all address space numbers. VA and ASM are considered in all processes. <6: 5> Granularity hint (GH)-software sets these bits to non-zero values and provides hints to the translation buffer so that blocks of pages are Treated as a large page.

<7> Save for future use. <8> Kernel readable (KRE)-This bit is read from kernel mode. If this bit is 0 and
An access violation occurs if LOAD or instruction fetch is attempted in kernel mode. This bit is valid even when V = 0.

<9> Read executable (ERE)-This bit is readable from Run mode. If this beam is 0 and LOAD or instruction fetch is attempted in execute mode, address violation will occur. This bit is valid even when V = 0.

<10> Supervisor Readable (SRE)-This bit is read from supervisor mode. This beam is 0
If a LOAD or instruction fetch is attempted in supervisor mode, an address violation will occur. This bit is valid even when V = 0.

<11> User Readable (URE)-This bit is read from user mode. If this beam is 0 and a LOAD or instruction fetch is attempted in user mode, an address violation will occur. This bit is valid even when V = 0.

<12> Kernel writable (KWE)-This bit is written from kernel mode. When this beam is 0 and STORE is attempted in kernel mode, address violation occurs. This bit is valid even when V = 0.

<13> Execute write enable (EWE)-This bit is written from execute mode. If this beam is 0 and STORE is attempted at run time, address violation will occur.

<14> Supervisor write enable (SWE)-This bit is written from supervisor mode. This beam is 0 and ST
If ORE is attempted at supervisor time, address violation will occur.

<15> User writable (UWE)-This bit is written from user mode. If this beam is 0 and STORE is attempted at user time, address violation will occur.

<31:16> Reserved for software. <63:32> Page frame number (PFN)-The PFN field always points to the page boundary. When V is set,
The PFN is concatenated by the byte-in-page of the virtual address to obtain the physical address. When V is cleared, this field can be used by software.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Wi-Tech Richard Tea USA Massachusetts 01460 Littleton Silverbird Lane 8 (72) Inventor Robinson Paul Tee Massachusetts USA 02174 Arlington Gardner's Treat 61 (56) References JP1 -255945 (JP, A) JP-A-61-206057 (JP, A) JP-A-62-212746 (JP, A) JP-A-59-218693 (JP, A) JP-A-60-171552 (JP, A) )

Claims (4)

(57) [Claims] 1. A method of operating a processor comprising a translation buffer for translating a virtual address to a physical address, the translation buffer having a plurality of page tables each containing a page frame number indexed by a virtual address tag. The translation buffer also stores an address space number and an address space match entry for each page table entry, where the address space number corresponds to a process executed on the processor. A value, wherein the matching entry has a value indicating that the address space number needs to be matched and a field having another value indicating that the address space number does not need to be matched. And having the processor store a current number as a value reflecting the state of the processor, indicating certain conditions that the matching entry needs to be disabled and other conditions that do not need to be disabled. Storing a third match value, comparing the virtual address tag with a virtual address field generated by the processor, and comparing the address space number with the current number;
If there is a match in the comparison of the virtual address tag and the field of the virtual address; if the match occurs by comparing the address space number with the current number, and if the match entry is the certain value, the memory Use the page frame number for reference; and if the third match value indicates the certain condition, even if the match entry is the other value, the address space number is the same as the current number. A method of operating a processor, comprising the steps of using a page frame number for memory references, whether matched or not. 2. In operating a processor system having a CPU and a memory having a translation buffer for translating a virtual address to a physical address, a plurality of page table entry numbers are stored in the translation buffer. An entry characterizes a location in the memory referenced by the page frame number, including a virtual address tag, a page frame number and an address space number; and in the translation buffer for each page table entry: a) a value indicating that the address space number needs to match a current value stored as part of a state of the processor, and that the address space number does not need to match the current value. Other A first value specifying that stores an address space alignment indicia and a value, to further (b) is operated to entry the address space matching indicator,
Storing a match disable indication having a second value indicating that the address space match indicator need not be activated for an entry; and a field of a virtual address generated by the processor, and a page of the translation buffer. A comparison step of comparing a table entry with one virtual address tag; said comparison step indicating a match, said address space match indication being another value, and said address space number being part of a state of said processor. Using the page frame number to address the memory when matching with the stored current value; the address when the comparing step indicates the match and the address space match indication takes on the certain value. Space number matches the current value Using a page frame number to address the memory, whether or not; if the comparing step indicates a match and the match disable indication is a second value, the address space match indication is at the certain value. Processor system operation, characterized in that a page frame number addressing the memory is used only when the address space number matches the current value, regardless of whether it is or the other value. Method. 3. The processor includes a translation buffer for translating a virtual address to a physical address, the translation buffer storing a plurality of page table entries, each page table entry being a page indexed by a virtual address tag. Addressing means including a frame number; the translation buffer comprising an address space number storing means for each of the page table entries;
Address space matching entry storage means, and storage means for a matching disable indicator, wherein the address space number corresponds to a process executed by the processor, and the matching entry requires that the address space number be matched. A field having a value indicating that there is one and another value indicating that the address space number does not need to be matched, wherein the match disable indicator is a first value indicating that the match entry is ignored And an indication having a second value indicating that the matching entry should not be ignored; and means for maintaining in the processor a current number representing the address space number as part of a state of the processor; Generated by said virtual address tag and said processor First means for comparing the address space number with a current number; and both the first and second comparing means generate a match, The addressing means uses the page frame number for memory references when the match entry is the certain value; the means for comparing the virtual address tag with the field of the virtual address generates the match and the match entry is If the other value, if the disable indicator is not set to the other value, the second comparing means determines whether the address space number matches the current number. Regardless, the address designating means uses the page frame number for memory reference. Processor. 4. A processor system having a CPU and a memory, comprising: a) fetching an instruction from the memory in the CPU, decoding the instruction in the CPU, and accessing a memory of read and write data in the CPU. Means for executing instructions; b) means for generating virtual addresses in the CPU for use in fetching the instructions and accessing the data memory; c) different pages stored in the memory, each of which being a different page of the memory. Means for translating a virtual address to a physical address for said memory, including a translation buffer for storing a plurality of said page table entries; E) the page from the translation buffer Means for addressing memory using a frame number and a portion of the virtual address; f) said translation buffer stores an address tag and an address space number for each page table entry and an address space matching entry. Where the address space number is the CPU
And a value indicating that the address space numbers need to be matched, and another value indicating that the address space numbers do not need to be matched. And the translation buffer also stores a matching disable indicator for each page table entry and is held as part of a state of the CPU by means for storing a current value in the CPU. G) comparing the address tag with a field of the virtual address generated by the CPU in a translation buffer and maintaining the address space number and a portion of the state of the CPU. With means for comparing also with the current number; When both of the comparing operations by the comparing unit generate a match and the matching entry is the certain value, the address specifying unit uses a certain page frame number for memory reference; If the match with the field results in a match and the match entry is the other value, then setting the disable match indicator will determine whether the address space number matches the current number. Processor system, wherein the address designating means uses the page frame number for the memory reference.