JP2609934B2 - Sync recovery circuit to recover word sync - Google Patents

Description

The present invention relates to a synchronization recovery circuit and a radio communication device using the same, and more particularly, to a synchronization recovery circuit in a cellular communication system. The present invention relates to a synchronization recovery circuit for detecting a word synchronization character and recovering word synchronization, and a wireless communication device using such a synchronization recovery circuit, such as a mobile phone or a mobile phone.

(B) Conventional technology Conventionally, a cellular communication system has been widely used as a mobile radio telephone such as an automobile telephone or a mobile telephone. In such a cellular communication system, an area to be covered is divided into a large number of cells, and a radio base station is provided and a group of channels is assigned to each cell. By keeping the coverage of each cell small and reducing the transmission output of the base station, frequent reuse of frequencies becomes possible, and the number of subscribers can be increased.

In such a cellular communication system, when a mobile station equipped with a wireless communication device, for example, an automobile equipped with an automobile telephone device, moves from one cell to another cell, the mobile station and the corresponding wireless base station are connected. Various kinds of digital control such as channel change are performed to perform complete communication with the car telephone device.

Each radio base station has two types of radio channels, one is a two-way control channel for various digital controls as described above, and the other is a two-way voice channel for telephone conversations. is there.

Four signal paths are used for such bidirectional communication. That is, the control channel includes a forward control channel (FOCC) used for communication from the radio base station to each mobile station and a reverse control channel (RCC) used for communication from each mobile station to the radio base station.
C) is mainly used for various controls before the voice channel is established, and is not used for conversation. The voice channel includes a forward voice channel (FOVC) used for communication from the radio base station to each mobile station.
And a reverse voice channel (RVC) used for communication from each mobile station to the radio base station.

In these channels, the message or data signal has word synchronization characters and is transmitted at a predetermined word rate and bit rate. Therefore, in the wireless communication device of the mobile station, it is necessary to first detect the word synchronization character from the received data signal to recover the word synchronization. For this reason, in a conventional wireless communication device, for example, as disclosed in U.S. Pat.No. 4,029,900, a synchronization recovery circuit for detecting a word synchronization character from a data signal and recovering word synchronization is provided. In the synchronization recovery circuit, a word synchronization signal based on the detected word synchronization character is supplied to a control circuit for data processing to recover word synchronization.

However, the conventional synchronization recovery circuit is configured to serially supply a word synchronization signal to the control circuit due to its hardware configuration. Therefore, in order to recover the word synchronization based on the serial word synchronization signal, the data signal must also be serially applied to the control circuit. The control circuit serially receives the word synchronization signal and the data signal, and fetches and uses the data signal after the word synchronization position is determined as valid data. In such a configuration, when the data rate is high, such as in a cellular communication system, if a data signal is read after word synchronization is achieved, data loss may occur. Therefore, the control circuit must always access the data signal. During that time, the control circuit cannot execute other processing such as key scan, LCD display, AF (analog frequency) processing, wireless function processing, and the like. There was a problem that various processes could not be performed at high speed.

In order to solve such a problem, the control circuit may be constituted by two microprocessors, on the one hand, the synchronization recovery processing of the received data may be performed, and on the other hand, other processing such as key scanning may be performed. For example, there is a problem that complicated control such as communication control (for example, determination of a communication protocol) between two microprocessors and timing control is newly required.

On the other hand, a technique has been proposed in which a data signal is converted from serial to parallel and then supplied to a control circuit.
No. 63-245032. However, as long as the word synchronization signal is supplied serially, it is impossible to confirm the synchronization position of the parallel data signal as it is, and processing by some software method in the control circuit is essential. Therefore, in such a technique,
It is difficult for a wireless communication device to operate at high speed.

(C) Problems to be Solved by the Invention An object of the present invention is to speed up various processes of a wireless communication device in a cellular communication system.

Another object of the present invention is to enable recovery of word synchronization of received data by parallel signal processing in a wireless communication device as a mobile station.

(D) Means for Solving the Problems In summary, the present invention converts serial data including a predetermined word-synchronous character into n-bit (n is an integer of 2 or more) first parallel data and converts the serial data into n-bit first parallel data. The n-bit second parallel data indicating the word synchronization position in one parallel data is generated, and the word synchronization of the serial data is recovered based on the first and second parallel data. .

(E) Function The present invention is configured as described above, and processes both the received data signal and the word synchronization signal indicating the word synchronization position as parallel data.

(F) Example An example of the present invention will be described below with reference to the drawings. In the embodiment described here, the forward control channel (FO
CC) shows the case where the present invention is applied. In this forward control channel, a forward control channel message (baseband data signal) is transmitted from the wireless base station, and the mobile station (wireless communication device) that has received the forward control channel message performs various processes such as registration and channel change according to the message. I do.

FIG. 1 is a diagram showing a typical format of such a forward control channel message.
This message is basically a bit sync field,
It consists of a word synchronization field and a data message. More specifically, as shown in FIG. 2 (a), the bit synchronization field is a 10-bit field in which 1s and 0s are alternately arranged (known as dotting). Next, as shown in FIG. 2 (b), the word synchronization field is an 11-bit field, and has a bit arrangement that hardly occurs in a voice message. For example, the United States of America has an array of "11100010010" as shown in FIG. Next, the data messages are each 40
Including bit data messages A and B,
It is repeated five times alternately. (Respectively, A _{1 to} A ₅ and
Represented as B ₁ ~B _5). The reason that the data message is repeated five times in this way is for error correction. When there is a difference between the received data, the data message is repeated by 3/5 or more.
That is, the validity of the data is determined by majority decision.

Although not shown in FIGS. 1 and 2, in the bit synchronization field, the word synchronization field and each data message, one busy-idle bit is added for every 10 bits. This busy-idle bit is for notifying the mobile station of the acceptance state of the radio base station that is the source of the message, that is, the idle state of the reverse control channel (RCC). Thus, the bit sync field, word sync field and data message are actually
It will be composed of 11 bits, 12 bits and 44 bits, respectively. The message shown in FIG. 1, for example, in the United States is subjected to well-known Manchester encoding, and is transmitted at a rate of 10 kilobits / second.

Next, FIG. 3 is a schematic block diagram of a wireless communication apparatus as a mobile station in a cellular system according to an embodiment of the present invention. In FIG. 3, the antenna 3 is connected to the receiver 1 and the transmitter 2 through an antenna duplexer 4. The receiver 1 FM-demodulates a signal from a wireless station received by the antenna 3. Then, the receiver 1 uses a discriminator (not shown) to supply the data signal of the forward control channel to the data receiver 6 and to provide the received voice signal of the forward voice channel to the voice processing unit 5. The data receiver 6 detects a word synchronization character from the given FCC message, and supplies a word synchronization signal together with a data signal to a control circuit 8 including an 8-bit microprocessor. After confirming the synchronization position of the data signal based on the given word synchronization signal, the control circuit 8 executes various controls according to the data signal. Control circuit 8
Performs other necessary processing and control for the key matrix 11, the LCD driver 12, and the like. On the other hand, the audio processing unit 5 amplifies the received audio signal of the given FOVC,
This is given to the speaker 10 of the handset. This allows the user of the mobile station to receive a call from the other party.
The control circuit 8 also controls the audio processing unit 5 such as a muting instruction. The data transmitter 7 performs Manchester encoding of the data signal from the control circuit 8 and performs RCC
As a message to the transmitter 2. On the other hand, the audio processing unit 5 processes the user's audio signal given via the microphone 9 and gives the RVC transmission audio signal to the transmitter 2. The transmitter 2 FM-modulates these messages and transmits them to the base station via the antenna 3.

The radio base station of each cell is connected to a mobile telephone exchange (MTSO) (not shown) via a conventional terrestrial line or microwave network. The MTSO is further connected to the public switched telephone network (PSTN) to achieve an interface between the mobile radiotelephone and the PSTN.

Next, FIG. 4 is a block diagram showing the internal mechanism of the data receiver 6 shown in FIG. 3, and FIGS. 5 to 10 are block diagrams showing the details of each part thereof. Also,
FIG. 11 is a timing chart showing signals of the data receiver 6, and FIG. 12 is a diagram schematically illustrating the operation principle.

First, a forward control channel message transmitted from a radio base station (not shown) is
Demodulated and extracted by LPF13. The analog forward control channel message extracted by LPF13 is
After being digitized by the limiter 601, a clock signal generating circuit is used as a data signal in Manchester code format.
602 and a Manchester decoder 603. The clock signal generation circuit 602 is formed of a known PLL circuit, and generates a clock signal RT (FIG. 11 (b)) that is bit-synchronized with the data signal in the Manchester code format. The clock signal RT is supplied to the Manchester decoder 603 and the inverter 607, and also to a delay circuit 608 and a word synchronization detection shift register 621, which will be described later. Also,
The Manchester decoder 603 uses the data signal and the clock signal R
The data signal in Manchester code format is converted to NRZ according to T.
The data signal is converted into a data signal of a format (FIG. 11 (a)) and supplied to a serial-parallel converter 604. The serial-parallel converter 604 has a function as a 16-bit shift register, and converts serial NRZ data from the Manchester decoder 603 into 16-bit parallel data.

FIG. 5 is a diagram showing a configuration of the serial-parallel converter 604. As shown in FIG. 5, the serial-parallel converter 604 is constituted by two 8-bit shift registers 605 and 606, and the clock terminal of each shift register is connected to the output ▲ ▼ of the inverter 607 (FIG. 4). 11 (c) is supplied. Therefore, shift register 60
5 and 606 both operate at the timing of ▲ ▼. That is, the shift register 605 at a timing of RT, with writes sequentially read the NRZ data, provides an output Q ₇ to the data input of the shift register 606. The shift register 606 also, ▲ ▼ writes sequentially read the output Q ₇ of the shift register 605 at the timing of. As a result, the NRZ data from the Manchester decoder 603 is 16-bit parallel data.
Is converted to Q ₀ to Q _15, of which, 8-bit data Q ₀ to Q ₇ output from the shift register 605 is applied to both the delay circuit 608 and the word synchronization detecting circuit 611, is outputted from the shift register 606 8 Bit data Q _{8 to} Q ₁₅ are provided to word synchronization detection circuit 611. In addition, FIG.
FIG. 3 is a diagram showing a configuration of the 8-bit shift register 605 or 606 shown in the figure, which is composed of eight flip-flops connected in series.

Returning to FIG. 4, 16 of the serial-parallel converter 604
The output of the bit is applied to the word synchronization detection circuit 611. The word synchronization detection circuit 611 detects a word synchronization character based on these data. More specifically, the word synchronization detection circuit 611 includes the last 4 bits of the 10-bit bit synchronization field shown in FIGS. 1 and 2, and an 11-bit word synchronization field. A 15-bit word synchronization character "1010 (bit synchronization field) 11100010010 (word synchronization field)" is detected. Generally, 10
The word synchronization character may be composed of only the word synchronization field of bits. However, as described above, the last four bits of the bit synchronization field are added to the original 10 bits of the word synchronization field, and By increasing the number, the probability that the word synchronization character coincides with the data of the data message part by chance is reduced, and the accuracy of the word synchronization detection is increased.
Then, the output signal of the word synchronization detection circuit 611 is read into the word synchronization detection shift register 621 at the timing of the clock signal RT.

FIG. 7 is a diagram showing details of the word synchronization detection circuit 611 and the word synchronization detection shift register 621. 7, the word synchronization detection circuit 611 is composed of inverters 612 to 619 and an AND gate 620. AND
Gate 620 includes Q ₁ , Q ₄ , Q ₈ , Q ₉ , Q ₁₀ , Q ₁₃ , and Q ₁₅ that are the outputs of serial-to-parallel converter 604, and outputs Q ₀ ,
The logical product of Q ₂ , Q ₃ , Q ₅ , Q ₆ , Q ₇ , Q ₁₂ and Q ₁₄ and the inverted signal is obtained. The output Q of the serial-parallel converter 604
_11, busy described above - an idle bit, because unrelated to the word synchronization, the output Q ₁₁ is not connected to the AND gate 620. Therefore, the serial-parallel converter
The values of the outputs Q _{15 to} Q ₁₂ and Q _{10 to} Q ₀ of 604 are “101011100010010”, which is the above-mentioned 15-bit word synchronization character.
Only when becomes, all inputs of AND gate 620 are "1"
The output “1” indicating the detection of the word synchronization character is obtained from the AND gate 620. As shown in FIG. 7, the output of the AND gate 620 is sequentially sent to the word synchronization detection shift register 621, which is an 8-bit shift register, at the timing of the clock signal RT, that is, with a half cycle delay from ▲. Read, 8-bit parallel data WS ₀
It is converted to ~WS _7. Then, the 8-bit parallel data WS ₀ to WS ₇ is applied to the word synchronization detection output port 622. Output port 622 is the output of inverter 607
At the timing of the output ラ ッ チ (FIG. 11 (d)) obtained by dividing ▼ by 8 by the frequency divider 610, the 8-bit input data is latched simultaneously.

On the other hand, outputs Q _{0 to} Q ₇ of the 8-bit shift register 605 of the serial-parallel converter 604 are provided to the delay circuit 608. The delay circuit 608 is an 8-bit buffer register composed of eight flip-flops as shown in FIG. 8, and similarly to the above-mentioned word synchronization detection shift register 621, a clock delayed by a half cycle from at the timing of the signals RT, writing simultaneously read the 8-bit data Q ₀ to Q _7. That is, the 8-bit register 608 is a timing register provided for synchronizing with the word synchronization detection shift register 621. The outputs RD _{0 to} RD ₇ of the shift register 608 are provided to a reception data output port 609. The output port 609 simultaneously latches 8-bit input data at the timing of ▲, which is the output of the frequency divider 610, similarly to the output port 622 described above.

Reading from output ports 609 and 622 is performed by address signals ▲ ▼ and ▲ from 2-bit address line 624.
The output of each output port is transmitted to the control circuit 8 of FIG. 3 via the 8-bit data bus 623.

FIG. 9 is a block diagram showing details of these output ports 609 and 622. In FIG. 9, the output port 609
Is a clock ▲ ▼ timing from the frequency dividing circuit 610 includes an 8-bit output RD ₀ ~ Rd ₇ 8-bit three-state buffer register for latching the 609a of the delay circuit 608, read written data is read signal ▲ The 8-bit data signals D ₀ to D ₀ to in response to ▼ and the address signal ▲ ▼
As D _7, is read to 8-bit data bus 623. Further, the output port 622 also clocks ▲ ▼ at the timing, the word includes 8 bits output WS ₀ to WS ₇ the 8-bit latches three-state buffer register 622a of the synchronism detecting shift register 621, read written data is ,
An 8-bit data bus as an 8-bit data signal according to the read signal ▲ ▼ and the address signal ▲ ▼
Read to 623.

FIG. 10 shows the three-state buffer register of FIG.
FIG. 9 is a diagram showing the configuration of 609a or 622a, which includes eight flip-flops provided in parallel and a gate provided for each Q output of the flip-flops. To prevent a short circuit via the 8-bit data bus 623, the output port 609
And 622 are configured such that the gates are opened only when output activation is sequentially instructed at different timings, and the data in the buffer register is read out to the data bus 623.

FIG. 12 (a) shows NRZ data output in parallel from the reception data output port 609 every 8 bits.
FIG. 2B shows word synchronization data output in parallel from the word synchronization detection output port 622 every 8 bits. As apparent from the above description and FIG. 12, the synchronization data output from the output port 622 has the word synchronization determination flag “1” at a position corresponding to the word synchronization position in the output signal from the output port 609. .

Next, FIG. 13 is a diagram showing the connection relationship between the control circuit 8 of FIG. 3 and the peripheral units.
Is realized by a microcomputer as shown in FIG. The control circuit 8 receives a clock signal from the data receiver 6.
▼ is received as an interrupt request and the data bus
623 via a receive received data or synchronization data D ₀ to D ₇ of the 8-bit described above. On the other hand, the control circuit 8 supplies the above-mentioned address signals ▼ and ▼ to the data receiver 6 via the 2-bit address line 629. The control circuit 8 also provides a read signal RD to the aforementioned output ports 609 and 622. Further, the control circuit 8 supplies necessary signals to the audio processing unit 5, the data transmitter 7, and the LCD driver 12, controls their operations, and further monitors the operation of the key matrix 11.

Next, FIG. 14 is a flowchart for explaining the operation of the control circuit 8. Hereinafter, the operation of the control circuit 8 will be described with reference to FIG. 13 and FIG.

First, the control circuit 8 resets a flag register F (not shown) (step S-1) and determines whether or not there is an interrupt request based on the output signal RT8 from the frequency divider 610 in the data receiver 6. (Step S-2). Then, if requested, other processes such as key scan, LCD driving, audio processing, etc. are interrupted, and the received data of 8 bits transmitted from the data receiver 6 via the data bus 623 (see FIG. )) And 8-bit synchronous data (FIG. 12 (b)) are read (step S-3). Then, it is determined whether or not the read 8-bit synchronization data includes a word synchronization determination flag "1" as shown in FIG. 12 (b) (step S-).
4) If not, go to step S-2 via step S-9
Return to

On the other hand, if it is determined in step S-4 that the synchronization data contains the word synchronization determination flag, the bit position of the flag is detected (step S- 4).
5) The received data after the bit position is stored as valid data in the memory in the control circuit 8 (step S).
-6). Thus, once word synchronization is established,
A flag is set in the aforementioned flag register F (step S-7).

Thereafter, when there is an interrupt request (step S-2), the received data is stored in the memory (steps S-6 and S-10) regardless of the presence or absence of the word synchronization determination flag, and reading of all the received data is completed. Upon completion (step S-11), data processing such as deletion of a busy-idle bit and error correction is performed (step S-12). The determination of the completion of reading in step S-11 can be made by providing a word counter that is incremented each time one word (8 bits) of data is taken in, and monitoring the count value.

Next, FIG. 15 is a flowchart showing another example of the processing of the control circuit 8. In the example shown in FIG. 15, when it is determined that there is an interrupt request (step S-12), first, all the received data and the synchronous data are read, and as shown in FIG. 1 and store them all in the memory in the control circuit 8 (step S
-22). Then, after the reading is completed, the position where the word synchronization determination flag is "1" is detected (steps S-23 and S24), and various data processing is executed by the received data after the detected flag position among the stored data. Is performed (step S-25). In the above-described embodiment, the case where the present invention is applied to the recovery of the word synchronization in the receiving system of the message of the forward control channel has been described. However, the recovery of the synchronization of the message of the forward voice channel is the same as the circuit described above. It is possible to apply using the circuit of the configuration.

(G) Effect of the present invention As described above, both the word synchronization data indicating the word recovery position and the received data are processed as parallel data, and these parallel data are read by interrupt processing. At times other than execution of this interrupt processing, processing other than word synchronization recovery can be performed, and various processing as a wireless communication device can be performed at high speed. Further, since the respective parallel data are read from the same data bus at different timings, these parallel data can be read on the same data bus without collision. Word synchronization can be quickly restored, and various processes as a wireless communication device can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a typical format of a forward control channel message. Fig. 2 (a)
(B) is a diagram showing a specific example of a bit synchronization field and a word synchronization field, respectively. Third
FIG. 1 is a schematic block diagram showing a wireless communication device according to one embodiment of the present invention. FIG. 4 is a block diagram showing an internal configuration of a data receiver in the wireless communication device shown in FIG. FIG. 5 is a diagram showing details of the serial-parallel converter shown in FIG. FIG. 6 is a block diagram showing details of the 8-bit shift register shown in FIG. FIG. 7 is a block diagram showing details of the word synchronization detection circuit and the word synchronization detection shift register shown in FIG. FIG. 8 is a block diagram showing details of the delay circuit shown in FIG. FIG. 9 is a block diagram showing details of the reception data output port and the word synchronization detection output port shown in FIG. FIG. 10 is a block diagram showing a configuration of the three-state buffer register shown in FIG. FIG. 11 is a timing chart for explaining the operation of the circuit shown in FIG. FIG. 12 is a diagram schematically illustrating the operation principle of the circuit shown in FIG. No.
FIG. 13 is a block diagram showing details of the control circuit shown in FIG. FIG. 14 is a flowchart for explaining the operation of the microcomputer shown in FIG. FIG. 15 is a flowchart showing another example of the processing of the microcomputer shown in FIG. (1) ... receiver, (2) ... transmitter, (6) ... data receiver, (7) ... data transmitter, (8) ... control circuit.

Claims (1)

(57) [Claims] A synchronization recovery circuit for recovering word synchronization of serial data including a predetermined word synchronization character, wherein the data conversion converts the serial data into first (n is an integer of 2 or more) bits of first parallel data. Means (604), synchronous data generating means (604, 611, 621) for generating n-bit second parallel data indicating a word synchronous position in the first parallel data, and each of the data converting means and synchronous data generating means is provided in parallel. Means (610) for outputting an interrupt signal when data can be generated, and receiving the interrupt signal from the output means, so that the first and second parallel data are output from the same data bus at different timings. And a control means (8) for reading the data and recovering word synchronization of the serial data based on the respective parallel data. Synchronization recovery circuit for recovering word synchronization of said and.