JP2615642B2 - Bipolar transistor and method of manufacturing the same - Google Patents

Description

The present invention relates to a bipolar transistor for extracting a base by connecting a base extraction region and an intrinsic base region, and a method of manufacturing the same.

B. Prior Art As a high speed and low power consumption bipolar transistor, for example, a bipolar transistor having a structure as shown in FIG. 7 is known. In FIG. 7, an n-type semiconductor layer is provided on, for example, a p-type semiconductor substrate 1 by, for example, epitaxial growth, and the n-type semiconductor layer is formed by an element isolation region 2 of silicon oxide or the like. It is divided into 3 mag. A p-type base region 4 is formed facing the surface of the n-type semiconductor layer in the island region 3, and an n ⁺ -type emitter region 5 is formed in the base region 4. The base region 4 is composed of an intrinsic base region (intrinsic base region) 4i substantially serving as an original base at the center and a high concentration base extraction region (graft base region) 4g for extracting a base electrode. Made up of The base extraction region 4g is formed by p-type impurity diffusion from the base extraction electrode 6 of the p ⁺ -type polycrystalline silicon layer, and the intrinsic base region 4i is formed by p-type impurity implantation using the base extraction electrode 6 as a mask. . The emitter region 5 is formed by using the insulating layer 8 formed on at least the side wall of the base extraction electrode 6 as a mask, and forming the n ⁺ -type polycrystalline silicon layer 7 for extracting the emitter formed on the insulation layer 8.
Formed by introducing an n-type impurity from the substrate. Further, a base electrode 9B of A liter or the like is connected to the base extension electrode 6, and an emitter electrode 9E is connected to the n ⁺ -type polycrystalline silicon layer 7, respectively. Note that, in the example of FIG. 7, the n ⁺ -type buried layer 11 and the n ⁺ -type electrode extraction region correspond to the island-shaped region 3 of the n-type epitaxial layer serving as the collector region.
The collector electrode 9C is electrically connected via 12.

According to the so-called emitter-base self-aligned bipolar transistor having such a structure, the process can be simplified by the self-alignment of the emitter and the base, the parasitic capacitance can be reduced, and the emitter width can be reduced.

However, in order to achieve higher speed, lower power consumption, and higher integration of the bipolar transistor, further reduction in the vertical direction (substrate thickness direction), that is, so-called shallow junction is required. It is required to reduce the base traveling time τ _B by the conversion. Here, the base transit time τ _B is generally τ _B = W _B ² / 2D _n (W _B : base width, D _n : diffusion constant of electron). Performance can be improved.

By the way, as a technique for making the base junction depth shallower and making the base width narrower, conventionally, a technique of ion-implanting a base impurity with low energy through a buffer oxide film and annealing at a low temperature has been used. A technique is known in which impurities for a base are introduced into polycrystalline silicon and diffused at a low temperature. Among them, a technique of introducing a base impurity into polycrystalline silicon and diffusing it at a low temperature has been widely used to prevent so-called accelerated diffusion, channeling tail, and the like caused by damage due to ion implantation.

C. Problems to be Solved by the Invention However, the technique of introducing a base impurity into the polycrystalline silicon and diffusing it at a low temperature is described in the so-called emitter-
When applied to a base self-aligned transistor, the connection between the intrinsic base region and the base extraction region may be disadvantageous as shown in FIGS. 8 and 9.

That is, the base extraction region 4g, which is a graft base region, is formed by diffusion from p ⁺ -type polycrystalline silicon 6 serving as a base extraction electrode, and the intrinsic base region 4i is formed by diffusion from the emitter extraction polycrystalline silicon 7. However, between these diffusion sources (or the side walls of the base extraction electrode), the insulating oxide film 8 for separating the emitter and the base is present at a thickness of, for example, about 0.3 μm. In some cases, as shown in FIG. 8, a gap may be formed between the intrinsic base region 4i and the base extraction region 4g, and the connection may not be made effectively. Also, too sufficiently perform the diffusion, since the base width is narrow and approximately 0.1μm or less, and the n ⁺ impurity of the p ⁺ impurity emitter regions 5 of the base lead-out region 4g, as shown in FIG. 9 collide The breakdown voltage of the emitter-base junction
Adverse effects such as deterioration of the matching characteristics of the emitter voltage V _BE and a decrease in the operating frequency (or cut-off frequency f _T ) occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and it is an object of the present invention to surely connect the intrinsic ace region and the base extraction region while reducing the depth of the base junction (making the junction shallower). And a method for manufacturing the same.

D. Means for Solving the Problems The present invention relates to a base extraction region formed of a high-concentration impurity region formed on the surface of a semiconductor substrate, and, in the base extraction region, a corner contacting a concentration region lower than a peak concentration region. Having, and a recess formed over the active region of the semiconductor substrate, formed in the active region below the recess,
An intrinsic base region connected to the base extraction region near the corner, wherein the peak concentration region and the lower concentration region of the base extraction region are self-aligned with different impurity diffusion sources; The above problem is solved by a bipolar transistor formed in a self-aligned manner with respect to the impurity diffusion source in the peak concentration region.

Further, a method for manufacturing a bipolar transistor includes a step of forming a base extraction region formed of a high-concentration impurity region on a surface of a semiconductor substrate, and forming a recess deeper than a peak concentration depth of the base extraction region from an end of the base extraction region. Forming an intrinsic base region connected to the base extraction region by forming the active region of the semiconductor substrate over the active region and introducing impurities from the concave portion to the active region through the sidewall formed on the side wall of the concave portion. And a process.

Here, the method for manufacturing a bipolar transistor is such that the base extraction region is formed by diffusing an impurity from an impurity diffusion source in contact with the semiconductor substrate, and the recess is formed in a self-aligned manner with respect to the impurity diffusion source. You may do it.

Alternatively, as another method, a step of forming a first sidewall composed of an impurity diffusion source on a side wall surface of a pattern formed on a semiconductor substrate, and a step of forming a first sidewall in an active region of the semiconductor substrate with respect to the first sidewall. Forming the recess in a self-aligned manner, and diffusing the impurity from the impurity diffusion source into the semiconductor body along the corner of the recess, thereby lowering the impurity concentration in a portion which goes under the recess. Forming a base extraction region, forming a second sidewall made of another impurity diffusion source in contact with the side wall of the first sidewall and the side wall of the recess, Forming an intrinsic base region connected to the base extraction region by introducing an impurity into the active region.

E. Function Generally, the impurity concentration distribution of the high-concentration impurity region formed by diffusion from the impurity diffusion source formed on the semiconductor surface is a distribution having one peak near the semiconductor substrate surface. By forming the concave portion reaching the lower concentration region, the impurity region remaining or formed under the concave portion has a low impurity concentration distribution. By connecting the base extraction region and the intrinsic base region under the recess, the connection between the two can be reliably performed, and at the same time, the base extraction region and the emitter region formed in the intrinsic base region can be connected. Is also avoided at high concentrations.

F. Embodiment A preferred embodiment of the present invention will be described with reference to the drawings.

First Embodiment This embodiment relates to the structure of an NPN-type bipolar transistor, and has a recess reaching a concentration region lower than the peak concentration of the high concentration impurity region.
The bipolar transistor ensures the connection between the base extraction region and the intrinsic base region, and at the same time, prevents the emitter region and the base extraction region formed in the intrinsic base region from colliding at a high concentration.

The element structure of the bipolar transistor of this embodiment is
The structure is as shown in the figure, and the main part is the structure shown in FIG. That is, as shown in FIGS. 1 and 2, the bipolar transistor of this embodiment has an N ⁺ type buried layer 52 on a P type
It has an island region 53 composed of an N-type epitaxial layer separated by 54. The island region 53 as a semiconductor substrate
A base extraction electrode 59 which is, for example, a polycrystalline silicon layer which is covered with the insulating film 60 and contains impurities is selectively formed on the surface of the substrate, and the base extraction electrode 59 formed by diffusion from the base extraction electrode 59 is formed. A region 55 is formed as a high-concentration impurity region below the base extraction electrode 59 in the island region 53.

On the surface of the island region 53, a recess 64 is formed which reaches a concentration region lower than the peak concentration in the depth direction of the high concentration impurity region. The corner of the concave portion 64 is in contact with a part of the base take-out region 55, and a part of the base take-out region 55 extends to a portion below the concave portion.
A sidewall formed by etching back an insulating film such as a CVD-SiO ₂ film extends from a part of the bottom of the concave portion 64 to the side wall thereof, and further from the side wall of the base extraction electrode 59 and the insulating film 60. A portion 63 is formed, and a thin polycrystalline silicon layer 61 is formed on the side wall portion 63 and over a part of the surface of the island region 53. This thin polycrystalline silicon layer 61 serves as a diffusion source of the emitter region 58 and an emitter extraction electrode. Further, the sidewall portion 63 is used to form the emitter region 58 and the intrinsic base region 57 in a consistent manner, and the emitter region 58 formed of an N ⁺ -type impurity region is diffused inside the P-type intrinsic base region 57. It has been formed.

The P-type intrinsic base region 57 is connected to the base extraction region 55 below the sidewall 63, that is, below the recess 64. Here, the recess 64
In the lower region 56, the impurity concentration is low due to the formation of the concave portion 64 according to the method of the second embodiment or the third embodiment described later. Therefore, in the bipolar transistor of this embodiment, the connection between the intrinsic base region 57 and the base extraction region 55 can be reliably performed, and the connection between the emitter region 58 and the base extraction region 55, which are high-concentration impurity regions, respectively. Collision can be avoided. In addition, since the region 56 under the concave portion 64 is a low-concentration impurity region, the breakdown voltage (V
It is also possible to improve the _EBO ) and reduce the capacity.

The emitter region 58 is connected to the emitter electrode 62E via the thin polycrystalline silicon layer 61, the intrinsic base region 57 is connected to the base extraction region 55 via the region 56, and the base extraction region 55 It is electrically connected to the base extraction electrode 59 and the base electrode 62B via the same. Further, the buried layer 52 is formed in a collector extraction region 65.
Is connected to collector electrode 62C.

The bipolar transistor of this embodiment having the above-described structure has a structure in which the emitter region 58 and the intrinsic base region 57 are formed in a self-aligned manner, but is a low-concentration impurity region below the concave portion 64. In the region 56, the connection between the intrinsic base region 57 and the base extraction region 55 is made.
Therefore, the connection between the intrinsic base region 57 and the base extraction region 55 can be reliably performed, and the collision between the emitter region 58 and the base extraction region 55 can be avoided. Further, the avoidance of the collision becomes remarkable due to the deviation of the peak concentration in the depth direction. In addition, the intrinsic base region 57 is connected to a region 56 below the recess 64 having an impurity concentration lower than the peak concentration of the high-concentration impurity region, so that unnecessary impurity diffusion is prevented and the base resistance is reduced.
R _bb can be reduced, and a low range of the base traveling time τ _B can be _achieved . In addition, since the impurity concentration of the region 56 is low, a reduction in capacitance and an improvement in withstand voltage can be realized.

Second Embodiment A method of manufacturing a bipolar transistor according to the present embodiment includes a manufacturing method of manufacturing the NPN-type bipolar transistor according to the first embodiment, in which a concave portion is formed so as to remove a peak concentration region of a high concentration impurity region. Is a method for manufacturing a bipolar transistor. Hereinafter, this embodiment will be described with reference to FIG.
The description will be made in the order of the steps with reference to FIG. In FIGS. 3B to 3E, only the area enclosed by the broken line in FIG. 3A is enlarged for simplicity.

(A) First, as shown in FIG. 3A, for example, an N ⁺ -type buried layer 22 is formed in a P-type semiconductor substrate 21, and an N-type epitaxial layer laminated thereon is selectively oxidized or trenched. Forming element isolation region 24 to be of first conductivity type (N type)
The island region 23 is formed as a semiconductor region. continue,
A polycrystalline silicon layer (DOPOS), which is a P-type impurity-containing layer, is applied and patterned to form a base extraction electrode 26 on the island region 23, and an insulating film 27 such as silicon oxide is applied. Next, the base extraction electrode 26 and the insulating film 27 are selectively opened on the island region 23, and an opening 28 exposing the island region 23 is formed. Note that the above element isolation region
A channel forming element region 25 is formed under a part of the part 24, and a part of the buried layer 22 is
Connect with C. Further, the base extraction electrode 26 as the impurity-containing layer is not limited to the polycrystalline silicon layer.
A material such as (boron silicate glass) may be used.

(B) Next, as shown in FIG. 3B, using the base extraction electrode 26 formed selectively, impurity diffusion is performed from the base extraction electrode 26 to form a base extraction region (P-type high concentration impurity region). (Graft base region) 29 is formed. The base extraction region 29 is formed by diffusion along the bottom of the opening 28. The region 29a diffused along the bottom of the opening 28 has an impurity concentration that varies in the depth direction and the lateral direction. Has a distribution.

FIG. 4 shows the impurity concentration distribution in the region 29a diffused along the bottom of the opening 28, the vertical axis represents the impurity concentration (1 nN), and the horizontal axis represents the depth. A curve I in the figure is an impurity concentration distribution curve near the base extraction electrode 26, and a curve II in the figure is an impurity concentration distribution curve far from the base extraction electrode 26. The curve I, as shown in FIG. 4, has a peak concentration N _ip near the surface, the depth Xp with its peak concentration N _ip
In a deeper region, the impurity concentration gradually decreases. Curve II also has a similar impurity distribution. Therefore, it can be seen that the portion near the base extraction electrode 26 has a higher concentration as a whole, and the impurity has a depth Xp relatively close to the surface. It can be seen that it has a concentration peak.

(C) Next, as shown in FIG. 3C, using the insulating film 27 and the like as a mask, a part of the island region 23 in the opening 28 serving as an active region and a portion of the base extraction region 29 are formed. The portion is removed, and a recess 20 is formed from a part of the base extraction region 29 to the active region. Here, the recess 20 is formed by a predetermined silicon etching, and the depth thereof is set to a depth Xe deeper than the peak concentration depth Xp of the base extraction region 29.

That is, the depth Xe at which the recess 20 is formed is, as shown by the curve I in FIG. 4, a depth deeper than the peak concentration depth Xp of the base extraction region 29 located near the surface. . Then, the impurity concentration N of the surface 29b is
_es is lower than the peak concentration _Nip , and accordingly, the region 30 which is the base extraction region 29 below the concave portion 20 has a lower concentration. Here, the impurity concentration _Nes is, for example, when the peak concentration in the intrinsic base region is 1 × 10 ¹⁸ / cm ² and the peak concentration N _ip in the base extraction region is 1 × 10 ¹⁹ / cm ² , The shape of the concave portion 20 is controlled by controlling the impurity concentration _Nes to have a lower concentration.

Note that the silicon etching can be performed by using ammonia and a hydrogen peroxide solution, or the concave portion can be formed by other means.

In this embodiment, the concave portion 20 is formed by silicon etching after forming the graft base region 29 by diffusion from the base extraction electrode 28, but for example, heat treatment for forming the graft base region 29 is performed by the heat treatment for forming the intrinsic base region 33 and the emitter region. When the diffusion is performed after the formation of the concave portion by silicon etching, such as in combination with the heat treatment for forming the concave portion, the concave portion 20 having a depth deeper than the peak concentration depth Xp is taken into consideration in consideration of the final impurity distribution of the graft base. May be formed in advance.

(D) Next, a CVD-SiO ₂ film for forming a sidewall portion over the concave portion 20, the side wall of the base extraction electrode 26 and the side wall and the surface of the insulating film 27 is formed.
Then, the CVD-SiO ₂ film is etched back by using anisotropic etching such as RIE method, and as shown in FIG. It is formed in contact with the side wall of the base extraction electrode 26 and the like.

By forming such a sidewall portion 31, an intrinsic base region and an emitter region described later can be formed in a self-aligned manner. Also, the side wall portion 31 is
The length in contact with the bottom of is as shown by the dotted line in FIG.
The length can be substantially equal to the end of the upper base extraction region 29.In particular, in the manufacturing method of the bipolar transistor of this embodiment, since the region having the peak concentration _Nip has already been removed by forming the concave portion 20, Thus, the region extending below the concave portion 20 of the base extraction region 29 can be sufficiently diffused.

Note that another insulating material can be used as the material of the sidewall portion.

(E) Next, a thin polycrystalline silicon layer 32 is formed on the entire surface including the concave portion 20. This thin polycrystalline silicon layer 32
It is formed to diffuse the intrinsic base region, which is a so-called intrinsic base region, toward the island region 23 at the bottom of the concave portion 20, and impurities such as B ⁺ and BF ₂ ⁺ are introduced by ion implantation.

Then, a capping CVD-SiO ₂ film or the like is formed, annealing is performed, and an intrinsic base region 33 is formed in the active region by impurity diffusion from the thin polycrystalline silicon layer 32. Then, the intrinsic base region 33 formed by activation is connected to the base extraction region 29 through the lower portion of the concave portion 20 which is formed deeper than the peak concentration depth and is a low concentration impurity region, and further, the base Extraction electrode
26 and electrically connected. That is, by connecting the intrinsic base region 33 to the base extraction region 29 through such a low concentration impurity region, the connection is reliably performed,
Since the impurity concentration is low, it is possible to improve the low capacity region and the withstand voltage.

Next, after removing the capping CVD-SiO ₂ film and the like, the thin polycrystalline silicon layer 32 is again used to remove N 2 such as arsenic.
Ion implantation as a type impurity is performed. That is, the intrinsic base region and the emitter region are formed by self-alignment using the thin polycrystalline silicon layer 32. After that, the emitter is diffused at a temperature of about 800 ° C. to 1100 ° C., and as shown in FIG. It is formed in the intrinsic base region 33 on the surface. Then, an aluminum wiring layer is formed on the entire surface, and the aluminum wiring layer is patterned to form wiring electrodes, thereby completing a bipolar transistor.

The method of manufacturing the bipolar transistor according to the present embodiment, which is performed by the above-described steps, first includes the step of forming the concave portion reaching the concentration region lower than the peak concentration in the depth direction of the high concentration impurity region.
The connection between the base extraction region 29 and the intrinsic base region 33 is reliably performed using the low-concentration impurity region below the concave portion 20, and the base extraction region 29 and the emitter region 34 are formed. The collision with can be effectively avoided. In addition, other characteristics of the manufactured bipolar transistor can be improved.

Third Embodiment A method of manufacturing a bipolar transistor according to a third embodiment is characterized in that a side wall portion made of a polycrystalline silicon layer is formed on a side wall of a base extraction electrode, and the base extraction region is deeper than the peak concentration depth of the base extraction region. And a method of manufacturing a bipolar transistor in which a concave portion is formed in an active region. Hereinafter, this embodiment will be described with reference to FIGS.
The description will be made in the order of the steps with reference to FIG. 5b to 5f, only the area within the broken line in FIG. 5a is enlarged for simplification. The same parts as those in the second embodiment are denoted by the same reference numerals, and description thereof will be omitted.

(A) As shown in FIG. 5a, an insulating film is formed on the island region 23.
40, a base extraction electrode 41 and an insulating film 42 which are made of a polycrystalline silicon layer or the like and contain impurities are laminated. Then, in a part of the island region 23, the insulating film 40, the base extraction electrode 41, and the insulating film 42 are opened to form an opening 43.

(B) Next, a polycrystalline silicon layer 44 is formed on the entire surface including the opening 43. This polycrystalline silicon layer 44 is used not only to form a sidewall portion formed in the next step, but also to diffuse impurities from the base extraction electrode 41 into the island region 23. The polycrystalline silicon layer 44 may be a so-called viewer polysilicon layer containing no impurities, or may be a polycrystalline silicon layer into which impurities such as B ⁺ and BF ₂ ⁺ are introduced.

(C) After forming such a polycrystalline silicon layer 44,
Anisotropic etching is performed on the polycrystalline silicon layer 44 to form a side wall 45 made of the polycrystalline silicon layer 44 on the side wall of the opening 43. And at the same time, the fifth
As shown in FIG. C, the surface of the island region 23 exposed at the bottom of the opening 43 is also removed by anisotropic etching to form a concave portion 39 on the surface of the island region 23.

Here, the concave portion 39 is consequently shaved in a manner consistent with the sidewall portion 45, and the concave portion 39 is not formed where the sidewall portion 45 exists. The depth Xe of the recess 39 is generally deeper than the depth Xp (see FIG. 4) having a peak concentration in the depth direction when the impurity is diffused through the polycrystalline silicon layer. . Then, the side wall portion 45 of the concave portion 39 is formed.
The corner 39c between the side wall along the bottom and the bottom of the recess 39 is
Since 9 is formed by anisotropic etching, it has an angle close to a right angle.

(D) Next, as shown in FIG. 5D, an impurity is diffused from the base extraction electrode 41 via the sidewall portion 45 or directly from the sidewall portion 45, and
The base take-out region 46 is formed so as to extend from the side wall to the bottom. Then, since the corner portion 39c of the concave portion 39 has an angle close to a right angle as described above, the impurities diffused from the sidewall portion 45 into the island-like region 23 have the active region from the angle 39c. On the side, the concentration becomes thinner by the amount of wraparound, and furthermore, as described above, the concave portion 39 is deepened by the depth Xe as described above, so that the concave portion 39 is formed.
The part below is sufficiently low in impurity concentration.

(E) As described above, while utilizing the shape of the concave portion 39,
After forming the concave portion 39 deeper than the peak concentration depth of the base extraction region 46 and the active region where the base extraction region 46 and the intrinsic base region and the emitter region are formed, as shown in FIG. A CVD-SiO ₂ film is formed on the substrate, and the CVD-SiO ₂ film is etched back to form a second
The sidewall portion 47 is formed in contact with the sidewall of the sidewall portion 45 and the sidewall of the concave portion 39. The second sidewall portion 47 is for electrically separating the emitter and the base, and by forming such a second sidewall portion 47, an intrinsic base region and an emitter region are formed by self-alling. it can.

Further, a part of the low concentration base extraction region 46 is diffused below the second sidewall portion 47 in contact with the concave portion 39, and despite the formation of the second sidewall portion 47, Thus, a secure connection between the intrinsic base region to be formed next and the base extraction region 46 is realized.

Here, in order to make connection more securely, the structure of the second sidewall portion may be as shown in FIG.
That is, by forming the second sidewall portion into a two-layer structure of the boron-doped silicon oxide layer 70 and the insulating layer 71, the low-concentration impurity region 72 is formed by impurity diffusion from the boron-doped silicon oxide layer 70, and then formed. A more reliable connection between the intrinsic base region and the base extraction region 46 can be realized. (F) Next, a thin polycrystalline silicon layer 48 is formed on the entire surface including the concave portion 39. This thin polycrystalline silicon layer 48
The intrinsic base region, which is a so-called intrinsic base region, is formed to diffuse toward the island region 23 at the bottom of the concave portion 39, and impurities such as B ⁺ and BF ₂ ⁺ are introduced by ion implantation.

Then, a capping CVD-SiO ₂ film or the like is formed, annealing is performed, and an intrinsic base region 49 is formed in the active region by impurity diffusion from the thin polycrystalline silicon layer 32. Then, the activated intrinsic base region 49 is connected to the base extraction region 46 through the lower part of the concave portion 39 which is formed deeper than the peak concentration depth and is a low concentration impurity region, and further, Extraction electrode
Connect to 41 electrically.

Next, after removing the capping CVD-SiO ₂ film or the like, the thin polycrystalline silicon layer 48 is again used to remove N 2 such as arsenic.
Ion implantation as a type impurity is performed. After that, emitter diffusion is performed at a temperature of about 800 to 1000 ° C,
As shown in FIG. 5E, an emitter region 50 which is a first conductivity type (N-type) impurity region is formed in the intrinsic base region 49 on the surface of the island region 23. Then, an aluminum wiring layer is formed on the entire surface, and the aluminum wiring layer is patterned to form wiring electrodes, thereby completing a bipolar transistor.

The method for manufacturing the bipolar transistor according to the present embodiment including the above-described steps first uses the low-concentration region caused by the shape of the concave portion 39 to ensure the connection between the base extraction region 46 and the intrinsic base region 49. At the same time, the collision between the base extraction region 46 and the emitter region 50 can be effectively avoided. In addition, other characteristics of the manufactured bipolar transistor can be improved.

Furthermore, even when the selectivity between the polycrystalline silicon layer and the semiconductor substrate is small, the sidewalls can be formed sufficiently, and miniaturization of the element can be achieved without particularly requiring a complicated process.

In the above-described first to third embodiments, the NPN-type bipolar transistor has been described. However, a PNP-type bipolar transistor may be used. Various changes can be made without departing from the spirit of the present invention.

G. Effects of the Invention According to the bipolar transistor and the method of manufacturing the same of the present invention, effective connection between the base extraction region and the intrinsic base region can be achieved by forming and using a desired recess, and collision between the high-concentration impurity regions can be achieved. Can be avoided. In addition, from the impurity concentration and the position in the depth direction, it is possible to improve the specificity of the bipolar transistor, such as improving the withstand voltage and reducing the capacitance.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an example of the bipolar transistor of the present invention, FIG. 2 is a cross-sectional view of a main part thereof, and FIGS. FIG. 4 is an impurity concentration distribution diagram of the base extraction region, FIGS. 5a to 5f are cross-sectional views showing steps of another example of the method of manufacturing the bipolar transistor of the present invention, and FIG. 2nd sidewall
7 to 9 are schematic cross-sectional views illustrating a conventional example. 23,53 island region 26,41,59 base extraction electrode 29,46,55 base extraction region 31,45,63 sidewall portion 47 second sidewall portion 32,48, 61 Thin polycrystalline silicon layer 33, 49, 57 Intrinsic base region 34 50, 58 Emitter region

Claims (4)

(57) [Claims] A base extraction region formed of a high-concentration impurity region formed on a surface of a semiconductor substrate; a corner portion in the base extraction region that is in contact with a concentration region lower than a peak concentration region; A concave portion formed over the region, an intrinsic base region formed in the active region below the concave portion and connected to the base take-out region near the corner, and a peak concentration region of the base take-out region; Each of the lower concentration regions is formed in a self-aligned manner with respect to another impurity diffusion source, and the concave portion is formed in a self-aligned manner with respect to the impurity diffusion source in the peak concentration region. Characteristic bipolar transistor. A step of forming a base extraction region comprising a high-concentration impurity region on the surface of the semiconductor substrate; and forming a recess deeper than a peak concentration depth of the base extraction region from an end of the base extraction region. Forming an intrinsic base region connected to the base extraction region by introducing an impurity from the recess into the active region via a sidewall formed on a side wall of the recess. A method for manufacturing a bipolar transistor. 3. The semiconductor device according to claim 2, wherein said base extraction region is formed by diffusing impurities from an impurity diffusion source in contact with said semiconductor substrate, and said recess is formed in a self-aligned manner with respect to said impurity diffusion source. 13. The method for producing a bipolar transistor according to claim 10. 4. A step of forming a first sidewall made of an impurity diffusion source on a side wall surface of a pattern formed on a semiconductor substrate, and forming a first sidewall in an active region of the semiconductor substrate with respect to the first sidewall. Forming a concave portion in a consistent manner, and diffusing the impurity from the impurity diffusion source into the semiconductor base along the corner of the concave portion, whereby the impurity concentration is reduced at a portion which goes under the concave portion. Forming a base extraction region comprising: forming a second side wall made of another impurity diffusion source in contact with the side wall of the first side wall and the side wall of the concave portion; Forming an intrinsic base region connected to the base extraction region by introducing an impurity into the region. Method.