JP2618103B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a digital / analog mixed semiconductor integrated circuit.

In recent years, with the development of semiconductor technology, a digital / analog mixed-type LSI (large scale integrated circuit) in which large-scale analog circuits are mixed has been produced. According to this, the mounting density of the electronic device can be increased, and the size can be further reduced.

Incidentally, the number of terminals of an LSI is determined for each package, and it is necessary to solve the problem of an increase in the number of terminals due to mixed mounting of analog circuits.

[0004]

2. Description of the Related Art As a conventional technique for solving the above-mentioned problem, there is a technique in which a terminal for a digital circuit and a terminal for an analog circuit are shared.

For example, when a multi-channel analog circuit (for example, an A / D converter) having a plurality of analog signal inputs is mounted, A
A plurality of terminals that do not overlap with the / D operation are selected, and the selected terminals are used as digital / analog terminals.

[0006]

However, in the prior art, since a digital terminal which does not overlap with the operation of the analog circuit is simply selected, for example, the input terminal, the output terminal or the input / output terminal is selected. In some cases, a plurality of digital terminals having different circuit types are mixed and selected. In particular, when a multi-channel analog signal is used as an input from a shared terminal as in an A / D converter, each digital terminal has There is a problem that an error between signals increases due to a difference in circuit type.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to eliminate errors between signals of a multi-channel analog signal by pseudo-arranging circuit forms between a plurality of shared terminals.

[0008]

In order to achieve the above object, the present invention has a plurality of digital / analog terminals P ₁ , P ₂ ,..., P _n as shown in FIG. In the semiconductor integrated circuit, capacitance adjusting means C for adjusting the load capacitance of the other terminals P ₂ ,..., P _n in accordance with a specific terminal (for example, P ₁ ) having the largest load capacitance among the plurality of terminals. _2, and further comprising a ...... C _n.

In FIG. 1, D ₁ , D ₂ ,..., D _n
Is a digital circuit, and A ₁ , A ₂ ,... _An are analog circuits.

[0010]

According to the present invention, the shared terminal P is provided by the load adjusting means.
_1, P _2, ......, load capacity for each P _n can be made uniform. Therefore, the circuit form of each dual-purpose terminal that affects the inter-signal error of the multi-channel analog signal is pseudo-aligned.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure
2 is a diagram showing one embodiment of a semiconductor integrated circuit according to the present invention.
Yes, P₁₁, ... P _mIs provided in the semiconductor integrated circuit 10.
Digital / analog shared terminal. However, here
Are two shared terminals (P₁₁And P_m) Only as a representative
Show.

These dual-purpose terminals P ₁₁ and P _m are terminals for inputting (or outputting or inputting / outputting) digital signals and for outputting a plurality of analog signals from a built-in D / A converter, for example. Terminal or a terminal for inputting a plurality of analog signals to a built-in A / D converter.

That is, in FIG. 2, a digital signal S generated by a digital circuit (not shown) in a chip is provided.
_DOUT1 is, CMOS output buffer 11 and the shared terminal P ₁₁
And a digital signal S _DIN1 from the outside of the chip is input to a digital circuit (not shown) in the chip via the same shared terminal P ₁₁ and the CMOS input buffer 12. analog signal S _A1 from the outside is input to the analog circuit (not shown) in the chip via the same shared terminal P ₁₁ and the analog switch 13. Therefore, one shared terminal P _11, along with a input and output terminals of the digital signal S _DOUT1 and S _DIN1, is also an input terminal of the analog signal S _A1.

[0014] The digital signal S _{DO UT2} generated by digital circuitry within the chip (not shown), CMOS
Addition to being output to the outside via the output buffer 14 and the shared terminal P _m, the analog signal S _A2 from outside of the chip via the same shared terminal P _m and the analog switch 15 analog circuitry within the chip (not shown) Is entered. Thus, the other one sharing terminal P _m, digital signal S _DOUT2
And an input terminal for the analog signal S _A2 .

Reference numerals 16 and 17 denote protection devices for overvoltage protection, T _P11 , T _P12 , T _P13 , T _P14 , T _P15 , T
_P16 and T _P17 are P-channel MOS transistors, T
_N11 , T _N12 , T _N13 , T _N14 , T _N15 , T _N16 , T _N17 are N
It is a channel type MOS transistor.

[0016] Here, two sharing terminal to represent in this embodiment, whereas the one terminal P ₁₁ is for digital "input and output", the other terminal P _m a digital "output"
The difference is that That is, there is a substantial difference in the circuit form CMOS input buffer 12 of the P ₁₁ side is not present on the P _m side.

As a result, there is a problem that, as a result of a slight difference between the wiring capacity of each shared terminal and the input capacity of the CMOS buffer, an inter-signal error occurs particularly in a multi-channel analog signal.

Therefore, in this embodiment, one of the dual-purpose terminals P ₁₁
Of the CMOS input buffer 12 and the input wiring L ₁₁ identical CMOS input buffer (hereinafter dummy buffer) 18 and an input wiring and (dummy wiring) to L ₁₂ other shared terminal P
By providing _m , the circuit types are made to match in a pseudo manner.

By doing so, each of the shared terminals P ₁₁ ,
Since the wiring capacitance attached to P _m and the input capacitance of the CMOS buffer can be made the same, it is possible to eliminate an error between multi-channel analog signals.

[0020] That is, the dummy buffer 18 is newly added and the dummy wiring L ₁₂ is "multiple shared terminal P _11, ...
..., P in other terminals (Example most large load capacity attached particular terminal (P ₁₁ in the embodiment) combined in the P _m
m )), so that it functions integrally as the capacity adjusting means 19 described in the gist of the invention.

In the above embodiment, one of the shared terminals P
While adding ₁₁ CMOS input buffer 12 and the input wiring L ₁₁ and the dummy buffer 18 and the dummy wiring L ₁₂ of the same configuration of the other shared terminal P _m, is not limited to this, for example, Ya dummy buffer 18 it may be crowded create a capacity device in place of the dummy wiring L _12. However, there is a disadvantage that the design is inferior to the above embodiment. According to the method of the embodiment, it is only necessary to repeatedly create an already designed circuit.However, in the method of manufacturing a capacitance device, it is necessary to find an optimum capacitance value and newly build the capacitance. It is.

[0022]

According to the present invention, the circuit format between a plurality of dual-purpose terminals is pseudo-aligned, so that errors between multi-channel and analog signals can be eliminated, and the operation of a digital / analog mixed LSI can be achieved. Stability can be improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of one embodiment.

[Explanation of symbols]

P ₁ , P ₂ ,..., P _n : shared terminal P ₁ : specific terminal P ₂ ,..., P _n : other terminals C ₂ ,... C _n : capacity adjusting means P ₁₁ , P _m : shared terminal terminal P _11: specific terminal P _m: the other terminals 19: volume adjustment means

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit having a plurality of digital / analog dual-purpose terminals, a capacitance adjusting means for adjusting a load capacitance of another terminal in accordance with a specific terminal having the largest load capacitance among the plurality of terminals. A semiconductor integrated circuit comprising: