JP2619964B2 - Two-input arithmetic operation method for addition or subtraction and decimal addition / subtraction circuit - Google Patents

Description

Detailed Description of the Invention [Table of Contents] [Overview] [Industrial application field] [Prior art] Diagram showing a conventional decimal addition / subtraction circuit (FIG. 3) FIG. Diagram showing an example (FIG. 4), [Problems to be solved by the invention] [Means for solving the problem] [Operation] [Example] Diagram showing an embodiment of the present invention (FIG. 2) [Effects of the Invention] [Overview] Regarding a two-input logical operation method and a decimal addition / subtraction circuit for addition or subtraction using a predicted sum of addition or subtraction of two-input numerical data, high-speed addition / subtraction without re-correction A correction circuit for each digit which adds 6 to the first input numerical data in which each digit is displayed in hexadecimal notation and outputs the result, and inverts and outputs the result in subtraction And the first input numerical data and the second input numerical data in which each digit is displayed in hexadecimal notation. A predicted value generation circuit for generating four decimal predicted values of addition or subtraction for each digit of the first input numerical data and the second input numerical data, and a first input numerical data and correction circuit of each digit A carry signal generating circuit for generating a carry signal for each digit in response to the output numerical data of the digit, and a decimal signal determined according to the carry signal of the digit and the carry signal of the digit one digit lower than the digit. And a selection circuit for selecting a predicted value as a result value of addition or subtraction for each digit.

[Industrial applications]

The present invention relates to a two-input logical operation method and a decimal addition / subtraction circuit for adding or subtracting two-input numerical data while generating a predicted sum of addition or subtraction of the two-input numerical data. About.

In an electronic computer or the like, it is necessary to add binary numerical data in the processing there. Various types of circuits have been developed and used as circuits for adding binary numerical data. One of the major reasons for the development effort of the adder circuit is to satisfy the demand for high-speed addition processing in electronic computers and the like.

[Conventional technology]

FIG. 3 shows an example of a conventional decimal addition / subtraction circuit. This decimal addition / subtraction circuit includes an input correction circuit 50, a binary addition circuit 60,
It comprises a decimal addition / subtraction selection circuit 61 and an output correction circuit 70.
The input correction circuit 50 includes a +6 addition circuit 52, an inversion circuit 54,
And a selection circuit 56. The selection circuit 56 selects the +6 addition circuit 52 at the time of decimal addition, and selects the inversion circuit 54 at the time of decimal subtraction. The output correction circuit 70 includes a -6 subtraction circuit 72 and a selection circuit 74. The selection circuit 74 is 2 when there is carry.
Selects hexadecimal addition circuit 60 and when there is no carry -6 subtraction circuit
Select 72. Input / output correction circuits 50 and 70 are provided for each digit.

The addition / subtraction operation of this decimal addition / subtraction circuit is as follows. An example of decimal addition will be described first with reference to FIG.

The addend X is set to 3214 and the addend Y is set to 2176. It is assumed that each digit of any of these numerical data is displayed in hexadecimal. The addend Y is corrected by a +6 addition circuit 52 of the input correction circuit 50 (which is selected because it is a decimal addition) to be 87DC, and is applied to the binary addition input of the binary addition circuit 60. The input and the augend 3214 input to the binary addend input are added. Since the operation of the decimal addition / subtraction circuit at this time is an addition operation, “0” is input to the least significant digit carry input to the selection circuit 56. Therefore, the binary addition output value of the binary addition circuit 60 is B9F0, and its carry output is decimal carry 0 = "0", decimal carry 1 = "0", 10
Since the binary carry 2 = "0" and the decimal carry 3 = "0" are output, the binary addition output value B9F0 is corrected by the output correction circuit 70. The sum of the augend 3214 and the addend 2176 output therefrom as a result of the addition operation in the decimal addition / subtraction circuit is 5390.

The subtraction operation when the values of the augend and the addend are the same as the above-described addition will be described below with reference to FIG.

The decrement Y is corrected by the inverting circuit 54 of the input correcting circuit 50 (which is selected because it is a decimal subtraction), becomes DE89, and is input to the binary addition input of the binary adding circuit 60. Is subtracted from the minuend 3214 input to the binary addend input. Since the operation of the decimal addition / subtraction circuit at this time is a subtraction operation, “1” is input to the least significant digit carry input to the selection circuit 56. Therefore, the binary addition output value of the binary addition circuit 60 is 109E, and its carry output is 10E.
Decimal carry 0 = "1", Decimal carry 1 = "1", Decimal carry 2 =
Since "0" and decimal carry 3 = "0" are output, the binary addition output value 109E is corrected by the output correction circuit 70.
The difference between the minuend 3214 output therefrom as a result of the subtraction operation in the decimal addition / subtraction circuit and the subtrahend 2176 is 1038
Becomes

[Problems to be solved by the invention]

The above-described decimal addition / subtraction circuit requires two digits to perform decimal addition / subtraction.
Output correction circuit 70 for correcting the output value of hexadecimal addition circuit 60
Must be provided as an essential component. Therefore, the result of decimal addition / subtraction is output with a delay of the time spent for signal propagation in the output correction circuit 70. this is,
Hinders the speed of decimal addition / subtraction.

The present invention has been created in view of such problems,
An object of the present invention is to provide a two-input logical operation method and a decimal addition / subtraction circuit for addition or subtraction that can achieve high-speed addition / subtraction without recorrection.

[Means for solving the problem]

According to the first aspect of the present invention, each digit is represented by an n-ary system.
For the input numerical data of, the addition is performed for each digit in order to output the addition result value in the m-ary notation in the addition, and the inversion is performed in the subtraction in order to output the subtraction result value in the m-ary notation. Four m-ary predicted values for addition or four subtractions for subtraction of the first input numerical data and the second input numerical data in which each digit is displayed in n-ary notation The m-ary prediction value is calculated by the first
And the correction is made in response to the corrected or inverted first input numerical data and the second input numerical data generated for each digit of the input numerical data and the second input numerical data. ,
Or the inverted first input numerical data and the second input numerical data
Is generated for addition or subtraction of the carry signal of each digit of the input numerical data of the above, and four m-ary prediction values for addition or four m-ary prediction values for subtraction generated for each digit are generated. The m-ary result of the addition or subtraction of the m-ary prediction value determined according to the carry signal of the relevant digit generated for addition or subtraction and the carry signal of the next lower digit from the relevant digit It is configured to be selected as a value.

As shown in FIG. 1, the invention according to claim 2 adds 6 to the first input numerical data in which each digit is displayed in hexadecimal notation in response to a 10 addition designation signal or a 10 subtraction designation signal. Or, a correction circuit 2 for each digit that causes inversion of the first input numerical data, and the 10-addition designation signal or the 10-
Addition of the first input numerical data and the second input numerical data in response to a subtraction designation signal, output numerical data of the correction circuit, and second input numerical data in which each digit is displayed in hexadecimal notation. A predicted value generating circuit 4 for each digit of the first input numerical data and the second input numerical data, which generates four decimal predicted values of And the second input numerical data;
In response to the output numerical data of the correction circuit 2, the second
And a carry signal generating circuit 6 that generates a carry signal for each digit of the input numerical data and the output numerical data of the correction circuit 2 for addition or subtraction, and four signals for the addition generated for each digit. Decimal predicted value, or four 10s for subtraction
Addition or subtraction of a decimal prediction value determined by the carry signal of the digit generated for addition or subtraction and the carry signal of the digit one digit lower than the digit of the decimal predicted value And a selection circuit 8 for selecting the result as a decimal result value.

(Operation)

Each digit of the first input numerical data represented in the n-ary system, for example, the hexadecimal system, is corrected or inverted by the correction circuit 2 corresponding to the digit in accordance with addition or subtraction. The corrected or inverted first input numerical data is input to the carry signal generating circuit 6 corresponding to the digit together with the second input numerical data expressed in hexadecimal. The carry signal generating circuit 6
Generates a carry signal determined according to both input numerical data.

At the same time, an m-ary system, for example, a decimal predicted value is generated for each digit of the first input numerical data and the second input numerical data input from the predicted value generating circuit 4.

It is determined by the carry signal of the generated predicted value and the carry signal of one digit lower than the carry signal.
The decimal prediction value is selected and output as a result value of addition or subtraction of the digit by the selection circuit 8 for each digit.

As described above, since the prediction value is selectively output, no signal delay occurs in the conventional re-correction circuit. High-speed operation can be achieved.

〔Example〕

FIG. 2 shows an embodiment of the first and second aspects of the present invention. In this figure, reference numerals 50, 52, 54, 56, 6
Reference numerals 0 and 62 are the same as the reference numbers assigned to the components in the decimal addition / subtraction circuit shown in FIG. 3, and the same reference numerals are the same as the components of the decimal addition / subtraction circuit shown in FIG. Is shown.

A first predicted sum generation circuit 20, a second predicted sum generation circuit 22,
The third predicted sum generation circuit 24, the fourth predicted sum generation circuit 26, and the multiplexer 28 constitute only the circuit portion 100 for the most significant digit among the characteristic portions of the present invention. The first predicted sum generation circuit 20 includes a 4-bit inversion circuit 30, a -6 addition circuit 32, a multiplexer 34, and a 4-bit addition circuit 36. The first input numerical data (for example, the augend data) X0 (decimal data expressed in hexadecimal; the same applies hereinafter) is input to the augend input of the 4-bit adder circuit 36, and 4 bits are input. The second input numerical data (for example, addend data) addend data Y0 (decimal data expressed in hexadecimal; the same applies hereinafter) is input to the input of the inverting circuit 30, and the input numerical data Y0 is input.
Is also supplied to one input of a multiplexer 34. 4
The output of the bit inversion circuit 30 is supplied to the other input of the multiplexer 34 via the -6 addition circuit 32. The multiplexer 34 selects one of the inputs for decimal addition and the other input for decimal subtraction. 4-bit addition circuit
"0" is input to the 36 least significant digit carrier input. The second predicted sum generation circuit 22 includes a 4-bit inversion circuit 30, a -6 addition circuit 32, a multiplexer 34, and a 4-bit addition circuit 38. The first input numerical data X0 is input to the augend input of the 4-bit adder circuit 38, and the multiplexer is input to the addend input.
34 outputs are input. “1” is input to the least significant digit carry input of the 4-bit adder circuit 38. The 3 predicted sum generation circuit 24 includes a +6 addition circuit 40, an inversion circuit 42, and a multiplexer.
44 and a 4-bit addition circuit 46. 4-bit addition circuit
The first input numerical data X0 is input to the augend 46, and the second input numerical data Y0 is input to the inputs of the +6 adding circuit 40 and the inverting circuit 42. The outputs of the +6 adding circuit 40 and the inverting circuit 42 are supplied to the other input of the 4-bit adding circuit 46 via the multiplexer 44. Multiplexer 44
Is the one input, that is, the output of + addition circuit 40 in the case of decimal addition, and the other input, that is, the inversion circuit, in the case of decimal addition.
Select 42 outputs. “0” is input to the least significant digit carry input of the 4-bit adding circuit 46. The fourth predicted sum generation circuit 26 includes a + addition circuit 40, an inversion circuit 42, and a multiplexer 44.
And a 4-bit addition circuit 48. 4-bit adder circuit 48
The first input numerical data X0 is input to the augend input, and the output of the multiplexer 44 is input to the addend input. "1" is input to the least significant digit carry input of the 4-bit adding circuit 48.

The multiplexer 28 carries the carry CR from the binary addition circuit 60.
According to Y0 to CRY3, the 4-bit addition circuits 36, 4
The output of the bit addition circuit 38, the 4-bit addition circuit 46, and the 4-bit addition circuit 48 are selected. The prediction selection method in the multiplexer 28 will be described below.

In the case of decimal addition, Zn = An (CRY _n = 0, CRY _{n + 1} = 0) Zn = Bn (CRY _n = 0, CRY _{n + 1} = 1) Zn = Cn (CRY _n = 1, CRY _{n n + 1} = 0) is performed by the multiplexer 28 in accordance with a prediction sum selection method such as Zn = Dn (CRY _n = 1, CRY _{n + 1} = 1). The carry CRY _n means a decimal carry to the upper digit, and the carry CRY _{n + 1} means a decimal carry from the lower digit. CRY _{n + 1} at the least significant digit = "0". Here, n is the input augend and each digit of the input addend, that is, 0, 1, 2, and 3 corresponding to X0 and Y0, X1 and Y1, X2 and Y2, and X3 and Y3. .

In the case of decimal subtraction, Zn = An (CRY _n = 0, CRY _{n + 1} = 0) Zn = Bn (CRY _n = 0, CRY _{n + 1} = 1) Zn = Cn (CRY _n = 1 , CRY _{n + 1} = 0) Zn = Dn (CRY _n = 1, CRY _{n + 1} = 1) in accordance with the prediction difference selection method. Carry CRY _n in this case is also
Y _{n + 1} has the same meaning as in the case of the decimal addition. The same applies to n. CRY _{n + 1} at the least significant digit = "1".

Other digits are composed of exactly the same components. The circuit portions of each digit are indicated by 110, 120, and 130, respectively.

2, a +6 addition circuit 52, an inversion circuit 54, and a multiplexer 56 correspond to the correction circuit 2 in FIG. 1, and include inversion circuits 30, 42, a -6 addition circuit 32, a +6 addition circuit 40, and multiplexers 34, 44. The 4-bit addition circuits 36, 38, 46, and 48 correspond to the predicted value generation circuit 4 in FIG. The binary addition circuit 61 and the decimal addition / subtraction selection circuit 61 correspond to the carry signal generation circuit 6 in FIG. 1, and the multiplexer 28 corresponds to the selection circuit 8 in FIG.

The operation of the decimal addition and the decimal subtraction of the present invention having the above configuration will be described below.

First, the operation of decimal addition will be described. As in the case of the above-described conventional example, the augend X is set to 3214 and the addend Y is set to 2114.
76. It is assumed that each decimal digit of any of these numerical data is displayed in hexadecimal.

The least significant digit in this addition operation, that is, X3 of the augend X =
The decimal carry CRY4 output from the binary adder circuit 60 for Y3 = 6 of the addend Y and the addend Y is “0”, and the decimal carry CR
Since Y3 is "1", X3 = 4 of the augend X in the above example,
And the addend Y, Y3 = 6, is input to the 4-bit adder circuit 36, 4-bit adder circuit 38, 4-bit adder circuit 46, and 4-bit adder circuit 48. 4-bit adder circuit among 0 "," 1 "," 6 "and" 7 "
The decimal number A3 = "0" generated from 36 is the multiplexer
At 28, a selection is made according to the predictive sum selection method described above.

In the addition operation for the addend X of X2 = 1 and the addend Y of Y2 = 7, the decimal carry CRY3 at the next lower digit is
Since the decimal carry CRY2 output from the binary adder circuit 60 for this digit is "1", the addend X X2 = 1 and the addend Y Y2 of the above example are "0". = 7 at its input, the decimal prediction sums "7" and "9" already generated from the 4-bit addition circuit 36, the 4-bit addition circuit 38, the 4-bit addition circuit 46, and the 4-bit addition circuit 48. , “3” and “4”, the decimal predicted sum B2 generated from the 4-bit adder circuit 38
= “9” is selected by the multiplexer 28 as the sum of the digits in accordance with the above-described prediction sum selection method.

In the addition operation of X1 = 2 of the addend X and Y1 = 1 of the addend Y, also X1 = 3 of the addend X and the addend Y
Even in the addition operation for Y1 = 2, the decimal carry to that digit and the decimal carry from that digit to the upper digit are also “0”, so the output from the 4-bit adder circuit 36 is output in any digit. The calculated decimal prediction sums A1 = “3” and A0 = “5” are selected and output by the multiplexer 28 as the sums of the corresponding digits, respectively.

In the subtraction operation, the subtrahend X is subtracted from the subtrahend X in substantially the same operation.

The least significant digit in the subtraction operation, that is, X3 of the minuend X =
The decimal carry CRY3 output from the binary adder circuit 60 for 4 and Y3 = 6 of the decrement Y is "0", and the decimal carry CRY4 from the next lower digit is "1". In the above example, X3 = 4 of the minuend X and Y3 = 6 of the minuend Y are received at their inputs, and the 4-bit addition circuit 36, 4-bit addition circuit 38, 4-bit addition circuit 46, and 4-bit addition circuit 48 have Among the generated decimal prediction differences, the decimal prediction difference B3 generated from the 4-bit adding circuit 38 out of “7”, “8”, “3”, and “4”
= “8” is selected as the digit difference in the multiplexer 28 according to the above-described prediction difference selection method.

The decimal carry CRY3 from the next lower digit in the subtraction operation for X2 = 1 of the minuend X and Y2 = 7 of the minuend Y is
Since the decimal carry CRY2 output from the binary adder circuit 60 for the digit is "0", "X2 = 1 for the minuend X and Y2 = 7 for the subtrahend Y in the above example are" 0 ". In response to the input, the 4-bit addition circuit 36, 4-bit addition circuit 38, 4-bit addition circuit 46, and 4-bit addition circuit 48 use "3", "4", "9" Of the decimal prediction difference A2 generated from the 4-bit addition circuit 36 among "0" and "0"
= “3” is selected in the multiplexer 28 as the digit difference in accordance with the above-described prediction difference selection method.

In the subtraction operation for X1 = 2 of the minuend X and Y1 = 1 of the subtrahend Y, the decimal carry CRY2 from the next lower digit
Is "0", and the decimal carry CRY1 output from the binary addition circuit 60 for the digit is "1", so that the decimal prediction difference C1 = “0”
Is selected in the multiplexer 28 according to the above-described prediction difference selection method. Also, X1 of the minuend X =
In the subtraction operation for Y1 = 2 of the subtraction Y, the decimal carry CRY1 from the next lower digit is “1” and the digit is output from the binary adder circuit 60 for that digit.
Decimal carry CRY0 is "1", so 4-bit adder
The decimal prediction difference D0 = "1" generated from 48 is selected as the difference of the digit in the multiplexer 28 according to the above-described prediction difference selection method.

In the above embodiment, the case where there is no carry from the digit of the highest-order sum of decimal numbers is described, but the decimal numbers A0 to D0
The carry generated by a decimal number selected from the following is output from the multiplexer 28 so as to constitute the next higher digit. Although the case where both addition and subtraction have four digits has been described, the present invention can be implemented with any other number of digits. In addition, how the number is displayed in any decimal system is not a limitation in practicing the present invention. Therefore, neither the correction circuit nor the addition circuit is limited to those of the above-described embodiment.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, instead of the re-correction for the calculation result, the prediction sum selection method is employed, so that the high-speed calculation is performed by the propagation time of the calculation signal in the re-correction. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the invention according to claim 2, FIG. 2 is a diagram showing an embodiment of the invention according to claims 1 and 2, and FIG. 3 is a diagram showing a conventional decimal addition / subtraction circuit. FIG. 4 is a diagram showing an example of addition and subtraction of the circuit in FIG. 1 and 2, reference numeral 2 denotes a correction circuit (+6 addition circuit 52, inversion circuit 54, multiplexer 56), and 4 denotes a predicted value generation circuit (inversion circuits 30, 42, -6 addition circuit 3).
2, +6 addition circuit 40, multiplexers 34,44, 4-bit addition circuits 36,38,46,48) 6 is a carry signal generation circuit (binary addition circuit 60, decimal addition / subtraction circuit 61), and 8 is a selection circuit ( Multiplexer 28).

Continued on the front page (72) Inventor Kazuyasu Nonomura 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Toru Watanabe 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Takumi Takeno 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shinya Kato 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References (JP, U)

Claims (2)

(57) [Claims] In addition, the first input numerical data in which each digit is displayed in an n-ary system is subjected to a correction for outputting an addition result value in an m-ary system for each digit in the addition, and is output. In the above, the subtraction result value is inverted for each digit for outputting in m-ary notation and output, and the first input numerical data and the second input numerical data in which each digit is expressed in n-ary notation are output. Four m-ary prediction values for addition or four m-ary prediction values for subtraction are generated for each digit of the first input numerical data and the second input numerical data, and are corrected or inverted. Said correction in response to said first input numerical data and said second input numerical data.
Or the inverted first input numerical data and the second input numerical data
The four m-ary prediction values of the addition generated for each digit of the carry signal of each digit of the input numerical data for addition or subtraction,
Or of the four m-ary predictions for subtraction,
Alternatively, a m-ary prediction value determined according to the carry signal of the digit generated for the subtraction and the carry signal of the digit one digit lower than the digit is selected as the m-ary result value of addition or subtraction of the digit. A two-input arithmetic operation method for addition or subtraction. 2. Addition of 6 to the first input numerical data in which each digit is displayed in hexadecimal in response to a 10 addition specifying signal or a 10 subtraction specifying signal, or inversion of the first input numerical data. The correction circuit 2 for each digit to be generated, and the 10 addition designation signal or the 10 subtraction designation signal, the output numerical data of the correction circuit and the second input numerical data in which each digit is displayed in hexadecimal notation. The four decimal predicted values for the addition of the first input numerical data and the second input numerical data or the four decimal predicted values for the subtraction are calculated by using the first input numerical data and the second Predicted value generation circuit 4 for each digit generated for each digit of input numerical data
Adding a carry signal for each digit of the second input numerical data and the output numerical data of the correction circuit 2 in response to the second input numerical data and the output numerical data of the correction circuit 2; Or a carry signal generating circuit 6 generated for the subtraction
And four decimal predicted values for the addition generated for each digit,
Or of the four decimal predictions for subtraction,
Alternatively, a selection is made to select a decimal predicted value determined according to a carry signal of the digit generated for the subtraction and a carry signal of a digit one digit lower than the digit as a decimal result value of addition or subtraction of the digit. A decimal addition / subtraction circuit comprising a circuit 8;