JP2623293B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, for example, a dynamic RA.
It relates to M (Random Access Memory).

B. 2. Description of the Related Art Conventionally, for example, a semiconductor integrated circuit device such as a combination of bipolar technology and MOS technology (bi-MOS), for example, dynamic R
In AM, a MOS transistor is formed in a memory cell portion, and a bipolar transistor is used in a peripheral circuit. In this case, for example, CMOS
(Complementary MOS).

Therefore, various types of capacitor cells have been developed for the capacitors of the memory cells in the semiconductor integrated circuit device as described above in order to reduce the cell area and increase the capacitance of the capacitors.

However, the configuration of the conventional capacitor cell has the following problems.

(1). There is a limit to the reduction of the area of the element part constituting the capacitor, and it is difficult to miniaturize the element part. Further, when the area of the capacitor is reduced, the capacitance itself is reduced.

(2). In addition, there is a limit in increasing the area of the capacitor, and it is difficult to increase the storage capacity.

(3). In the case of a structure in which a capacitor is formed in a trench (groove), in addition to the above (2), a channel is induced on the substrate side, causing a leak current.

C. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device which can reduce the area of an element portion including a capacitor in a semiconductor integrated circuit device, increase the capacitance of the capacitor, and eliminate leakage current. is there.

D. In other words, the present invention provides a semiconductor substrate of the first conductivity type, a plurality of grooves extending from one main surface of the semiconductor substrate to the inside thereof and arranged at intervals from each other, a capacitor and a transistor. A memory cell formed in a first region of the semiconductor substrate; a bipolar transistor formed in a second region of the semiconductor substrate adjacent to the first region in which the memory cell is formed; The above first and second
A buried layer of the second conductivity type buried inside the semiconductor substrate including the region of the above and forming a part of the inner wall of the groove, and an insulating material formed on the inner wall of the groove in the first region A conductive material that is filled in the groove in the first region and is insulated from the semiconductor substrate and the buried layer by the thin film; and a thin film of the groove in the second region. The groove in the first region has an insulating material filled therein, and the conductive material and the buried layer function as electrodes, respectively, and the thin film functions as a dielectric to form the groove. The present invention relates to a semiconductor integrated circuit device comprising a capacitor, wherein the groove in the second region is an element isolation region of an adjacent bipolar transistor.

E. Examples Hereinafter, examples of the present invention will be described.

FIGS. 1 to 6 show an embodiment of the present invention, in which the present invention is applied to, for example, a highly integrated dynamic RAM using a bi-MOS technology.

As shown in FIG. 1, the dynamic RAM according to the present embodiment includes a memory cell unit MC and a bipolar transistor unit BP constituting a peripheral circuit thereof. The peripheral circuit may be, for example, CMOS, but is not shown.

First, a memory cell unit MC (hereinafter simply referred to as MC) will be described. A P ⁻ type epitaxial layer 4 is provided on one main surface of a P ⁻ type silicon substrate 1 with an N ⁺ type buried layer 3 interposed therebetween. An N ⁺ -type source region 18 and an N ⁺ -type drain region 19 are formed in a predetermined pattern on the surface of the P ⁻ -type epitaxial layer 4, and a gate electrode 17 is interposed therebetween through a gate oxide film 16. N-channel MOS transistors (transfer gates) are provided. The source region 18 is provided with a high-concentration N ⁺ -type diffusion region 6 for connecting a capacitor described later.

As shown in the figure, between the source regions 18-18,
It penetrates through the N ⁺ type diffusion region 6 and the N ⁺ type buried layer 3 and further has P ⁻
A trench 8 is formed at a predetermined position until the mold substrate 1 is reached, and a P ⁺ type channel stopper region 2 is formed at the bottom thereof.
Is provided. Then, N ⁺ type polysilicon (field plate) is formed in the trench 8 via an oxide film 10.
The N ⁺ -type buried layer 3 is used together with the N ⁺ -type diffusion region 6 as an electrode of a capacitor. Here, it is characteristic that this N ⁺ -type buried layer 3 is provided in common with the N ⁺ -type buried layer 3 below the bipolar transistor portion BP (hereinafter simply referred to as BP.).

Further, a silicide layer 21 is provided on the surfaces of the source region 18, the drain region 19 and the respective polysilicon layers (the gate electrode 17 and the N ⁺ type polysilicon layer 11) to improve the conductivity. A nitride layer 20 serving as a mask is attached to the side surface of each polysilicon layer, and an insulating layer (filling oxide) 12 is formed on the N ⁺ type polysilicon layer 11.

Further, an insulating layer 22 is applied on the surface, a contact hole 24 is provided in the drain region 19, and a wiring (bit line) 23 made of, for example, aluminum is formed.

The MC is configured as described above. That is, a transfer gate is constituted by the gate electrode (word line) 17, the source region 18, and the drain region 19, and the N ⁺ type buried layer 3 (and further the N ⁺ type diffusion layer 6) is formed in the source region 18. N-type polysilicon layer 11 and insulating oxide film
10 capacitors are connected.

Here, FIGS. 2 to 4 show the MC of FIG. 1, FIG. 2 is a sectional view taken along the line II-II of FIG. 4, and FIG. FIG. 4 is a plan view, FIG.
The figure is a cross-sectional perspective view of the memory cell (the insulating layer 22 and the like are not shown).
It is. However, in FIG. 4, the region of the polysilicon layer 11 is indicated by oblique lines.

On the other hand, as shown in FIG.
A trench groove 8 similar to that described above is formed, and the trench is filled.
The element region is separated by the SiO ₂ layer 9, and in the N ⁻ type diffusion layer 5 on the N ⁺ type buried layer 3 existing in this element region.
A P ^- type base region 13 is formed by diffusion. The base region 13 N ⁺ -type extraction emitter region 14 and P ⁺ -type base electrode region 15 Togaotto s diffusion is formed, also, N ⁺ -type buried layer 3
An N ⁺ type diffusion region 6 is provided thereon, and an N ⁺ type collector electrode extraction region 25 is formed thereon by diffusion. Therefore, in this NPN type vertical bipolar transistor, the collector electrode extraction region 25 and the base region 13 are connected through the N ⁻ type diffusion region 5, the buried layer 3 and the N ⁺ type diffusion region 6. In the drawings, B indicates a base electrode, E indicates an emitter electrode, and C indicates a collector electrode, and is formed of, for example, aluminum. 7 is a field oxide film,
Reference numeral 2 denotes a P ⁺ type channel stopper region similarly to MC.

As described above, according to the memory having the bi-MOS structure of the present embodiment, the N ⁺ -type buried layer 3 and the N ⁺ -type diffusion region 6 are provided in common to MC and BP before the trench 8 is formed. And
Moreover, it is formed so as to surround the trench 8. In the MC, a capacitor using the trench 8 as an electrode is formed with the N ⁺ type buried layer 3 and the N ⁺ type diffusion region 6 as electrodes. On the other hand, BP uses the trench 8 for element isolation. From the above configuration, the following remarkable functions and effects can be obtained.

(1). Since the N ⁺ -type buried layer 3 (and the N ⁺ -type diffusion region 6) serving as an electrode of the capacitor can be formed before the trench 8 is formed by using a known burying technique in BP, a special new process is used. The buried region 3 having a large area can be formed in a predetermined region of the MC and used as a capacitor electrode without requiring any technology (N ⁺
By adding the mold diffusion region 6, the area can be further increased.)

Therefore, the capacity of the MC capacitor can be increased.

(2). The buried region 3 does not need to be precisely controlled as in the case of impurity diffusion, and a wide region can be easily formed by using a known burying technology in BP. Therefore, the capacitance of the capacitor can be effectively increased. In this regard, the device can be manufactured in the same steps as in a normal CMOS type 1M dynamic RAM.

(3). In addition, since the inside of the trench 8 (that is, the polysilicon layer 11) is set to 0 V and charges can be stored on the N ⁺ type region 3 (and further 6), an undesired channel is formed on the substrate side. Formation can be prevented (prevention of leakage current).

(4). Further, since the capacitor is formed by using the trench 8, even though the capacitor capacity is large,
The area occupied by MC is considerably reduced, which is very advantageous for miniaturization and high integration.

(5). In BP, since the trench 8 is used for element isolation, the junction area between the buried layer 3 and the P ⁻ type substrate 1 can be reduced, and the collector parasitic capacitance can be reduced.

Next, a method of manufacturing a memory according to this example will be described with reference to FIG.

First, as shown in FIG. 6A, an N ⁺ -type buried layer 3 is provided on a P ⁻ -type silicon substrate 1 over a region of BP and MC, and further an N ⁻ -type epitaxial layer 5 is formed by a known technique. Next, as shown in FIG. 6B, P
Ions 40 of a type impurity (for example, boron) are implanted, and the conductivity type of the N ⁻ type epitaxial layer 4 is converted to form a P ⁻ type region 4. At the time of the above-described ion implantation, all portions other than the portion into which the ions 40 are implanted (MC in the case of this figure) are covered with a mask (for example, a photoresist), but this is not shown. Similarly, illustration of the following drawings may be omitted.

Then, as shown in FIG. 6C, a known LOCOS (Local Oxida
After the formation of a selective oxide film (field oxide film) 7 by the technique of silicon (field of silicon), ions 30 of an N-type impurity are selectively implanted at a high concentration to form an N ⁺ -type region 6. Note that this
It is desirable that the N ⁺ -type region 6 be made narrow so as not to affect the channel of the transfer gate of the MC. That is, in FIG. 1, the presence of the N ⁺ type region 6 at a position outside the channel of the transfer gate makes it possible to prevent the movement of carriers through this region 6 and to perform the on / off operation of the transfer gate with high reliability. You.

Next, as shown in FIG. 6D, a deep trench 8 reaching the substrate 1 is selectively formed in the semiconductor region by a known dry etching technique, and a P-type trench is formed in the bottom of the trench by ion implantation. Impurity (eg boron) ions
By implanting 70, a P ⁺ type channel stopper region 2 is formed. BP uses this trench 8 for element isolation,
MC uses it as a capacitor.

Then, the SiO ₂ CVD on the entire surface including the trench 8 (Chemi
cal Vapor Deposition) and then dry etching to etch SiO ₂ 9 (etch back)
Then, as shown in FIG. 6E, SiO ₂ 9 is left only in the trench groove 8 of BP. Thereafter, the BP is covered with a mask 31 (for example, a photoresist).

Next, as shown in the enlarged partial cross-sectional view of FIG. 6F, a thin Si ₃ N ₄ film 10a is deposited on the surface of the MC including the trench 8 by CVD, and further thermally oxidized to grow a thin SiO ₂ film 10b. Let me
An insulating film 10 is formed. Then, as shown in FIG. 6F, an N-type polysilicon 11 is deposited on the entire surface by CVD, and a SiO ₂ film 12 is formed on the entire surface by CVD.

Next, as shown in FIG. 6G, etching is performed so that the SiO ₂ film 10, the N-type polysilicon layer 11 and the SiO ₂ film are formed only in the trench 8 of the MC.
Leave the membrane 12. Here, the SiO ₂ film is filled in the recesses on the upper surface of the polysilicon layer 11 to flatten the upper surface.

Next, as shown in FIG. 6H, ions 50 of a P-type impurity (for example, boron) are implanted into a predetermined region of the BP by ion implantation to form a P ⁻ -type base region 13.

Next, as shown in FIG. 6I, the entire surface is thermally oxidized to grow a SiO ₂ film, a gate oxide film 16 is formed, and then polysilicon 17 is further deposited on the entire surface by CVD. At this time, ion implantation of an N-type impurity (eg, As) is performed to
Although the polysilicon layer 17 has a low resistance, it is not shown.

Then, as shown in FIG. 6J, the polysilicon layer 17 of the MC and the gate oxide film 16 are left by patterning, and only the polysilicon 17 of BP is removed by etching, and the SiO ₂ film 16 is patterned.

Next, as shown in FIG. 6K, an N-type impurity (eg, As) 60
Is selectively ion-implanted to form an N ⁺ -type emitter region 14 and an N ⁺ -type collector region 25 in the BP, and at the same time, an N ⁺ -type source region 18 and an N ⁺ -type drain region 19 in the MC, respectively.
Although not shown, a P-type impurity (for example, boron) is selectively ion-implanted in the same manner as above to form a P ⁺ -type base electrode extraction region 15 in BP.

Next, as shown in FIG. 6L, the SiO ₂ layer 20 is selectively formed on the side surface of each polysilicon layer of the MC by a known sidewall technique, and further, for example, titanium is deposited and annealed to anneal the MC. The surface of each polysilicon layer and each N ⁺ type diffusion region is silicided, unnecessary titanium is removed by etching, and a silicide layer 21 is formed. Thereafter, though not shown, the device shown in FIG. 1 is completed by applying an insulating film coating, various wiring processes, and the like by a known method.

As is clear from the manufacturing method described above, the memory having the bi-MOS structure according to the present embodiment uses the specific buried layer usually provided in the bipolar transistor part BP also for the memory cell part MC and uses it as the electrode of the capacitor. Therefore, the electrode of the MC capacitor can be formed at an early stage of the structure process without adding a special process, and the capacitor can be easily formed by using the subsequent trench. Therefore, since the bipolar technology is skillfully applied to the memory cell, the area of the electrode of the capacitor can be increased (that is, the capacitance of the capacitor can be increased). In particular, in this type of semiconductor integrated circuit device, it is an epoch-making means that a capacitor is formed using a trench groove and a low-resistance buried layer is used as an electrode of the capacitor.

The embodiments described above can be further modified based on the technical idea of the present invention.

For example, the shape, arrangement, and the like of the trench groove can be modified, and various dry etching methods and the like can be employed as the formation method. Further, the shape, arrangement, and the like of the buried layer can be further modified. The method of forming each of the above-described regions may be variously changed.

In the above-described example, polysilicon is used as the material of the gate electrode of the MC, but other materials such as tungsten, tantalum, or other high-melting metals or silicide, which is a compound of metal and Si, may be used. An appropriate one may be used instead of the electrode and the aluminum wiring of the MC.

The conductivity type of each of the above-described semiconductor regions may be reversed, or a P-channel MOS may be used for a memory cell. The arrangement of other peripheral circuits can also be changed. The present invention is also applicable to integrated circuit devices other than the above-described dynamic RAM. In the above-described example, the MOS is a horizontal type, but it can be modified to a vertical type MOS. In this case, the degree of integration can be further increased.

F. Advantageous Effects of the Invention As described above, in the present invention, since the capacitor is formed using the groove provided in the semiconductor layer, the occupied area of the planar cell can be reduced. Further, a low-resistance buried layer is formed in the semiconductor layer before forming the groove, and the low-resistance buried layer is formed so as to surround the groove, so that a large buried layer can be formed in a predetermined region, and Since the buried layer is used as an electrode of the capacitor, the capacitance of the capacitor can be effectively increased.
In addition, since charges can be accumulated on the buried layer side, leakage current due to formation of an undesired channel can be prevented.

[Brief description of the drawings]

1 to 6 show an embodiment of the present invention. FIG. 1 is an enlarged sectional view of a main part of a dynamic RAM having a bi-MOS structure, and FIG. 2 is an MC (memory cell section) of FIG. 3) is an enlarged cross-sectional view of the MC of FIG. 1 (although a cross section taken along the line II-II of FIG. 4 described later is shown). FIG. 4 is a plan view of the MC of FIG. 1, FIG. 5 is a cross-sectional perspective view of the MC, FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, and FIG. Figure, Figure 6F, Figure
6G, 6H, 6I, 6J, 6K, and 6L show the first
FIG. 3 is a cross-sectional view sequentially showing a method for manufacturing the device shown in FIG. In the reference numerals shown in the drawings, 1... P ^- type silicon substrate 3... N ⁺ type buried layer 6... N ⁺ type (diffusion) region 8... Trench trench 10... Oxide film 11. Silicon layer 16 Gate oxide film 17 Gate electrode (word line) 18 Source region 19 Drain region 23 Aluminum wiring (bit line) 30, 40, 50, 60, 70 (N-type) Or P-type impurity) ion BP: Bipolar transistor section MC: Memory cell section.

Claims (1)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a plurality of grooves extending from one main surface of the semiconductor substrate to the inside thereof and arranged at intervals from each other, a capacitor and a transistor, A memory cell formed in a first region of the semiconductor substrate; a bipolar transistor formed in a second region of the semiconductor substrate adjacent to the first region in which the memory cell is formed; And a buried layer of a second conductivity type buried in the semiconductor substrate including the second region and forming a part of the inner wall of the groove, and formed on the inner wall of the groove in the first region. A thin film made of an insulating material, a conductive material filling the inside of the groove in the first region, and insulated from the semiconductor substrate and the buried layer by the thin film; and the second region And an insulating material filled in the groove in the first region, wherein the groove in the first region is such that the conductive material and the buried layer each function as an electrode, and the thin film is a dielectric material. Functioning as the above capacitor,
2. The semiconductor integrated circuit device according to claim 1, wherein the trench in the second region is an element isolation region of an adjacent bipolar transistor.