JP2628207B2 - Print timing correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a print timing correction device in a serial dot printer, a clock circuit (1) for generating a basic clock, a basic clock is counted, and when the counted value reaches a set value, A carrier motor timer (2) for outputting a carrier motor clock and returning to an initial value; counting a basic clock; when the counted value reaches a set value, outputting a print timing clock and returning to an initial value; When a signal of a predetermined value (low) is applied to the clear terminal, the count value returns to the initial value, and while the signal of the predetermined value (low) is applied to the clear terminal, the counting of the basic clock is stopped. And a carrier motor clock that is counted when the carrier motor clock is counted and a predetermined value (low) signal is applied to the clear terminal. Scan counter (3)
A pulse counter for print timing (4) that is cleared when a signal of a predetermined value (low) is applied to a clear terminal while counting a clock for print timing, a first register for comparison (5A), The second comparison register (5B) is compared with the count value of the carrier motor pulse counter (3) and the value of the first comparison register (5A). low), and when they do not match, a first comparator (6A) that outputs another predetermined value (high) signal, and the count value of the print timing pulse counter (4) and the first comparator (6A). 2 is compared with the value of the comparison register (5B), and when they match, a signal of a predetermined value (low) is output. When they do not match, a signal of another predetermined value (high) is output. Second
Set the value of the comparator (6B) and the carrier motor timer (2) to _TCR ,
The setting value of the comparison register (5A) is A, the setting value of the print timing timer (9) is T _HM , and the second comparison register (5A)
When the set value of B) and _{B, T CR × A-T} HM × B ≧ 0 The condition value carrier motor timer that satisfies formula (2), printing timing timer (9), the Setting value processing means (13) for setting each of the first comparison register (5A) and the second comparison register (5B), and a clear terminal of the carrier motor pulse counter (3) and printing The output of the first comparator (6A) is applied to the clear terminal of the timing pulse counter (4), and the output of the second comparator (6B) is applied to the clear terminal of the print timing timer (9). When the output is applied and the print timing pulse counter (4) is cleared, the output of the second comparator (6B) changes to another predetermined value (hig
h).

[Industrial applications]

The present invention relates to a serial dot printer using a stepping motor as a serial motor.
Carrier that gives carrier motor excitation timing
The present invention relates to a print timing correction device that corrects a difference between a motor clock and a print timing clock.

[Conventional technology]

FIG. 4 is a diagram for explaining generation of a carrier motor clock and a print timing clock in a serial dot printer. In the figure, reference numeral 21 denotes a clock generator, 22 denotes a CR motor timer, and 23 denotes a print timing timer. Note that CR is an abbreviation for carrier, CR clock is a carrier motor clock, HM is an abbreviation for hammer, and HM clock is a print timing clock.

The clock generator 21 has a frequency of, for example, 1 MHz (the period is 1 μs). The CR timer 22 counts the clock output from the clock generator 21, and when the count value reaches a predetermined value, outputs a CR clock and returns to the initial value. The print timing timer 23 performs the same operation. The CR clock provides timing for exciting the winding of the stepping motor that moves the carrier. The HM timing clock gives the timing for exciting the solenoid in the print head.

FIG. 6 is a diagram showing an outline of the stepping motor shown in FIG. 5; A cross-shaped rotor is arranged in the stator, and the stator is provided with A-phase, A-phase, B-phase, and B-phase.

FIG. 6 is a diagram for explaining the relationship between the CR clock and the winding excitation. A switch (not shown) for supplying a current to the A-phase winding of the stepping motor is turned on only during # 1 to # 3 CR clocks, # 5 to # 7 CR clocks,. A
The phase, B phase, and B phase are as shown in the figure.

[Problems to be solved by the invention]

In the conventional circuit configuration, when it is desired to operate the carrier motor timer and the print timing timer at a certain fixed frequency ratio, the interval between each clock pulse is limited to an integral multiple of the basic clock. Otherwise, if each timer is set to an approximate value so as to be close to the ideal frequency ratio and the timer is operated, the printing error occurs due to the accumulation of the error.

The present invention has been made in view of this point,
It is an object of the present invention to correct a shift of a print position by synchronizing a clock for a carrier motor and a clock for a print timing at a constant interval in a serial dot printer.

[Means for solving the problem]

FIG. 1 is a diagram illustrating the principle of the present invention. A printing timing correction apparatus according to the present invention includes a clock circuit (1) for generating a basic clock, a carrier for counting the basic clock, and outputting a carrier motor clock when the counted value reaches a set value and returning to a default value.・ The motor timer (2) and the basic clock are counted, and when the counted value reaches the set value, the print timing clock is output and returned to the initial value, and a signal of a predetermined value (low) is applied to the clear terminal. When the count value returns to the initial value, a print timing timer (9) that stops counting the basic clock while a signal of a predetermined value (low) is applied to the clear terminal, and a carrier motor clock are used. The pulse counter for carrier motor which is cleared when a signal of a predetermined value (low) is applied to the clear terminal upon counting (3)
A pulse counter for print timing (4) that is cleared when a signal of a predetermined value (low) is applied to a clear terminal while counting a clock for print timing, a first register for comparison (5A), The second comparison register (5B) is compared with the count value of the carrier motor pulse counter (3) and the value of the first comparison register (5A). low), and when they do not match, a first comparator (6A) that outputs another predetermined value (high) signal, and the count value of the print timing pulse counter (4) and the first comparator (6A). The value of the second comparison king register (5B) is compared, and if they match, a signal of a predetermined value (low) is output. If they do not match, a signal of another predetermined value (high) is output. Second
Set the value of the comparator (6B) and the carrier motor timer (2) to _TCR ,
The setting value of the comparison register (5A) is A, the setting value of the print timing timer (9) is T _HM , and the second comparison register (5A)
When the set value of B) and _{B, T CR × A-T} HM × B ≧ 0 The condition value carrier motor timer that satisfies formula (2), printing timing timer (9), the Setting value processing means (13) for setting each of the first comparison register (5A) and the second comparison register (5B), and a clear terminal of the carrier motor pulse counter (3) and printing The output of the first comparator (6A) is applied to the clear terminal of the timing pulse counter (4), and the output of the second comparator (6B) is applied to the clear terminal of the print timing timer (9). When the output is applied and the print timing pulse counter (4) is cleared, the output of the second comparator (6B) changes to another predetermined value (hig
h). The set value processing means (13) is constituted by, for example, a microprogram and a processor.

〔Example〕

FIG. 2 is a block diagram of one embodiment of the present invention. In the figure, 1 is a clock generator, 2 is a timer for a CR motor, 3 is a pulse counter for CR, 4 is a pulse counter for HM, 5A and 5B are comparison registers, 6A and 6B are comparators, and 7 is a comparator.
CR motor excitation phase generation circuit, 8 is CR motor driver, 9
Denotes a print timing timer, 10 denotes a print head drive on-time generating circuit, 11 denotes a print head driver, and 12 denotes a crystal oscillator.

The clock generator 1 receives a signal from the crystal oscillator 12 and outputs a basic clock. The CR timer 2 counts the basic clock, and outputs a CR clock when the counted value reaches a predetermined set value, and returns to the initial value. The set value of the CR timer 2 can be changed by a microprogram. The CR pulse counter 3 counts the CR clock and is cleared when a low level signal is input to its clear terminal. The HM pulse counter 4 counts the HM clock and is cleared when a low level signal is input to the clear terminal. The value of the comparison register 5A can be changed by a microprogram. The same applies to the comparison register 5B. The comparator 6A compares the value of the pulse counter 3 with the value of the comparison register 5A, and outputs a low-level signal when they match. The output of the comparator 6A is applied to the clear terminals of the pulse counters 3 and 4. Comparator 6
B compares the value of the pulse counter 4 with the value of the comparison register 5B, and outputs a low-level signal when they match. The output of the comparator 6B is applied to the clear terminal of the print timing timer 9. The CR motor excitation phase generation circuit 7
In accordance with an instruction from the microprogram, a control signal for controlling the current of the motor winding is generated in synchronization with the CR clock. A control signal output from the CR motor excitation phase generation circuit 7 is sent to a CR motor (stepping motor) via a CR motor driver 8. The print timing timer 9 counts the basic clock, and when the count value reaches a predetermined set value, outputs the print timing clock and returns to the initial value. The set value of the print timing timer 9 can be changed by a microprogram. The print head drive on-time generation circuit 10 generates a control signal for controlling the current of the solenoid of the print head in synchronization with the HM clock according to an instruction from the microprogram. The control signal output from the print head drive on-time generation circuit 10 is sent to the print head via the print head driver 11.

FIG. 3 is a diagram showing waveforms at various parts in the embodiment of the present invention. In the figure, T _CR is setting the CR motor timer 2, T _HM indicates the set value of the print timing timer 9, respectively.

In the illustrated example, a _{T CR × 4 = T HM ×} 5 + Δe, 4 is set in the comparison register 5A in this case, 5 is reset to the comparison register 5B.

The falling edge of the output of comparator 6A becomes the start point of the synchronization zone. When the value of the pulse counter 4 matches the value of the comparison register 5B and the output of the comparator 6B goes low, the print timing timer 9 is cleared and the
While the output of 6B is at a low level, the print timing timer 9 remains stopped. When the value of the pulse counter 3 matches the value of the comparison register 5A, the comparator 6A outputs a low level, and the pulse counter 3 and the pulse counter 4 are cleared. When the pulse counter 4 is cleared, the output of the comparator 6B goes high, thereby releasing the stop of the print timing timer.

A specific example will be described. The basic clock is 1 MHz (period = 1 μs).

In this case, since the frequency ratio is CR: HM = 8: 9, the period ratio is C
Although R: HM = 9: 8, the value actually set in the timer is an integral multiple of the basic clock (1 MHz = 1 μs). Therefore, approximate values are set in the CR motor timer and the print timing timer. Since the frequencies are 4800Hz and 5400Hz, the greatest common divisor is 600. Since 4800 ÷ 600 = 8,5400 ÷ 600 = 9, 8 is set in the comparison register 5A and 9 is set in the comparison register 5B. However, there needs to be _{T CR × A-T HM ×} B ≧ 0. In this case, an error of 209 × 8−185 × 9 = 7 (μs) occurs in each synchronization zone, but the error can be corrected by the circuit of the embodiment. That is, the print timing clock is stopped by the error (7 μs),
At the start of the next synchronization zone, both timers start simultaneously.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, CR
Even if the values set for the motor timer and the print timing timer are approximate, the two timers can be synchronized at regular intervals, so that accumulation of errors can be prevented at any frequency ratio. This can also prevent the printing position from being shifted due to printing.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is a diagram showing waveforms at various parts in the embodiment of the present invention, and FIG. FIG. 5 is a diagram illustrating the outline of a carrier motor, and FIG. 6 is a diagram illustrating the relationship between a CR clock and winding excitation. 1 ... clock generator, 2 ... CR motor timer, 3 ...
… CR pulse counter, 4… HM pulse counter, 5A and 5B… Comparison registers, 6A and 6B… Comparator, 7
………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………….

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-5967 (JP, A) JP-A-61-22973 (JP, A) JP-A-63-57253 (JP, A) 222971 (JP, A) JP-A-53-55170 (JP, A) JP-A-62-156960 (JP, A) JP-A-64-47556 (JP, A) JP-A-2-36970 (JP, A)

Claims (1)

(57) [Claims] A clock circuit (1) for generating a basic clock, a carrier motor timer for counting the basic clock, outputting a carrier motor clock when the counted value reaches a set value, and returning to an initial value. (2) The basic clock is counted, and when the counted value reaches the set value, the print timing clock is output and returned to the initial value. When the signal of the predetermined value (low) is applied to the clear terminal, the total is counted. The numerical value returns to the initial value, and while the signal of the predetermined value (low) is applied to the clear terminal, the print timing timer (9) that stops counting the basic clock and the carrier motor clock are counted and cleared. The carrier motor pulse counter (3), which is cleared when a signal of a predetermined value (low) is applied to the terminal, and counts the print timing clock and sets the predetermined value to the clear terminal. A pulse counter for print timing (4), which is cleared when a (low) signal is applied, a first comparison register (5A), a second comparison register (5B), and a carrier motor The count value of the pulse counter (3) is compared with the value of the first comparison register (5A). When both values match, a signal of a predetermined value (low) is output. Output a signal of a predetermined value (high)
The comparator (6A) compares the count value of the print timing pulse counter (4) with the value of the second comparison register (5B), and when they match, a signal of a predetermined value (low) And a second comparator (6B) that outputs a signal of another predetermined value (high) when the two do not coincide with each other. The set value of the carrier motor timer (2) is set to _TCR , the first The set value of the comparison register (5A) is A, the set value of the print timing timer (9) is T _HM , and the second comparison register (5B)
When the setting value is _{B, T CR × A-T} HM × B ≧ 0 The condition value carrier motor timer that satisfies formula (2), printing timing timer (9), first Setting value processing means (13) for setting each of the comparison register (5A) and the second comparison register (5B), and a clear terminal of the carrier motor pulse counter (3) and a print timing. The output of the first comparator (6A) is applied to the clear terminal of the pulse counter (4), and the second terminal is applied to the clear terminal of the print timing timer (9).
When the output of the comparator (6B) is applied and the pulse counter (4) for print timing is cleared, the output of the second comparator (6B) becomes another predetermined value (high).
A print timing correction device characterized by being changed to: