JP2629639B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a field effect transistor (FET) having a back gate electrode for compensating or suppressing fluctuations in drain current.
And a method of manufacturing the same.

[0002]

2. Description of the Related Art A field effect transistor (FE) using a compound semiconductor represented by GaAs, InP or the like.
In T), a phenomenon in which the drain current fluctuates due to a temperature change, and a phenomenon in which the drain current fluctuates due to channel modulation due to a change in charge at a deep level of the semi-insulating substrate, a so-called back gate effect phenomenon often occurs. Therefore, conventionally, a structure in which a p-type conductive substrate is used as a growth substrate and this is used as it is as a back gate electrode (FIG. 4A)
And a structure in which a conductive layer such as p-GaAs is provided between a semi-insulating substrate and a channel layer and used as a back gate electrode as shown in JP-A-5-343434 (FIG. b)) was used to address these problems. Incidentally, in FIGS. 4A and 4B,
401 is a p-GaAs substrate, 402 is an i-GaAs channel layer, 403 is an n-Al _0.2 Ga _0.8 As electron supply layer, 404 is an n ⁺ GaAs cap layer, 405 is a gate electrode, 405 is a drain electrode, and 406 is a source electrode. , 4
08 is a parasitic capacitance due to the back gate electrode, 409 is a semi-insulating GaAs substrate, 410 is an i-GaAs buffer layer,
Reference numeral 411 denotes a p-GaAs substrate. In other words, in these structures, the potential of the channel is modulated by using the provided back gate electrode, thereby compensating for the fluctuation of the drain current due to the temperature change, or by fixing the potential below the channel. By taking the method of suppressing the back gate effect, the phenomenon of the back gate effect due to the fluctuation of the drain current has been avoided.

[0003]

The field effect transistor (FET) having the back gate electrode described above is
The structure has a structure in which the back gate electrode greatly spreads beyond the channel layer immediately below the gate electrode to be modulated. For this reason, a large parasitic capacitance is newly generated between the back gate electrode and the source / drain electrode, wiring, or the like. Therefore, in the element having the conventional structure, there is a problem that the high frequency performance is greatly deteriorated.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to solve such a conventional problem and to reduce the increase in the regulated capacitance by the back gate electrode as much as possible. Is to provide.

For this reason, the field effect transistor (FET) of the present invention comprises, on a semiconductor substrate, a conductive layer of one conductivity type serving as a back gate electrode and a channel layer of another conductivity type different from the conductive layer. At least two layers are formed,
Further, the active layer region including the conductive layer and the channel layer is gradually narrowed from the surface of the active layer immediately below and around the gate electrode in the depth direction of the substrate, and at least the ohmic electrode By partially contacting a part of the narrowed active layer, the overlap between the back gate electrode and other electrodes and wiring is significantly reduced,
The above objective has been achieved.

The field effect transistor (F) of the present invention
The manufacturing method of ET) includes forming a conductive layer of one conductivity type and a channel layer of another conductivity type different from the conductive layer on a semiconductor substrate, and forming a gate electrode on the channel layer. A step of covering the periphery of the formed gate electrode with at least one or more kinds of insulating films or organic films, and performing ion implantation from both sides of the covered insulating film or organic film from an oblique direction to the substrate, Forming a ohmic electrode such that at least a portion of the active layer region is at least partially in contact with a portion of the active layer region that does not have a high resistance after removing the insulating film or the organic film. , The above structure is realized.

[0007]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

[Embodiment 1] FIGS. 1A and 1B show a field effect transistor (FET) showing an embodiment of the present invention.
1 is a structural cross-sectional view and a structural plan view of FIG. Referring to FIG. 1A, a first embodiment of the present invention is a semi-insulating GaAs.
An i-GaAs buffer layer 102 (400 nm thick) and a p-GaAs layer 103 (20 nm thick, carrier density 2 × 10 ¹⁸ c) serving as a back gate electrode are formed on a substrate 101.
m ⁻³ ) and p-Al _0.2 Ga _0.8 As layer 104 (thickness 1).
0 nm, carrier density 2 × 10 ¹⁸ cm ⁻³ ), i-GaAs
s channel layer 105 (50 nm thick) and n-Al
_{A 0.2} Ga _0.8 As electron supply layer 106 (thickness 30 nm, carrier density 2 × 10 ¹⁸ cm ⁻³ ) is sequentially formed.
Further, these active layer regions 107 are gradually narrowed in the depth direction of the substrate. Also, n-Al _0.2 Ga
_{On the 0.8} As electron supply layer 106, a part of the side surface is made of SiO.
A Y-type gate electrode 108 having a gate length of 0.25 μm covered with the _two films 109 and an AuGe / Ni / electrode formed in a self-aligned manner with respect to the Y-type gate electrode 108 and partially contacting the active layer region 107. Source electrode 110 made of Au
And a drain electrode 111. Note that the portion described on the Y-type gate electrode 108 is such that the source electrode 110 and the drain electrode 111 are connected to the Y-type gate electrode 10.
8 formed in a self-aligned manner with respect to
It is a Ge / Ni / Au layer 112.

Referring to FIG. 1B, in the embodiment of the present invention, a back gate electrode 113 in an active layer region 107 is connected to a back gate electrode connected through a through hole from the substrate surface. It comprises an electrode 114, a Y-type gate electrode 108, a source electrode 110 and a drain electrode 111.

[Embodiment 2] A second embodiment of the present invention will be described. 2 (a)-(e) and FIG. 3 (a)-
(D) is a main process drawing of the field-effect transistor showing the second embodiment.

First, as shown in FIG. 2A, an i-GaAs buffer layer 202 (400 nm thick) and a p-GaAs layer 203 serving as a back gate electrode are formed on a semi-insulating GaAs substrate 201 by MBE. (Thickness 20 nm, carrier density 2 × 10 ¹⁸ cm ⁻³ ) and p-Al _0.2 Ga _0.8 As
Layer 204 (10 nm thick, carrier density 2 × 10 ¹⁸ cm)
^-3 ), i-GaAs channel layer 205 (50 n thick)
m) and n-Al _0.2 Ga _0.8 As electron supply layer 20
6 (thickness 30 nm, carrier density 2 × 10 ¹⁸ cm ⁻³ ) are sequentially grown, and a SiO ₂ film 207 having a thickness of about 300 nm is formed on the n-Al _0.2 Ga _0.8 As electron supply layer 206 by a thermal CVD method. To form Next, the SiO ₂ film 2
07, a PR film 208 is formed, and P
The R film 208 is patterned, and as shown in FIG. 2B, the SiO ₂ film 207 is dry-etched using a CF ₄ gas 209 to form an opening 210 having a width of about 0.5 μm. Next, after removing the PR film 208, FIG.
As shown in, SiO ₂ of about 300nm by thermal CVD
A film 211 is formed on the entire surface. Next, as shown in FIG. 2D, an anisotropic dry etching of the SiO ₂ film 211 is performed by using a CF ₄ gas 212 so that the side wall 2 is formed in the opening 210.
13 (about 200 nm thick). Next, FIG.
As shown in (e), using a patterned PR film 214, Ti / Pt / Au is deposited as a gate electrode 215 by a thickness of about 20 nm / about 50 nm / about 250 nm. Next, after removing unnecessary PR and deposited metal by a lift-off method, as shown in FIG.
Using the mask 15 as a mask, the SiO ₂ film is removed by anisotropic dry etching using the CF ₄ gas 301. Next, as shown in FIG.
The SiO ₂ film 302 is formed of, by anisotropic dry etching using CF ₄ gas 303 to form sidewall 304 of SiO ₂ around the gate electrode. Next, as shown in FIG. 3C, after covering the upper portion of the gate electrode 215 and the back gate electrode lead-out region with the PR film 305, the substrate is rotated at an angle of, for example, about 32 degrees with respect to the vertical direction of the substrate. While implanting B ions 306 (2 × 10 ¹³ / cm ⁻² ; 1)
50 keV and 30 keV are implanted twice) to form a high-resistance region 307 having a high resistance. Next, PR film 3
After removing 05, the side wall 304 of SiO ₂ formed around the gate electrode is further removed by anisotropic dry etching using CF ₄ gas. Next, an opening made of a PR film is provided in the back gate electrode lead-out region, and back etching is performed using wet etching with a mixed solution of phosphoric acid, hydrogen peroxide and water, and selective dry etching with a mixed gas of BCl ₃ and SF _6. A through hole to the gate electrode is formed, and a p-type ohmic electrode is further formed. Next, as shown in FIG.
An ohmic metal 308 is vapor-deposited in a self-aligned manner as a mask, and heat treatment is performed to complete a field effect transistor (FET) having a structure shown in FIGS. 1A and 1B.

[0012]

As described above, the field effect transistor (FET) of the present invention has a structure in which one conductive type conductive layer serving as a back gate electrode and another conductive layer different from the conductive layer are formed on a semiconductor substrate. At least two conductive channel layers are formed, and further, the active layer region including the conductive layer and the channel layer extends in the depth direction of the substrate from the surface of the active layer immediately below the gate electrode and around the gate electrode. On the other hand, it is characterized in that it is gradually narrowed, and at least a part of the ohmic electrode is in contact with a part of the narrowed active layer. For this reason, the area of the back gate electrode is smaller than the area of the surface of the active layer, and hardly overlaps with other electrodes and wirings other than the gate electrode. Therefore, the generation of the parasitic capacitance due to the back gate electrode can be reduced as much as possible, and the high-frequency performance of the device can be improved.
Further, in the present structure, since a part of the ohmic electrode is in contact with a part of the active layer whose resistance is not increased, the parasitic resistance can be easily reduced.

In the method of manufacturing a field effect transistor according to the present invention, the back gate electrode and the channel layer are not manufactured by activation by ion implantation, and a region having a high resistance in a self-aligned manner can be formed. This has the effect that the channel of the element can be easily shortened.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a structure of a field effect transistor according to a first embodiment of the present invention, wherein FIG. 1A is a diagram showing a cross-sectional structure thereof, and FIG. 1B is a diagram showing a planar structure thereof.

FIG. 2 (a), (b), (c), (d) and (e)
FIGS. 7A and 7B are element process diagrams illustrating a manufacturing process of the field-effect transistor according to the second embodiment of the present invention. FIGS.

FIGS. 3 (a), (b), (c) and (d) are elementary process drawings showing a manufacturing process of a field-effect transistor according to a second embodiment of the present invention.

FIGS. 4A and 4B are cross-sectional views showing the structure of a conventional field-effect transistor.

[Explanation of symbols]

Reference Signs List 101 semi-insulating GaAs substrate 102 i-GaAs buffer layer 103 p-GaAs layer 104 p-Al _0.2 Ga _0.8 As layer 105 i-GaAs channel layer 106 n-Al _0.2 Ga _0.8 As electron supply layer 107 active layer region 108 Y type Gate electrode 109 SiO ₂ film 110 Source electrode 111 Drain electrode 112 AuGe / Ni / Au layer 113 Back gate electrode 114 Leader electrode of back gate electrode 201 Semi-insulating GaAs substrate 202 i-GaAs buffer layer 203 p-GaAs layer 204 p− Al _0.2 Ga _0.8 As layer 205 i-GaAs channel layer 206 n-Al _0.2 Ga _0.8 As electron supply layer 207 SiO ₂ film 208 PR film 209 CF ₄ gas 210 Opening 211 SiO ₂ film 212 CF ₄ gas 213 Side wall 214 PR film 215 Get Gate electrode 301 CF ₄ gas 302 SiO ₂ film 303 CF ₄ gas 304 sidewall 305 PR film 306 B ions 307 high resistance region 308 ohmic metal 401 p-GaAs substrate 402 i-GaAs channel layer 403 n-Al _0.2 Ga _0.8 As electron Supply layer 404 n ⁺ GaAs cap layer 405 Gate electrode 406 Drain electrode 407 Source electrode 408 Parasitic capacitance due to back gate electrode 409 Semi-insulating GaAs substrate 410 i-GaAs buffer layer 411 p-GaAs substrate

Claims (3)

(57) [Claims] At least two layers of a conductive layer of one conductivity type serving as a back gate electrode and a channel layer of another conductivity type different from the conductive layer are formed on a semiconductor substrate,
Further, the active layer region including the conductive layer and the channel layer is gradually narrowed in the depth direction of the substrate from immediately below the gate electrode and from the surface of the active layer around the gate electrode, and A semiconductor device, wherein at least a part of an ohmic electrode is in contact with a part of the narrowed active layer. 2. A method for manufacturing a semiconductor device according to claim 1, further comprising: forming a conductive layer of one conductivity type and a channel layer of another conductivity type different from the conductive layer on a semiconductor substrate. Forming a gate electrode on the channel layer; covering the periphery of the formed gate electrode with at least one or more types of insulating films or organic films; Performing ion implantation from an oblique direction of the substrate to increase the resistance of the conductive layer and a portion of the channel layer; and removing a portion of the active layer region that has not been increased in resistance after removing the insulating film or the organic film. Forming an ohmic electrode so that at least a portion thereof is in contact with the semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein at least one gate electrode is formed around said formed gate electrode.
The step of covering with more than one kind of insulating film or organic film, after forming a gate electrode on the substrate, including the gate electrode,
A method of manufacturing a semiconductor device, comprising: a step of depositing an insulating film on the entire surface of the substrate; and a step of performing anisotropic dry etching on the insulating film to leave an insulating film only on sidewalls of the gate electrode. .