JP2629652B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly, to a field effect transistor having InAs on an InP substrate as an operating layer and exhibiting a high cutoff frequency and a high transconductance and having excellent high frequency characteristics.

[0002]

2. Description of the Related Art Conventionally, InAlA using an InP substrate is used.
In the s / InGaAs field effect transistor, a structure in which the InAs composition ratio of the InGaAs operation layer is increased has been used in order to improve the high frequency characteristics. A simple example is a structure using an InAs layer as an operation layer. This structure is described in, for example, Tatsushi Akazaki et al. IEEE ELECTORON DEVICE LET by Tatsushi Akazaki et al.
Reported in TERS 13 325 (1992).

FIG. 3 shows a cross-sectional structure diagram of a field effect transistor reported in this document. An InAlAs buffer layer 302 is grown on an InP (100) just substrate 301, and an InGa with an InAs composition ratio of 0.53 is formed thereon.
Growing an As operation layer 303, an InAs operation layer 304, and an InGaAs operation layer 305 having an InAs composition ratio of 0.53;
Further, the InAlAs spacer layer 306, n-InAlA
s electron supply layer 307, InAlAs Schottky layer 30
8, n-InAlAs cap layer 309, n-InGa
A As cap layer 310 is grown. And n-In
A source electrode and a drain electrode 313 are formed on the GaAs cap layer 310, and the InAlAs Schottky layer 308 is formed.
A gate electrode 312 is formed in the recessed portion exposing the surface of.

In this structure, the operating layer includes an InAs layer having a conduction band discontinuity larger than that of the InGaAs layer having an InAs composition ratio of 0.53 than the InGaAs layer having an InAs composition ratio of 0.53. More electrons can be confined in the operation layer as compared with the structure described above. Further, the InAs layer is made of InAs having an InAs composition ratio of 0.53.
Electrons can be transported at a higher speed than the GaAs layer. for that reason,
The field effect transistor having this structure exhibits a higher cutoff frequency and transconductance than those using only InGaAs having an InAs composition ratio of 0.53 for the operation layer, and the high-frequency characteristics of the transistor are improved.

[0005]

In the above-mentioned prior art, the crystallinity deteriorates with an increase in the InAs composition ratio of the InGaAs operation layer. Therefore, the thickness of the InAs operation layer has been limited to about 4 nm. . When an InAs layer as thin as about 4 nm is used for the operation layer,
Electrons ooze from the InAs layer to the InGaAs layer, and only about 50% of the electrons during operation accumulate in the InAs layer, which can be expected to have excellent electron transport characteristics.

The exuded electrons have much lower electron transport characteristics than InAs, and the InAs composition ratio of InAs is 0.53.
Because of the presence in the As layer, the excellent electron transport characteristics of the InAs layer are hardly reflected in the transistor characteristics, and it has not been possible to expect sufficient cutoff frequency and improvement in the transconductance.

Conventionally, it has been considered that the reason why the crystallinity is degraded when the InAs composition ratio of the InGaAs operation layer is increased is that the lattice mismatch of the operation layer with the InP substrate becomes large. However, according to the experimental results of the present inventors, it has been found that when only InAs is grown only on In _0.53 Ga _0.47 As, a growth layer with good crystallinity can be obtained up to about 8 nm.

The reason why an In _0.53 Ga _0.47 As layer with good crystallinity cannot be grown on a thick InGaAs active layer (for example, an InAs layer) having a high InAs composition ratio is considered as follows. Considering the interface between the InAs layer and the In _0.53 Ga _0.47 As layer grown thereon, the difference in surface free energy between InAs and the In _0.53 Ga _0.47 As layer is large, and the interface free energy between the layers is large. large. Therefore, InA
When In _0.53 Ga _0.47 As is grown on the s layer, irregularities occur in the growth layer at the hetero interface, and the crystallinity deteriorates. And when the flatness of the growth layer at the hetero interface is impaired,
The crystallinity of the underlying InGaAs active layer (for example, InAs layer) with a high InAs composition ratio also deteriorates. This deterioration in crystallinity is further promoted when the thickness of the InAs layer is large and the strain energy stored therein is large.

Therefore, in the conventional structure, when the thickness of the InAs layer exceeds 4 nm, or when the composition ratio of InAs is 0.1 nm.
53 or more other InGaAs layers are 4 nm thick InAs
When it is disposed below the layer, in addition to the deterioration of the crystallinity, the electrons are scattered by the unevenness at the hetero interface, and the electron transport characteristics are deteriorated.

The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object the first object is to form an InAs layer of 4 nm or more while maintaining a good crystal structure. Second, electrons that have oozed out of the InAs layer can be confined in an operation layer having much better electron transport characteristics than the In _0.53 Ga _0.47 As layer. By achieving these, an object is to provide a field-effect transistor exhibiting a higher cut-off frequency and transconductance than the conventional example and having excellent high-frequency characteristics.

[0011]

According to the present invention, there is provided a field effect transistor having an InAs operation layer and a carrier supply layer formed on an InP substrate according to the present invention. A field effect transistor, wherein a graded operation layer in which the composition ratio of InAs gradually decreases from 1 to 0.53 from the InAs operation layer toward the carrier supply layer is inserted between the field effect transistor and the carrier supply layer. , Are provided.

[0012]

In the field effect transistor according to the present invention, I
The InAs composition ratio of I n on the carrier supply layer side of the nAs operation layer
From 1 to 0 .0 from the nAs layer side to the carrier supply layer side.
An InGaAs layer continuously changed up to 53 is provided. InAs layer and InAs lattice-matched to the InP substrate
InGaAs between the InAlAs layer having a composition ratio of 0.52
By continuously changing the InAs composition ratio of the layer,
The difference in surface free energy and the interface free energy between the respective layers can be reduced, and each layer having a smooth heterointerface can be obtained. As a result, deterioration of electron transport characteristics due to scattering caused by unevenness at the hetero interface is suppressed.

The InGaAs layer in which the InAs composition ratio is continuously changed from 1 to 0.53 from the InAs layer side to the carrier supply layer side has an InAs lattice matching with the InP substrate.
Since the conduction band discontinuity is larger in the InAlAs layer than in the GaAs layer, electrons oozing out of the InAs layer also
In in which the composition ratio of InAs adjacent to the s layer continuously changes
It is confined in the GaAs layer. This layer in which the InAs composition ratio changes continuously is composed of InG having an InAs composition ratio of 0.53.
Since it has better electron transport characteristics than the aAs layer, the cutoff frequency and the transconductance can be improved, and a field effect transistor having excellent high frequency characteristics can be provided.

Further, by providing the InGaAs layer in which the InAs composition ratio is continuously changed from 1 to 0.53, the InAs composition ratio is 0.53 below the InAs operation layer.
It becomes possible to arrange a higher In _x Ga _{1 -x} As (0.55 <x <1) layer. High I below the InAs working layer
When an InGaAs layer having an nAs composition ratio is provided, InAs
Electrons that seep out of the active layer are confined in the high InAs composition InGaAs layer adjacent to the InAs layer, and the high InAs composition InGaAs layer is better than the InAs composition 0.53 InGaAs lattice-matched to the InP substrate. Because of its excellent electron transport characteristics, it is possible to realize higher cut-off frequency and transconductance.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1A is a sectional view showing a first embodiment of the present invention, and FIG. 1B is an energy band diagram of the conduction band. As shown in FIG. 1A, in the field-effect transistor of this embodiment, an InAlAs buffer layer 102 (for example, an InAs composition ratio of 0.52 and a film thickness of 200 nm) and an InGaAs operation layer 103 (for example, InAs) are formed on an InP substrate 101. Composition ratio 0.53, film thickness 13n
m), the InAs operation layer 104 (for example, a film thickness of 4 nm),
The InGaAs graded operation layer 105 (for example, having a film thickness of 2) in which the nAs composition ratio was continuously changed from 1 to 0.53.
nm), an InGaAs active layer 106 (for example, an InAs composition ratio of 0.53, a film thickness of 1 nm), an InAlAs spacer layer 107 (for example, an InAs composition ratio of 0.52, a film thickness of 4 n)
m), InAlAs carrier supply layer 108 (for example, In
As composition ratio 0.52, film thickness 20 nm, dopant Si concentration 3 × 10 ¹⁸ cm ⁻³ ), InAlAs Schottky layer 1
09 (for example, InAs composition ratio 0.52, film thickness 20 nm)
Are sequentially grown, and a source electrode 110, a gate electrode 111, and a drain electrode 112 are formed thereon.

In the field effect transistor thus configured, InGaAs is formed on the InAs operation layer 104.
When the graded layer 105 is grown, the growth can be performed in a state where the surface free energy difference and the interface free energy are small, so that a flat crystal layer with good crystallinity can be obtained.

The energy band diagram of FIG. 1B shows the change of the conduction band near the InGaAs operation layer of this structure. The horizontal axis represents the thickness of each layer of the structure shown in FIG. The axis is the conduction band energy. This FIG. 1 (b)
The conduction band of the As operation layer 104 and the InGaAs graded operation layer 105 (2 nm in thickness) where the InAs composition ratio is continuously changed from 1 to 0.53 are lower than the Fermi level and higher than the Fermi level, for example, In. _0.53 Ga
_This indicates that electrons can be confined at a much higher probability than the InGaAs active layer 103 made of _0.47 As, and that the InAs active layer 1 is expected to have high electron transport characteristics.
04, it can be seen that most of the electrons during operation can be confined in the InGaAs graded layer 105 having a high InAs composition ratio.

With such a structure, a high InAs composition layer among the operation layers, that is, the InAs layer 104 (4 nm thick) / InGaAs graded layer 105 (InA
s composition ratio changes continuously from 1 to 0.53, film thickness 2n
m) can confine about 80% of the electrons
Due to the high transport characteristics of the high InAs composition layer, a field effect transistor having excellent high frequency characteristics exhibiting high cutoff frequency and transconductance can be obtained.

In this embodiment, the high In of the operating layers
The layers having the As composition ratio were the InAs operation layer 104 (film thickness 4 nm) / InGaAs graded operation layer 105 (InAs composition ratio continuously changed from 1 to 0.53, film thickness 2 nm) from the InP substrate side. And the thickness of the InAs layer 104 can be changed in the range of 1 nm to 8 nm. However, as the thickness of the InAs layer 104 becomes thinner, I
The ratio of electrons that can be confined in the nAs layer 104 decreases, and as the thickness of the InAs layer 104 exceeds 4 nm, the strain energy increases and it becomes difficult to maintain good crystallinity. The thickness of the layer 104 is preferably greater than or equal to 3 nm and less than or equal to 6 nm. Also, InGa
As graded operation layer 105 can be changed in the range of 1 nm to 6 nm. However, as the thickness of the graded operation layer 105 increases, the distribution of electrons moves away from the gate electrode and hinders the improvement of high-frequency characteristics, so that it is preferably 1 nm or more and 4 nm or less.

The InGaAs active layer 103 (for example, an InAs composition ratio of 0.53 and a film thickness of 13 nm), InGaAs
The s operation layer 106 (for example, an InAs composition ratio of 0.53 and a film thickness of 1 nm) may not be provided. Further, the InAlAs layer buffer 102, the InAlAs spacer layer 107, the InAlAs layer
Also, the InAs composition ratio of each layer of the s carrier supply layer 108 and the InAlAs Schottky layer 109 is not limited to 0.52, and for example, a semiconductor in a range of 0 to 0.6 can be adopted. The material is, for example, GaAs
Mixed crystals such as s, AlAs, InP, and AlSb can also be used.

Further, the doping concentration can be set to a desired concentration. When electrons are used as carriers, n-type dopants other than Si, such as S and Se, can also be used. In a field-effect transistor using holes as carriers, for example, a p-type dopant such as Be or C can be used.

[Second Embodiment] FIG. 2A is a sectional view showing a second embodiment of the present invention, and FIG. 2B is an energy band diagram of the conduction band. The field-effect transistor of this embodiment shown in FIG.
An InAlAs buffer layer 202 (for example, InAs
Composition ratio 0.52, film thickness 200 nm), InGaAs operation layer 203 (for example, InAs composition ratio 0.53, film thickness 9 n)
m), a high InAs composition ratio InGaAs operation layer 204 (for example, InAs composition ratio 0.8, film thickness 4 nm), an InAs operation layer 205 (for example, film thickness 4 nm), and an InAs composition ratio of 1
InGaAs graded operation layer 206 (for example, 2 nm in thickness) continuously changed from
As operation layer 207 (for example, InAs composition ratio 0.53, film thickness 1 nm), InAlAs spacer layer 208 (for example, I
nAs composition ratio 0.52, film thickness 4 nm), InAlAs carrier supply layer 209 (for example, InAs composition ratio 0.52,
Film thickness 20 nm, dopant Si concentration 3 × 10 ¹⁸ c
m ^-3 ), the InAlAs Schottky layer 210 (for example, I
An nAs composition ratio of 0.52 and a film thickness of 20 nm are sequentially grown, and a source electrode 211, a gate electrode 212, and a drain electrode 213 are formed thereon.

The energy band diagram of FIG. 2B shows the change of the conduction band near the InGaAs operation layer of this structure. The horizontal axis represents the thickness of each layer of the structure shown in FIG. The axis indicates conduction band energy. FIG. 2B shows the high I
Conduction of nAs composition ratio InGaAs operation layer 204 (InAs composition ratio 0.8), InAs operation layer 205, and InGaAs graded operation layer 205 (film thickness 2 nm) in which InAs composition ratio is continuously changed from 1 to 0.53 This indicates that electrons can be confined with a significantly higher probability than a layer whose band is lower than the Fermi level and higher than the Fermi level, for example, the InGaAs operation layer 203 made of In _0.53 Ga _0.47 As, and high electron transport characteristics are expected. It can be understood that most of the active electrons can be confined in the active layers 204, 205, and 206 having a high InAs composition ratio.

With such a structure, a layer having a high InAs composition ratio among the operation layers, that is, an InGaAs operation layer 204 (InAs composition ratio 0.8, film thickness 4 nm) / InA
s operation layer 205 (film thickness 4 nm) / graded operation layer 2
06 (InAs composition ratio continuously changes from 1 to 0.53, film thickness 2 nm), more than 80% of the electrons are confined, so the high transport characteristics of the high InAs composition ratio layer are reflected and the high cutoff frequency is high. Thus, it is possible to obtain a field effect transistor having excellent high frequency characteristics exhibiting mutual conductance.

In this embodiment, In _0.53 Ga _0.47 A
On the active layer 203 having the s composition, an In _0.8 Ga _0.2 As active layer (204) having a lattice constant different from that of InP and an InAs active layer 205 are stacked by 4 nm each. Is a graded layer that gradually changes, so that the graded operation layer can be formed as a flat layer having good crystallinity. That is, a layer having a high InAs composition ratio is 8 below the graded operation layer.
Even when the thickness is formed to be nm, it is possible to prevent the crystal growth surface from having irregularities, and to prevent deterioration of characteristics due to scattering of electrons at the hetero interface.

In this embodiment, high InA
The layers having an s composition ratio of InGaAs in order from the InP substrate side are InGaAs operation layers 204 (InAs composition ratio 0.8, film thickness 4 nm) / In
As operation layer 205 (4 nm thick) / InGaAs graded operation layer 206 (InAs composition ratio is 1 to 0.53
The thickness of the InAs operation layer 205 can be changed in the range of 1 nm to 8 nm. However, as the thickness of the InAs operation layer 205 decreases, the proportion of electrons that can be confined in the InAs operation layer 205 decreases, and as the thickness of the InAs operation layer 204 exceeds 4 nm, the strain energy increases. Since it becomes difficult to maintain good crystallinity, I
It is preferable that the thickness of the nAs layer 205 be 3 nm or more and 6 nm or less.

Further, the composition ratio of the high InAs composition ratio InGaAs operation layer 204 can be changed in a range higher than 0.55 and lower than 1. However, when the InAs composition ratio is close to 1, the strain energy of the entire high InAs composition ratio layer increases, and the crystallinity is deteriorated due to dislocation.
The InAs composition ratio of the As operation layer 204 is 0.65 or more.
It is preferably 85 or less. In addition, the InGaAs operation layer 20
4. The thickness of the InGaAs graded operation layer 206 is set to 4 nm and 2 nm, respectively, but the InGaAs operation layer 204 can have any thickness within a critical thickness where dislocation does not occur, and the InGaAs layer 206 has a thickness of 1 nm. From 6nm
Can be changed within the range.

However, as the thickness of the InGaAs active layer 204 is increased, the strain energy of the entire high InAs composition ratio layer is increased and crystallinity is deteriorated due to dislocation. Therefore, the thickness is preferably 2 nm or more and 6 nm or less.
The graded operation layer 206 preferably has a thickness of 1 nm or more and 4 nm or less because the distribution of electrons moves away from the gate electrode as the film thickness increases, preventing improvement in high-frequency characteristics. The InGaAs operation layer 203 (InAs composition ratio 0.53, film thickness 9 nm), the InGaAs operation layer 20
7 (InAs composition ratio 0.53, film thickness 1 nm) may be omitted.

In this embodiment, the InAlAs layer buffer 202, the InAlAs spacer layer 208, the InAlAs layer
Although the InAs composition ratio of each layer of the lAs carrier supply layer 209 and the InAlAs Schottky layer 210 is set to 0.52, an appropriate value can be adopted in the range of about 0 to 0.6. The constituent material is, for example, GaAs
A mixed crystal such as s, AlAs, InP, and AlSb can also be used.

Further, the doping concentration can be set to a desired concentration. When electrons are used as carriers, n-type dopants other than Si, such as S and Se, can also be used. In a field-effect transistor using holes as carriers, for example, a p-type dopant such as Be or C can be used.

[0031]

As described above, the field effect transistor according to the present invention has InGaAs (InAs) in its operation layer.
The composition ratio changes continuously from 1 to 0.53) / InAs
Structure, InGaAs (InAs composition ratio is 1 to 0.
53) / InAs / In _x Ga _1-x A
s (0.55 <x <1).
nAs active layer (or high InA including InAs active layer)
Even if the film thickness of the (s composition ratio operation layer) is increased, the crystallinity of the operation layer on which the crystal is grown can be favorably maintained.
Further, the InAs and InGaAs graded operation layers having high electron transport characteristics (or the InAs, InGaAs graded operation layer and the high InAs
Most of the electrons can be stored in the composition ratio (InGaAs operation layer), a high cutoff frequency and a high transconductance can be realized, and a field effect transistor having excellent high frequency characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a first embodiment of the present invention and an energy band diagram of a conduction band near an operation layer thereof.

FIG. 2 is a sectional view of a second embodiment of the present invention and an energy band diagram of a conduction band near an operation layer thereof.

FIG. 3 is a sectional view of a conventional example.

[Explanation of symbols]

101, 201, 301 InP substrate 102, 202, 302 InAlAs buffer layer 103, 106, 203, 207, 303, 305 I
nGaAs operation layer 104, 205, 304 InAs operation layer 105, 206 InGaAs graded operation layer 107 208, 306 InAlAs spacer layer 108, 209 InAlAs carrier supply layer 109, 210, 308 InAlAs Schottky layer 110, 211, 311 Source electrode 111 , 212, 312 Gate electrode 112, 213, 313 Drain electrode 201, 201, 301 InP substrate 204 High InAs composition ratio InGaAs operation layer 307 n-InAlAs spacer layer 309 n-InAlAs cap layer 310 n-InAlAs cap layer

Claims (5)

(57) [Claims] 1. A field effect transistor having an InAs operation layer and a carrier supply layer formed on an InP substrate, wherein the composition ratio of InAs between the InAs operation layer and the carrier supply layer is from the InAs operation layer to the InAs operation layer. A field effect transistor comprising a graded operation layer gradually decreasing from 1 to 0.53 toward a carrier supply layer. 2. A high In composition ratio of InAs between said InP substrate and said InAs operation layer of not less than 0.55 and less than 1.
2. The field effect transistor according to claim 1, wherein an InGaAs operation layer having an As composition ratio is inserted. 3. The field effect transistor according to claim 1, wherein the thickness of the InAs operation layer is 3 nm or more and 6 nm or less. 4. The graded operation layer has a thickness of 1 nm.
3. The field-effect transistor according to claim 1, wherein the thickness is at least 4 nm. 5. The semiconductor device according to claim 1, wherein said graded operation layer and said carrier supply layer, and said InP substrate and said InAs
Between the operation layer or the high InAs composition ratio of InGaAs active layer, a low I each consisting of In _0.53 Ga _0.47 As
3. The field effect transistor according to claim 1, wherein an InGaAs operation layer having an nAs composition ratio is inserted.