JP2633636B2 - Printer motor driver protection system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a motor driver protection method for protecting a motor driver of a printer used in a bank terminal or the like from destruction due to a malfunction, even if a control CPU is a program mob, the motor driver is not activated. A motor control unit including a space motor, a motor driver for driving the space motor, and a control unit for writing control data to the motor control unit in a predetermined timing sequence with a view to providing an effective malfunction detection unit for preventing damage. CPU
A malfunction detection circuit that detects when the control data is not written at a predetermined timing at which the control data is to be written to the motor control unit as an abnormality in the write timing, wherein the malfunction detection circuit includes: When an abnormality is detected in the control data write timing in the motor control unit, a non-maskable interrupt is issued to the control CPU, and the control CPU stops writing the control data to the motor control unit in response to the non-maskable interrupt. With.

[Industrial applications]

The present invention relates to a motor driver protection method for protecting a motor driver of a printer used for a bank terminal or the like from being damaged by a malfunction.

In general, in a printer using a DC motor as a space motor for controlling head movement, a CPU writes control data of the space motor into a motor control unit in a fixed timing sequence, and drives the space motor by a motor driver. However, when program runaway occurs,
The write timing of the control data changes, and the motor driver is destroyed.

The present invention provides means for promptly stopping the writing when there is an error in writing such control data.

[Conventional technology]

FIG. 4 shows a basic configuration of a conventional printer to which the present invention is applied.

In the figure, reference numeral 10 denotes a printer, and 11 denotes a control CPU for controlling the entire printer.

Reference numeral 12 denotes a memory for storing control programs, control data, print data, and the like.

Reference numeral 13 denotes a print head of a wire dot type or a thermal type.

Reference numeral 14 denotes a print control unit that drives and controls the print head 13 according to a dot pattern based on print data.

Reference numeral 15 denotes a space motor for moving the print head 13, and in this case, a CD motor is used.

Reference numeral 16 denotes a motor control unit that drives and controls the space motor 15.

 17 is a bus.

The control CPU 11 sends control data for driving the space motor 15 in a predetermined timing sequence according to a control program to move the print head 13 to the motor control unit.
Write to 16. The motor control unit 16 drives the internal motor driver according to the control data, and
To work.

The control CPU 11 writes control data to the print control unit 14 at appropriate timing while the print head is moving, and
13 is driven to perform a printing operation.

FIG. 5 shows the internal configuration of the motor control unit 16 in FIG. 4, and FIG. 6 is a timing chart of the drive pulses.

In FIG. 5, reference numeral 18 denotes a control register serving as a port to which the control CPU 11 writes control data via the bus 17.

Reference numeral 19 denotes a drive pulse generating circuit for driving a motor driver described later, which generates a drive pulse having a width of 4 to 10 μs at a cycle of, for example, 20 KHz based on the control data.

20 is a motor driver, and has a bridge circuit configuration to the transistors TR ₁ consisting TR _4.

The motor driver 20 can drive the space motor 15 back and forth using a single power supply of + 24V or + 48V. That is, transistors TR ₁ to TR ₄
Each base is, P ₄ is applied respectively to no driving pulse P ₁ as shown in Figure 6. At this time, TR ₁ and TR ₄ are turned on at the same time, while TR ₂ and TR ₃ are turned off at the same time, and a pulse shown by an arrow in FIG. Flows. At the timing shown in FIG. 6, TR ₁ and TR ₄ are simultaneously turned off, TR ₂ and TR ₃ are simultaneously turned on, and the space motor 15 is supplied with a reverse pulse current as indicated by an arrow in FIG. Flows.

Here, all of the driving pulses P ₁ / P ₄ and P ₂ / P ₃ are at the same time L so that the H level does not overlap between the respective sets.
Times TS ₁ and TS ₂ at which the current level becomes TR ₁ are provided.
To TR ₃ or from TR ₂ to TR ₄ to prevent short-circuit between the power supply and ground, thereby preventing the transistor from being destroyed.

In this way, the space motor 15 can be continuously driven by the motor driver 20.

[Problems to be solved by the invention]

In a conventional printer, when a program runaway occurs in the control CPU, the CPU sometimes writes control data to the motor control unit in a sequence different from a normal timing sequence.

In this case, there is a problem that a certain amount of time is required until the CPU detects program runaway and stops writing control data, so that the motor driver is erroneously driven and the motor driver is destroyed.

An object of the present invention is to provide an effective malfunction detecting means for preventing a motor driver from being destroyed even when a control CPU runs out of control.

[Means for solving the problem]

In the present invention, detection of a program runaway in the CPU is performed in principle by determining the execution of the same loop for a certain number of days or more, or the elapse of a processing time for a certain time or more. Therefore, the motor control unit is provided with a means for detecting the timing error of control data writing, and if a timing error is detected, the CPU is forced to interrupt (NMi) and stop writing control data immediately. It is intended to be.

 FIG. 1 is a diagram showing the basic configuration of the present invention.

 In the figure, reference numeral 10 denotes a printer.

A control CPU 11 controls the operation of the entire printer.

Reference numeral 12 denotes a memory used for storing a control program, control data, print data, and the like.

 13 is a print head.

Reference numeral 14 denotes a print control unit that drives the print head 13 for printing.

Reference numeral 15 denotes a space motor for controlling the movement of the print head 13, and a DC motor is used.

Reference numeral 16 denotes a motor control unit that drives and controls the space motor 15.

 17 is a bus.

Reference numerals 18, 19, and 20 denote a control register, a drive pulse generation circuit, and a motor driver, respectively, which constitute the motor control unit 16.

Reference numeral 21 denotes a malfunction detection circuit added according to the present invention, which detects a case where control data is written to the motor control unit 16 at abnormal timing.

Reference numeral 22 denotes a microphone disable interrupt (NMi) signal, which is output to perform a forced interrupt to the control CPU when the malfunction detection circuit 21 detects an abnormality in writing control data.

(Operation)

The operation based on the principle configuration of the present invention shown in FIG. 1 is as follows.

During the printing operation of the printer 10, the control CPU
The control data for driving the print head and the control data for driving the space motor are written into the motor control unit 16 and the motor control unit 16, respectively, and the print drive and the movement control of the print head 13 are performed.

In the control CPU 11, control data for the space motor 15 is created in a fixed timing sequence, and is written to the control register 18 of the motor control unit 16 via the bus 17.

The control data written in the control register 18 is taken into the drive pulse generation circuit 19, and a drive pulse is generated for the motor driver 20.

The motor driver 20 is switching-controlled by the drive pulse, and drives the space motor 15.

If the control CPU 11 runs out of control, the motor controller 16
An abnormality occurs in the timing of writing control data to the control register 18 of FIG.

The malfunction detection circuit 21 monitors the timing of writing the control data, and when detecting an abnormality in the write timing, outputs a non-maskable interrupt (NMi) signal to the control CPU 11.
Raise to

When there is a non-maskable interrupt, the control CPU 11 immediately performs the interrupt processing after finishing the instruction being executed,
The drive control of the space motor 15 is abnormally terminated, and the writing of control data to the motor control unit 16 is stopped.

In this way, according to the present invention, before the control CPU detects a program runaway, it detects a control data write error and regards this as a runaway, and stops the control data write promptly. Can be prevented from being destroyed.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

FIG. 2 is a circuit diagram of an embodiment of the malfunction detection circuit 21 in FIG. 1, and FIG. 3 is a signal timing diagram thereof.

In FIG. 2, 23 and 24 are counters (CNT) using LS393, 25 is a NOT gate (N) using LS04, 26 is a flip-flop (FF) using LS74, and 27 is an AND gate using LS08 (A), 28 is an OR gate (OR) using LS32, 29 is LS74
Flip-flop (FF) using LS30, NOT using LS06
The gate.

Among the signals in the circuit, C1M is a 1 μs cycle clock, * A804W is a write enable signal, Z01 is + 5V, D7 is a start signal, * RST is a reset signal, and * A817W is a control register.
Control signal write signal to 18 (see Fig. 1), CLR is a clear signal, POMASK is a control data write mask signal, * POMASK is an inverted POMASK signal, NMi is a non-maskable interrupt signal, * NMi is an inverted NMi Represents a signal.

The operation of the malfunction detection circuit of FIG. 2 will be described below with reference to FIGS. 1 and 3 as necessary.

The flip-flop 26 generates a write mask POMASK and an inverted write mask * POMASK (FIG. 3 (a)) that define a write permission period for control data in a normal state.

Inverted write mask * POMASK is a write enable signal *
When the A804W goes high, it goes low and the counter 2
Start 3,24.

Counters 23 and 24 count clock C1M, and 32 μs
Later, an H level output is generated. This output is inverted by the NOT gate 25, and the clear signal CLR (FIG. 3 (b)) is set to L level.

The clear signal CLR is applied to one input of the AND gate 27, and outputs the H level because the reset signal * RST of the other input is at the H level during operation.
Clear This allows * POMASK (Fig. 3 (a))
An L level period (H level in POMASK) with a width of 32 μs is obtained.

Within this * POMASK L level period, the control CPU 11 (first
It is determined that the control data is written normally if the control data is written out of the figure, and that if the control data is written out of the L level period, it is determined to be abnormal and a non-maskable interrupt is raised.

That is, when the control CPU 11 shown in FIG. 1 writes the control data into the control register 18 of the motor control unit 16, the write signal * A817W temporarily becomes L level. The upper part of FIG. 3 (c) occurs at the timing of * A817W in the normal state and within the H level period of POMASK of FIG. 3 (a). However, when an abnormality occurs due to a program runaway, as shown in the lower part of FIG.

The OR gate 28 receives these POMASK and * A817W as inputs and takes the OR logic. Therefore * A817W is H of POMASK
If it is within the level period, * A817W is buried in POMASK, and if it is out of the H level period, * A817W is separated and output.

The flip-flop 29 outputs the separated * A8
It is set to ON only at the rise of 17W, and as shown in FIG. 3 (d), NMi is set to the H level to raise a non-maskable interrupt to the control CPU 11 (FIG. 1). That is, abnormal writing of control data is detected, and the control CPU is caused to perform quick response processing.

〔The invention's effect〕

According to the present invention, even if a program runaway occurs during writing of motor control data in the printer, an error is detected on the hardware and an interrupt process is forcibly executed. Thus, it is possible to respond much more quickly than in the case of the method described above, and it is possible to enhance the destruction prevention performance of the motor driver.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a circuit diagram of an embodiment of a malfunction detecting circuit according to the present invention, FIG. 3 is a signal timing diagram of the malfunction detecting circuit of FIG. 2, and FIG. FIG. 5 is a basic configuration diagram of the printer, FIG. 5 is an internal configuration diagram of a motor control unit, and FIG. 6 is a timing diagram of driving pulses. In FIG. 1, 10: Printer 11: Control CPU 12: Memory 13: Print head 14: Print control unit 15: Space motor 16: Motor control unit 17: Bus 18: Control register 19: Drive pulse generation circuit 20: Motor driver 21: Malfunction detection circuit 22: Non-maskable interrupt signal (NMi)

Claims (1)

(57) [Claims] A control signal is transmitted to a motor controller (16) including a space motor (15), a motor driver (20) for driving the space motor (15), and a motor controller (16) in a predetermined timing sequence. In a printer equipped with a control CPU (11) for writing, a malfunction detection circuit () that detects when control data is not written at a predetermined timing at which control data is to be written to the motor control unit (16) as an abnormal write timing ( The malfunction detection circuit (21) provides an unmaskable interrupt to the control CPU (11) when the motor control unit (16) detects an abnormality in the control data write timing, and the control CPU (11) Responds to the non-maskable interrupt by
A motor driver protection method for a printer, wherein writing of control data to the motor control unit (16) is stopped.