JP2640184B2 - Read-only semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only semiconductor memory device, and more particularly to a read-only semiconductor memory device used for digital signal processing.

[0002]

2. Description of the Related Art One type of semiconductor memory device is a read-only semiconductor memory device (read only memory, hereinafter referred to as a ROM) for storing information such as a certain program or data. Is widely used for various applications.

In a digital signal processing application, the ROM is used as a coefficient holding means or a storage means for performing a table lookup operation. Here, the operation of the table look-up method means that the operation result corresponding to the input is stored in a table in advance, and when the input is given, the operation result corresponding to the input is retrieved from the table and output. It is a method. When a table is stored in the ROM, the input is used as an address, and the operation result is stored corresponding to each address.

In an integrated circuit device dedicated to digital signal processing, a ROM is incorporated in the integrated circuit device. The main reason for using a ROM for such signal processing applications is that one memory cell is formed of one transistor, so that when storing data of the same capacity, another storage device such as an SRAM (static Hardware is smaller than random access memory). That is, ROM is inexpensive and occupies a relatively small area, so that it is often used for such purposes.

FIG. 32 schematically shows a general configuration of a ROM. In FIG. 32, the ROM includes a memory cell array 6 in which memory cells for storing information are arranged in a matrix of rows and columns. In order to select a desired memory cell from the memory cell array 6,
An address buffer 7 and an address decoder 8 are provided. Address buffer 7 receives an externally applied address input and generates an internal address. Address decoder 8 decodes the internal address from address buffer 7 and selects a corresponding memory cell in memory cell array 6.

The address input may include a row address and a column address designating a row and a column of memory cell array 6, respectively, or may include only a row address. In the case of a ROM in which one row of memory cell data is read simultaneously, such as when one row of the memory cell array 6 is formed of one word, a column address is unnecessary. Thus, in this case, the address input contains only the row address. 1
In the case of a ROM having one page and including a plurality of words, it is necessary to read data of a desired memory cell from one row of memory cells. In this case, both a row address and a column address are required. Therefore, depending on the configuration of the ROM, address decoder 8 may include only a row decoder or may include both a row decoder and a column decoder. The ROM shown in FIG. 32 is generally shown to include both of the above cases.

The ROM further receives internal control signals AT, AT ', φp in response to external control signals CE, OE.
And a control signal generating circuit 10 for generating OE and the like; an output circuit 9 activated in response to an internal control signal OE to output data of a selected memory cell to the outside of the ROM as output data; And the like, a bit line in the memory cell array 6 (an internal data transmission line,
This includes a precharge circuit 41 for precharging to a predetermined reference potential of, for example, the power supply potential Vcc level.

The internal control signal AT is supplied to an address buffer 7
At the timing of fetching the address input and generating an internal address. Internal control signal AT 'gives the timing of address decoding in address decoder 8. Output circuit 9 includes an amplifier for amplifying data of a selected memory cell in memory cell array 6 and an output buffer for buffering the output of the amplifier to derive output data. The internal control signal OE defines the timing for activating the output circuit 9.

The precharge circuit 41 has an internal control signal φp
Activated in response to An external control signal CE is a control signal for setting the ROM to an enabled state. The control signal OE is a control signal for giving data output timing of the ROM. Precharge signal φp is normally activated when control signal CE is inactive.

FIG. 33 shows a structure of a memory cell of the ROM shown in FIG. In FIG. 33, the ROM memory cell MC includes one MOS transistor (insulated gate field effect transistor) 1. MOS transistor 1 has its gate connected to word line 2 and its source connected to reference potential line 4 supplying reference potential Vss, which is, for example, the ground potential. MOS transistor 1
Is connected or disconnected to bit line 3 according to the data stored in memory cell MC. In FIG. 33, the connection / disconnection of the region 16 surrounded by the broken circle is set depending on whether or not the wiring is masked in the transistor manufacturing process. At one end of the bit line 3,
In response to precharge signal φp, there is provided a precharge transistor 15 for connecting bit line 3 to a second reference potential Vcc, for example, an operating power supply potential. Next, the operation of the ROM shown in FIGS. 32 and 33 will be described with reference to the operation waveform diagram of FIG.

First, when the control signal CE is at "H" and the ROM
Is in the disabled standby state, precharge signal φp is at “H” level. Therefore, precharge transistor 15 is in the ON state, and bit line 3 is precharged to "H" of power supply potential Vcc level.

When control signal CE falls to "L", R
OM is enabled and a memory cycle begins. In response to the fall of control signal CE, the address applied to address buffer 7 is taken there, and an internal address is generated. The timing at which this internal address is generated is defined by control signal AT. Address decoder 8 also decodes the internal address from address buffer 7 and transmits row select signal WL onto the selected word line. The decode timing in address decoder 8 is defined by internal control signal AT '.
When the row selection signal WL is transmitted to the selected word line and its potential rises to "H", the transistor 1 of the memory cell MC connected to this word line is turned on.

Now, consider the case where the drain of transistor 1 is connected to bit line 3 via region 16 in FIG. In this case, the precharge charge of the bit line 3 is supplied to the reference potential Vss
And the potential of the bit line 3 falls.

On the other hand, if no wiring is formed in the region 16 between the transistor 1 and the bit line 3, there is no charge discharge path between the transistor 1 and the bit line 3. Holds the precharged potential. The potential on the bit line 3 is detected and amplified by an amplifier included in the output circuit 9.

Next, when control signal OE falls to "L", output circuit 9 is activated, and data of the selected memory cell is output as output data D. Here, when the signal OE is "H", the output data D is in a high impedance state. When the output signal OE falls to "L", the output data D is initially invalid and becomes valid data after a lapse of a predetermined time because the value of the output data D at the time when the signal OE falls is selected memory. This is because it is unknown whether the data is cell data.

In the operation waveform diagram shown in FIG. 34, region 16 shown in FIG. 33 is cut off, and memory cell M is turned off when bit line 3 holds the precharge potential.
For example, a case where C holds data “1”, this region 16 is in a connected state, and a case where the potential of the bit line 3 decreases corresponds to a state where data “0” is held. .

When one memory cycle is completed, control signal CE rises to "H". This control signal CE cannot fall to "L" again unless the precharge time Tb has elapsed. This time Tb corresponds to bit line 3
Required for precharging to the power supply potential Vcc level.

[0018]

SUMMARY OF THE INVENTION As described above, ROM
Are widely and generally used for storing data and programs that do not need to be changed because of their simple memory cell structure and their high integration. However, R
Since one memory cell is one transistor in the OM, a number of transistors equal to the storage capacity is required. FIG. 35 shows the configuration of an 8 word × 1 bit ROM.

In FIG. 35, eight word lines 12
e, 12f, 12g, 12h, 12i, 12j, 12k
And 12l at the respective intersections of the bit line 3 and the memory cell transistors 11e, 11f, 11g, 11h, 1
1i, 11j, 11k and 11l are provided.

The memory transistors 11e, 11g, 11
i, 11j has its drain connected to the bit line 3 via the region 16. The memory transistors 11f, 11h,
The drains of 11k and 11l are separated from the bit lines in the wiring region 16. Memory transistor 11e
To 11l are connected to a reference potential (hereinafter simply referred to as ground potential) line 4 which is, for example, a ground potential,
Each gate is connected to a corresponding word line.

Address inputs for designating these memory cells are externally applied, and address decoder 8
(See FIG. 32), and the row select signal WL is transmitted to the corresponding word line. In this case, the word line 12e
Row selection signal WL is transmitted to any of .about.121. Now, word lines 12e to 12l have addresses 1 to 8
Respectively.

In the case of such an 8 word × 1 bit ROM, the relationship between the address input, the potential on the word line, the selected memory cell transistor (transistor in the ON state) and the data read at that time is listed. Thirty-six
Shown in the figure.

For example, when the address input is address 1, word line 12e is selected, its potential rises to "H", and memory cell transistor 11e is turned on. Since the drain of the memory cell transistor 11e is connected to the bit line 3, the potential of the bit line 3 falls to "L" and the data to be read becomes "0". Hereinafter, similarly, the potential of the corresponding word line rises according to the address input, and each memory cell transistor becomes conductive, and the data to be read is determined according to the connection state of the drain.

As described above, an RO of 8 words × 1 bit is used.
In order to form an M memory cell array, one transistor, that is, eight transistors, is required for each memory cell. Generally, N words x M bits of ROM
, N × M transistors are required in the memory cell array. Therefore, as the capacity of the ROM is increased, the number of transistors is increased and the area occupied by the transistors is increased. Further, when the array area is limited, it is difficult to secure a memory cell transistor formation region with a sufficient area, and it is impossible to obtain a highly reliable memory cell transistor.

When such a ROM is used for digital signal processing, the RO is determined according to the processing contents.
A so-called bank configuration for switching M is often adopted.

For example, FIG.
FIG. 3 is a diagram schematically showing a ROM configuration for implementing an up-type operation. In FIG. 37, there are provided a first ROM 31a and a second ROM 31b for storing a set of coefficients corresponding to each operation mode. An operation mode designating signal SA is applied to a selection input SE of each of the ROMs 31a and 31b in order to select one of the first and second ROMs according to the operation mode, that is, the processing content.

The ROM 31a stores the output result a for the input x.
X is stored, while the ROM 31b stores the output b · x for the input x. This input x is stored in the ROM 31
a and 31b are provided as address inputs, respectively. In such a ROM bank configuration, when the operation mode designating signal SA selects the ROM 31a, the input x
, An output z = ax is obtained.

When the operation mode designating signal SA selects the ROM 31b, an output z = b.x for the input x is obtained. As an example of such a bank configuration, for example, one ROM may double the input x and the other ROM may output the result of dividing the input x by 2.

When such a bank configuration is adopted and a bank is switched in accordance with the operation mode, a plurality of ROMs are required. Therefore, when such a ROM is incorporated in an integrated circuit device exclusively for digital signal processing, the occupied area is required. Is increased. In this case, a combination of the input x and the operation mode designating signal SA is used as an address, and it is also possible to configure only one ROM.
Also in this case, the storage capacity of one ROM is equal to the 37th.
The storage capacity for two ROMs shown in the figure is required, and the scale becomes large.

Still further, a typical example of digital signal processing is image processing. In such image processing fields, orthogonal transformation, sampling frequency transformation, and the like are frequently performed. For example, in the discrete Fourier transform, coefficients for performing a Fourier transform, an inverse Fourier transform, a matrix permutation for performing a butterfly operation, and the like are stored in separate ROMs.

FIG. 38 is a diagram schematically showing a configuration of a matrix operation circuit section in such a semiconductor integrated circuit device dedicated to image processing. The configuration of the signal processing integrated circuit device shown in FIG.
It is shown on pages 174 to 175 of February 5, 1990 (No. 492). FIG. 38 shows a part of the circuit configuration of the two-dimensional discrete cosine transform. This device comprises a matrix operation circuit 33 and ROMs 32a and 32 each storing a predetermined set of coefficients.
b, 32c and 32d.

In order to set any one of the ROMs 32a to 32d to the selected state, an externally applied operation mode designating signal SB (2 bits) is applied to each of the ROMs 32a to 32d.
It is provided to a selection input SE of 2d.

The matrix operation circuit 33 performs a conversion process using a predetermined pixel of n rows and m columns (for example, 8 rows and 8 columns) as one unit. That is, when one unit block of the pixel x _ij is given, the matrix operation circuit multiplies the given input x _ij by a coefficient from any of the ROMs 32a to 32d and sequentially accumulates the multiplication results. The output Σa _ij · x _ij is output. Here, a _ij is a coefficient output from the selected ROM.

In the case of the configuration shown in FIG. 38, one coefficient ROM is selected in accordance with the operation mode, and the arithmetic circuit 33 performs an input x _ij and a predetermined arithmetic operation. In this case, the resolution (the number of constituent bits, that is, the data width) of the input x _ij increases, and the operation circuit 3
If the size of the unit block handled by 3 becomes large, each ROM
Increases the number of coefficients to be stored and also increases the data width of the coefficients, thereby increasing the capacity of the ROM. Therefore, even in the case of such a configuration in which each of the ROMs is switched according to the operation mode, a plurality of ROMs are required, and the scale of the ROM unit increases, which is one obstacle to high integration.

Here, in the above document, four coefficients R
The OM is used for storing a ROM for storing coefficients for discrete cosine transform, a ROM for storing coefficients for performing inverse cosine transform, and storing a coefficient for performing matrix permutation for performing butterfly operation. RO to do
This is to support ROM for storing M and a coefficient for functioning as a filter in a loop (low-pass filter) for reducing block distortion generated at the time of encoding by the discrete cosine transform. When functioning as a filter in the loop, the matrix operation circuit 33 functions as one digital filter.

As shown in FIG. 39, the ROM
It is often used as a program ROM for storing a predetermined program. The program ROM 35 usually stores a microcoded program, and has an advantage that the CPU 36 can execute a predetermined processing program at a high speed without accessing an external storage device. . In the control field and the like, when such a CPU 36 and the program ROM 35 are used as control circuits, they are often used as one-chip microcomputers. As a result, the scale of the program ROM 35 becomes large, and it becomes impossible to form such a control circuit compactly with one chip.

In a control system, consider a control device that determines that the system is normal only when both the state variable at the point A and the state variable B at the point B satisfy predetermined conditions. Now, suppose that an input x represents a certain state variable at point A, and an input y represents a certain state variable at point B. The control system uses these inputs x and y
Is multiplied by the same coefficient a, and the obtained results ax and ay are compared with predetermined reference values p and q, respectively, to determine whether the controlled system is normal or abnormal. FIG. 40 shows an example of such a configuration.

In FIG. 40, a first ROM 41 stores a multiplication result ax of an input x and a coefficient a in a table format, and a second ROM 42 stores a multiplication result a of an input y and a coefficient a.
y is stored in a table format. The subtractor 43 outputs the first RO
The multiplication result output ax from M is subtracted from a predetermined reference value p, and the second subtractor 44 subtracts the multiplication result output ay from the second ROM 42 and the predetermined reference value q. The subtractor 45 receives the outputs of the subtracters 43 and 44 and generates a signal indicating that the controlled system is normal only when the outputs of both the subtracters 43 and 44 are smaller than a predetermined value. One example of such a system is where the inputs x and y are the detected outputs from a thermocouple and the coefficient "a" is a voltage / temperature conversion coefficient that converts the detected output of the thermocouple to temperature. Conceivable.

The arithmetic circuit 45 determines that the output ax-p from the first subtractor 43 is equal to or less than a first predetermined value (permissible error) and the output ay-q of the second subtractor 44 is a second predetermined value. A normal indication signal is generated only when the value is equal to or less than the value.

In this case, since the input x and the input y must be processed simultaneously, two ROMs, that is, the first R
An OM 41 and a second ROM 42 are required. The first and second ROMs 41 and 42 store the same coefficient. Although the first and second ROMs 41 and 42 have the same storage contents, the inputs x and y
Are different and cannot be given to one ROM at the same time. Therefore, as the configuration of the control system, it is necessary to use the two ROMs, so that a compact structure cannot be achieved and the occupied area increases.

In the ROM, data "1" and "0" are read by discharging bit lines during data reading. In this case, since one word is composed of a plurality of bits, electric charges are discharged in a plurality of bit lines. This discharge charge flows to the ground potential. For this reason, the discharge charge causes an increase in the ground potential and the like, which may make it impossible to read data accurately.

It is therefore an object of the present invention to eliminate the above-mentioned disadvantages of the conventional ROM and to provide a ROM capable of greatly increasing the storage capacity with the same occupied area.

Another object of the present invention is to provide a ROM which realizes a larger storage capacity with a smaller number of memory transistors.

Still another object of the present invention is to provide a ROM in which one memory cell can express a plurality of different word bits.

Still another object of the present invention is to provide a ROM that can reliably read data even in a ROM in which one word is composed of a plurality of bits.

[0046]

According to a first aspect of the present invention, there is provided a read-only semiconductor memory device comprising: a bit line for transmitting at least one internal data; a word line for transmitting a row selection signal; Each includes a memory cell for storing information, which is provided at an intersection of a bit line and a word line.

The read-only semiconductor memory device according to the first aspect of the present invention further comprises a plurality of reference potential transmission lines to each of which a reference potential is transmitted, and each of the reference potential transmission lines in response to a potential instruction signal from the outside. Potential setting means for setting a potential.

The plurality of reference potential transmission lines are arranged so as to be commonly connectable to a plurality of memory cells. Each of the memory cells has a memory transistor which is selectively connected to or disconnected from any of the plurality of reference potential transmission lines and stores data. When the memory transistor activates a row selection signal on a corresponding word line, the memory cell electrically connects the bit line to one of the plurality of reference potential transmission lines or all of the plurality of reference potential transmission lines. And the bit lines are electrically separated,
The stored data is read.

According to a second aspect of the present invention, there is provided a read-only semiconductor memory device in which a plurality of reference potential transmission lines and bit lines are arranged in parallel.

[0050]

The read-only semiconductor memory device according to the first aspect of the present invention has a plurality of reference potential transmission lines whose potentials can be changed in response to an external signal. The transistor of the memory cell stores information by a connection mode between the bit line when the word line is selected and the plurality of reference potential transmission lines.

By changing the potentials of the plurality of reference potential transmitting lines in response to an external potential designating signal, the information transmitted from the memory cell transistor to the bit line when the word line is selected can be made variable. . Therefore, even when the same memory cell is selected, a plurality of different word bits can be expressed, and a read-only semiconductor memory device in which one memory cell corresponds to a plurality of addresses can be obtained.

In the read-only semiconductor memory device according to the second aspect of the present invention, since the reference potential transmission line and the bit line are arranged in parallel, one reference potential transmission line is connected via one memory cell. Only charge / discharge of the bit line charge is performed. Therefore, even when the bit line is discharged, the amount of charge flowing to the ground potential is very small, so that the potential of the ground potential line can be prevented from rising, and data can be reliably read.

[0053]

FIG. 2 is a diagram schematically showing the entire configuration of a ROM according to an embodiment of the present invention. In FIG.
The ROM 100 generates a predetermined set of reference potentials in response to an externally applied potential instruction signal S in addition to the configuration of the conventional ROM shown in FIG. A reference potential generating circuit 50 for transmitting the potential to a potential transmission line (not shown in FIG. 2) is provided. Here, in the ROM shown in FIG. 2, portions corresponding to those of the conventional ROM are denoted by the same reference numerals.

The potential instruction signal S may be any of an operation mode instruction signal, a bank selection signal, an address signal, and the like.

FIG. 1 shows a ROM according to an embodiment of the present invention.
3 is a diagram showing an example of the structure of the memory cell of FIG. In FIG. 1, a memory cell MC has one MOS transistor 1
And reference potential transmitting lines 5a and 5b to each of which a reference potential is transmitted. A reference potential of a combination determined in response to a potential means signal S from the outside is transmitted to reference potential transmission lines 5a and 5b from reference potential generating circuit 50 shown in FIG.

Memory cell transistor 1 has a drain connected to bit line 3, a gate connected to word line 2, and a source connected to reference potential transmission lines 5a and 5b.
And is connected or disconnected to one of the ground lines 4. The storage information of the memory cell MC is set according to the connection state between the source of the memory cell transistor 1 and a reference potential transmission line (hereinafter, referred to as a reference potential transmission line including the ground line 4). The following two cases can be considered as combinations of reference potentials applied to reference potential transmission lines 5a and 5b.

Case 1: "H" potential is transmitted to the first reference potential transmission line 5a, and "L" potential is transmitted to the second reference potential transmission line 5b.

Case 2: The "L" potential is transmitted to the first reference potential transmission line 5a, and the "H" potential is transmitted to the second reference potential transmission line 5b.

FIG. 3 is a table showing the relationship between the connection state of the source of the memory transistor and the storage information at that time in each of Case 1 and Case 2.

Next, a data read operation of the ROM according to one embodiment of the present invention will be described with reference to FIGS. The storage information of the memory cell MC is determined by the connection relationship between the source terminal of the memory cell transistor 1 and the reference potential transmission line. First, the case 1 will be described.

First, bit line 3 is precharged to "H" of power supply potential Vcc in the same manner as in the prior art. After completion of the precharge, the word line 2 is selected by an address input, a row selection signal WL is transmitted onto the selected word line 2, and the potential of the word line 2 rises to "H".

Now, the potential of the first reference potential transmission line 5a is set to "H", and the potential of the second reference potential transmission line 5b is set to "L". When memory cell transistor 1 is rendered conductive in response to the potential on selected word line 2, bit line 3 is connected when its source terminal is connected to ground line 4 or second reference potential transmission line 5b. Is discharged through the memory cell transistor 1, the potential of the bit line 3 decreases, and data "0" is read.

If the source terminal of memory cell transistor 1 is connected to first reference potential transmission line 5a or is in an open state (non-connection state), the charge precharged to bit line 3 is discharged. Instead, bit line 3 maintains the precharge potential, whereby data "1" is read.

Next, the case 2 will be described. In this case, the potential of the first reference potential transmission line 5a is "L", and the potential of the second reference potential transmission line 5b is "H". After the completion of precharging of the bit line 3, the potential of the word line 2 is set to "H".
To turn on the memory cell transistor 1. When the source terminal of the memory cell transistor 1 is connected to the ground line 4 or the first reference potential transmission line 5a,
The precharged charge of bit line 3 is discharged, and data "0" is read.

When the source terminal of memory cell transistor 1 is connected to second reference potential transmission line 5b or is in an open state, the precharge potential of bit line 3 does not change, and data "1" is output. Is read.

As described above, by switching the reference potential of reference potential transmission lines 5a and 5b, two types of data can be stored by one memory cell.

FIG. 4 is a diagram showing a configuration example of a memory cell array of an 8 word × 1 bit ROM using the memory cell structure shown in FIG. In FIG. 4, four word lines 12a, 12b, 12c and 12d and a bit line 3
At the intersection with the memory cell transistors 11a, 11b, 1
1c and 11d are provided respectively.

A first reference potential transmission line 5a, a second reference potential transmission line 5b and a ground line 4 are provided in parallel with bit line 3.

Memory cell transistor 11a has its source connected to ground line 4 and its gate connected to word line 12a.
And its drain is connected to the bit line 3.
Memory cell transistor 11b has its source connected to first reference potential transmission line 5a and its gate connected to word line 1
2b, and its drain is connected to the bit line 3. The source of the memory cell transistor 11c is the second
, Its gate is connected to word line 12 c, and its drain is connected to bit line 3. The source of the memory cell transistor 11d is opened (disconnected state), the gate is connected to the word line 12d, and the drain is connected to the bit line 3.

By switching the potential of reference potential transmission lines 5a and 5b, one memory cell can store information of two addresses. That is, a configuration in which one word line corresponds to two different addresses is obtained.

FIG. 5 is a diagram showing a list of operations of the ROM shown in FIG. As shown in FIG. 5, in case A in which the potentials of reference potential transmission lines 5a and 5b are set to "H" and "L", respectively, memory cell transistors 11a to 11a correspond to addresses 1 to 4, respectively.
d is selected, and data “0”, “1”, “0” and “1” are read.

In case B in which the potentials of reference potential transmission lines 5a and 5b are switched to "L" and "H", respectively, memory cell transistors 11a to 11d correspond to addresses 5 to 8, respectively. Selected,
Data "0", "0", "1" and "1" are read.

That is, the word line 1
2a corresponds to addresses 1 and 5, word line 12b corresponds to addresses 2 and 6, word line 12c corresponds to addresses 3 and 7, and word line 12d corresponds to addresses 4 and 8.

As described above, even if the connection destination of the source terminal of the memory cell transistor is fixed, by switching the potentials of reference potential transmission lines 5a and 5b,
One word line can correspond to a plurality of addresses. Therefore, even if the ROMs have the same capacity, the number of memory cell transistors can be significantly reduced. For example, when comparing the conventional 8-word × 1-bit ROM shown in FIG. 35 with the ROM memory cell array shown in FIG. 4, the number of memory cell transistors in the configuration shown in FIG. You can see that it is halved compared to the example.

FIG. 6 is a diagram showing a memory array arrangement when a ROM of 8 words × 4 bits is constructed using the memory cell structure shown in FIG. In FIG. 6, four word lines 12a, 12b, 12c, and 12d are arranged so as to intersect with four bit lines 3a, 3b, 3c, and 3d. A set of reference potential transmission lines 4, 5a and 5b is provided for each of bit lines 3a to 3d. Reference potential transmission lines 4, 5a and 5b are bit lines 3a
To 3d. Reference potential transmission lines 5a and 5b are connected to main reference lines RP1 and RP2, respectively. Main reference lines RP1 and RP2 are arranged in parallel with word lines 12a to 12d. A reference potential is transmitted from reference potential generating circuit 50 to main reference lines RP1 and RP2.

The word lines 12a to 12d and the bit line 3
Memory transistors 11a to 11d are arranged at respective intersections with a. Each gate of the memory transistors 11a to 11d is connected to a corresponding word line 12a to 12d.
d. The source terminal of the memory transistor 11a is connected to the ground line 4. The source terminal of memory transistor 11b is connected to reference potential transmission line 5a. The source terminal of memory transistor 11c is connected to reference potential transmission line 5b. The source terminal of the memory transistor 12d is open, and is not connected to any reference potential transmission line.

The word lines 12a to 12d and the bit line 3
b, the memory transistors 11e, 11f, 1
1g and 11h are arranged. Memory transistor 1
Source terminals 1e, 11f and 11g are connected to reference potential transmission lines 5a, 5b and 4, respectively. The source terminal of the memory transistor 11h is set to an open state. Memory transistors 11i, 11j, and 11k are provided at respective intersections of word lines 12a to 12d and bit line 3c.
And 111 are arranged. Memory transistor 11i
Are set to the open state. Source terminals of memory transistors 11j, 11k and 11l are connected to reference potential transmission lines 4, 5b and 5a, respectively.
The gates of the memory transistors 11i to 11l are connected to corresponding word lines 12a to 12d, respectively.

The memory transistors 11m, 11n, 11
o and 11p are arranged at respective intersections of the word lines 12a to 12d and the bit line 3d. Memory transistor 1
Gates 1m to 11p are connected to corresponding word lines 12a to 12d. Source terminals of memory transistors 11m and 11n are both connected to reference potential transmission line 5b. Each source of memory transistors 11o and 11p is connected to reference potential transmission line 5a.

Precharge transistors 15a to 15d are provided for bit lines 3a to 3d, respectively. Precharge transistors 15a to 15d precharge the bit line to the Vcc level ("H" level) in response to precharge signal φp.

In the array arrangement shown in FIG. 6, by switching the potentials of main reference lines RP1 and RP2, data of two different addresses can be stored in one memory cell. That is, FIG.
As in the case of the array arrangement shown in FIG.
(One word line 12a to 12d is generically shown)
Correspond to the two addresses.

FIG. 7 is a diagram showing a list of operations of the RAM shown in FIG. Hereinafter, the operation will be briefly described with reference to FIGS. 6 and 7.

Now, consider the case where reference potential transmission lines 5a and 5b are set to "H" (Vcc level) and "L" (ground potential level), respectively.

When address 1 is specified, word line 1
2a is selected. Memory transistors 11a, 11e, 11i, and 11 connected to word line 12a
m is turned on. Thereby, data "0", "1", "1", and "0" stored in memory transistors 11a, 11e, 11i, and 11m are transmitted onto corresponding bit lines 3a, 3b, 3c, and 3d. .

When address 2 is designated, word line 1
2b is selected, and the memory transistors 11b, 11f,
11i and 11n are turned on. In this case, data "1", "0", "0" and "0" are transmitted on bit lines 3a, 3b, 3c and 3d, respectively.

When address 3 is designated, word line 12c is selected and memory transistors 11c and 11c are selected.
g, 11k and 11o store data “0”, “0”, “0” and “1”, respectively, in each bit line 3
a, 3b, 3c and 3d.

In the case of address 4, word line 12d is transmitted. Memory transistors 11d, 11h, 11
1 and 11b are turned on, and data "1",
"1", "1" and "1" are transmitted onto each of bit lines 3a to 3d.

Next, consider a case B in which the "L" and "H" potentials are transmitted from reference potential generating circuit 50 to main reference lines RP1 and RP2.

For addresses 5, 6, 7, and 8,
Word lines 12a, 12b, 12c and 12d respectively
Is selected. In each case, "0,0,
"1,1", "0,1,0,1", "1,0,1,0" and "1,1,0,0" are transmitted on bit lines 3a to 3d for each address. .

Therefore, each word line is selected by two different addresses. For example, word line 1
2a is selected when addresses 1 and 5 are specified. By using the configuration shown in FIG. 6, an array arrangement of 8 words × 4 bits can be realized using 4 × 4 memory transistors 11a to 11p.

FIG. 8 shows another array arrangement equivalent in electrical connection to the memory array arrangement shown in FIG. That is, FIG.
In the memory array arrangement shown in FIG.
A set of reference potential transmission lines 4, 5a and 5b is provided for each bit line.

In the configuration shown in FIG. 8, a set of reference potential transmission lines 4, 5a and 5b is shared by memory transistors connected to two adjacent bit lines. That is, the memory transistor 11 coupled to the bit line 3a
Memory transistors 11e, 11f, 11g and 11h connected to a, 11b, 11c and 11d and bit line 3b share a set of reference potential transmission lines 4, 5a and 5b.

Memory transistors 11i to 11l coupled to bit line 3c and memory transistors 11m to 11p coupled to bit line 3d are coupled to another set of reference potential transmission lines 4, 5a and 5b.

In the array arrangement shown in FIG. 8, data similar to that shown in FIG. 6 is read. Therefore, this operation is the same as that shown in FIG. 6, and will not be repeated.

According to the arrangement shown in FIG. 8, one set of reference potential transmission lines 4, 5a and 5b is provided between two adjacent bit lines. Therefore, the wiring area required for the reference potential transmission line can be significantly reduced, and the memory cell array area can be reduced.

In the array arrangement shown in FIG. 8, a part of one set of reference potential transmission lines 4, 5a and 5b,
For example, a configuration may be used in which only ground line 4 is shared between memory cells coupled to adjacent bit lines.

Further, the set of reference potential transmission lines 4, 5
A configuration in which a and 5b are shared by memory cells coupled to three or more bit lines may be used.

FIG. 9 shows the reference potential generating circuit 5 shown in FIG.
FIG. 3 is a diagram showing an example of a specific configuration of 0. In FIG. 9, reference potential generating circuit 50 includes two cascaded inverters IV1 and IV2. Inverter IV1
Receives the potential instruction signal S. The output of inverter IV1 is transmitted to reference potential transmission line 5b. Inverter IV2 receives the output of inverter IV1. The output of inverter IV2 is transmitted to reference potential transmission line 5a. In the configuration shown in FIG. 9, the potentials of reference potential transmission lines 5a and 5b can be set according to "H" and "L" of potential instruction signal S.

In the configuration of the memory cell shown in FIG. 1, there is shown a case where three reference potential transmission lines are provided. However, instead of this configuration, four reference potential transmission lines may be provided, and the source terminal of the memory cell transistor may be connected to any one of the four reference potential transmission lines.

FIG. 10 shows another embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of a structure of an OM memory cell. This first
In FIG. 0, in addition to three reference potential transmission lines 4, 5a and 5b, a fourth reference potential transmission line (power supply line) for transmitting, for example, reference potential Vcc which is an operation power supply voltage.
20 are added.

The storage data of this memory cell is set according to which of the reference potential transmission lines 4, 5a, 5b and 20 the source terminal of memory cell transistor 1 is connected to. In this case, the source terminal of the memory cell transistor 1 is always connected to these four reference potential transmission lines 4, 5a,
5b and 20 are connected. An “L” potential is always transmitted to ground line 4, and an “H” potential is always transmitted to power supply line 20. The potentials of first and second reference potential transmission lines 5a and 5b attain either "H" or "L" in response to potential instruction signal S.

The operation of the memory cell shown in FIG. 10 will be briefly described. Now, memory cell transistor 1
Is connected to the power supply line 20. In this case, regardless of the potentials of reference potential transmission lines 5a and 5b, when memory cell transistor 1 is in the selected state, the potential of bit line 3 does not change and the precharge potential is maintained at "H". Data “1” is read from cell transistor 1. The source terminal of the memory cell transistor 1 is connected to the other reference potential transmission lines 4 and 5
a and 5b, the first
Operations similar to those of the memory cell structure shown in FIG. The operation of the memory cell shown in FIG.
Shown in the figure.

As is apparent from a comparison between FIGS. 11 and 3, it can be seen that the memory cell structure shown in FIG. 1 and the memory cell structure shown in FIG. 10 perform the same operation. Can be

In the memory cell structure shown in FIG. 11, bit line 3 can be charged and discharged in any connection state, so that data can be read without precharging bit line 3. RO that can be
M can be obtained. Therefore, it is not necessary to provide the precharge circuit 41, and it is not necessary to consider the time Tb (see FIG. 34) required for the bit line precharge, and it is possible to obtain a ROM that operates at high speed with a small area. it can.

Further, in the ROM memory cell configuration shown in FIG. 10, bit line 3 is not precharged to power supply potential Vcc, and as shown in FIG.
Even when precharging bit line 3 to precharge to the intermediate potential of bit line 2, the bit line is charged or discharged during data reading from the intermediate potential to "H" or "L". The time required for discharging can be reduced as compared with the conventional device, and the current consumption flowing at that time can also be reduced, so that a ROM with high speed and low current consumption can be obtained.

In FIG. 12, Vcc / 2 generating circuit 5
00 is provided for precharging each bit line to the potential level of Vcc / 2. This Vcc / 2 generation circuit 5
00 is provided in common for each bit line 3. DRAM
In the field of (dynamic random access memory), such a Vcc / 2 generating circuit is known, and is widely used for precharging each bit line pair to a potential level of Vcc / 2. Therefore, such a Vcc / 2 generating circuit can be used.

In the above embodiment, four states can be expressed in a one-transistor type memory cell using three or four reference potential transmission lines. In this configuration, one memory cell corresponds to the conventional memory cell 2
It fulfills the function of the individual. Therefore, two banks can be realized using one ROM, and a conventional ROM can be realized using the same number of memory cell transistors.
ROM having a capacity twice as large as that of the ROM can be realized.

This configuration can be further extended to a configuration in which one memory cell realizes the function of the conventional N memory cells. In order for one memory cell to represent the states of N memory cells, each state can take two states of "0" and "1", and therefore, a total of ^2N states must be represented. . Therefore, 2 ^N −1 reference potential transmission lines may be provided as reference potential transmission lines including the ground line, or 2 ^N reference potential transmission lines may be provided as the reference potential transmission lines including both the power supply line and the ground line.

FIG. 13 is a diagram showing a list of data that can be stored in one memory cell when three banks A, B and C are realized using this one ROM. As shown in FIG. 13, banks A, B and C
When there are three, there are eight (2 ³ ) types of data represented by one memory cell. Therefore, in this case, as shown in FIG.
5a, 55b, 56a, 56b, 57a, 57b and 58 are provided. The data stored in the memory cell is determined by the connection state of the source of the memory transistor 1. In the case of the memory cell structure shown in FIG. 14, two reference potential transmission lines are controlled in pairs.

Reference potential transmission lines 55a and 55b are used to represent bank A, and reference potential transmission lines 56a
And 56b are used to represent bank B, and reference potential transmission lines 57a and 57b are used to represent bank C.

In this case, the potential of each reference potential transmission signal line pair corresponding to each of banks A, B and C is set to a state opposite to the signal potential of the reference potential transmission line pair representing another bank. FIG. 15 shows a list of operations of the memory cell structure shown in FIG. As shown in FIG. 11, only the potential of the reference potential transmission line pair corresponding to the selected bank is reversed from the pair of reference potential transmission lines corresponding to the remaining banks. For example, when bank A is designated, the potentials of reference potential transmission lines 55a and 55b are set to "L" and "H", respectively, and the remaining reference potential transmission lines 56a, 56b,
57a and 57b are "H", "L", "H", respectively.
And "L". As is clear from the table shown in FIG. 15, a memory cell storing data corresponding to three banks A, B and C is obtained by the memory cell structure shown in FIG.

Reference potential generation circuit 50 for expressing data of three banks individually in one memory cell
FIG. 16 shows an example of a specific configuration of the above.

In FIG. 16, reference potential generating circuit 50
Are the gate circuits G1, G2 and G3 and the inverter I
V11, IV12 and IV13. Banks A and B
In order to set one of C and C, 2-bit bank selection signals S0 and S1 are used as a potential designation signal.

Gate circuit G1 receives signals S0 and S1. Inverter IV11 receives the output of gate circuit G1. The output of gate circuit G1 is transmitted to reference potential transmission line 55a, and the output of inverter IV11 is transmitted to reference potential transmission line 55a.
b. Gate circuit G1 receives signals S0 and S1.
Output "L" signal when both are "H".

Gate circuit G2 receives signal S0 at its true input, and receives signal S1 at its false input. Inverter IV
12 receives the output of the gate circuit G2. The output of gate circuit G2 is transmitted onto reference potential transmission line 56a, and the output of inverter IV12 is transmitted to reference potential transmission line 56b.
The gate circuit G2 outputs the signal S0 at "H" and the signal S1.
Output a signal of "L" when is "L".

Gate circuit G3 receives signal S0 at its false input, and receives signal S1 at its true input. Inverter IV
13 receives the output of the gate circuit G3. Gate circuit G3
Is transmitted onto reference potential transmission line 57a, and the output of inverter IV13 is transmitted onto reference potential transmission line 57b. Gate circuit G3 outputs an "L" signal when signal S0 is "L" and signal S1 is "H".

The reference potential generating circuit 50 shown in FIG.
Is essentially a decoder, and its decoding operation is
The list is shown in the figure. As shown in FIG.
If both 0 and S1 are "1", bank A is designated,
If "1" or "0", bank B is specified, and if "0" or "1", bank C is specified. In FIG. 17, data "1" and "0" are set to potential "H",
By associating with "L", the selected bank can be designated by the signals S1 and S0. In the combination of signals S1 and S0 shown in FIG. 17, when both are "0", the outputs of gate circuits G1 to G3 all become "H". In this case, there is no corresponding bank,
It is used in the unused state or used for setting the standby state.

In FIGS. 13 to 17, the bank selection signal is used as the potential designation signal. Instead of the bank selection signal, for example, as shown in FIG. 37 and FIG. Alternatively, ROM selection signals SA and SB for switching the ROM in response may be used. Further, in a program ROM as shown in FIG. 39, this ROM stores a program in a normal operation and a test program in an interrupt processing or a test operation, for example, and switches the program according to the operation mode. The operation mode instruction signal may be used as potential setting signal S (S0, S1).

Further, in the above embodiment, one RO
A configuration in which a plurality of ROMs are represented by M is shown. However, the configuration shown in FIG. 18 can be realized instead.

In FIG. 18, memory cell array 60
a has addresses 0 through m, and each address is 1
Let us consider a case where the word line corresponds to one word line. in this case,
It is assumed that addresses 0 to n-1 correspond to an address whose most significant address bit XM is "0", and addresses nm to m correspond to an address whose most significant address bit XM is "1". In this case, if the most significant address bit XM is applied as a potential designating signal to reference potential generating circuit 50, the number of word lines of memory cell array 60b can be reduced by half, as shown in FIG. 18 (b). Increasing the number of address bits XM can further reduce the number of memory transistors in the memory cell array. If the least significant bit is used instead of using the most significant address bit XM, a configuration in which the reference potential is switched between an even address and an odd address can also be obtained.

The open state of the memory cell transistor may be realized by cutting the region 16 into a disconnected state (no wiring).
The structure of the memory cell transistor 1 is arbitrary.

In the structure of the above-described embodiment, reference potential transmission lines 4, 5a and 5b are provided in parallel with bit line 3. Hereinafter, a technical effect obtained by arranging such a reference potential transmission line and a bit line in parallel will be described.

FIG. 19 is a diagram schematically showing a layout of a memory cell of a conventional ROM, and FIG. 20 is a diagram showing a cross-sectional structure along a line AA 'in FIG. In this conventional ROM cell structure, there is shown a configuration in which only one address is assigned to one word line.

Referring to FIG. 19, word lines 2g and 2h
Are provided in parallel with the impurity diffusion region 4. This impurity diffusion region 4 becomes a common source region commonly connecting the respective source regions of the memory transistors connected to word lines 2g and 2h. Bit lines 3i and 3j are arranged in a direction crossing word lines 2g and 2h and impurity diffusion region 4.

A channel region of a memory transistor is formed below word lines 2g and 2h. The channel region may be formed of an impurity diffusion region as long as a condition that a channel is formed when a potential “H” is transmitted to the corresponding word line is satisfied. Impurity diffusion region 3a
i is connected to bit line 3i via contact hole 300i. Bit line 3i is formed of a metal wiring layer. Impurity diffusion region 3bj is connected to another bit line 3j via contact hole 300j. Impurity diffusion regions 3ai, 3bi, 3aj and 3bj provide a drain region of each memory transistor.

Referring to FIG. 20, the memory transistor includes an impurity diffusion region 3ai connected to bit line 3i through contact hole 300i, word line 2h as a gate electrode, and impurity diffusion region 4 as a source region. Including. Another memory transistor includes impurity diffusion region 4 as a source, word 2j as a gate, and impurity diffusion region 3bi as a drain region. This impurity diffusion region 3bi is not connected to bit line 3i. The ground potential is transmitted to impurity diffusion region 4.

In operation, when word line 2h is selected, a channel is formed in each memory transistor connected to word line 2h.

The charge precharged to bit line 3i is discharged to impurity diffusion region 4 through contact hole 300i and the channel, while the charge precharged to bit line 3j is not discharged to the impurity diffusion region. This is because the impurity diffusion region 3aj is not provided with a contact hole for establishing connection with a bit line.

The following problems occur when the above arrangement is used. A plurality of memory transistors are connected to one word line as shown in FIG. FIG. 21 shows a case where eight memory transistors M1 to M8 are connected to one word line WL. The connection between each memory transistor M1 to M8 and the corresponding bit line BL1 to BL8)
To M8 to be determined by the stored data.

The impurity diffusion region 4 forms a ground line GNDL and has a relatively large resistance. Therefore, the resistance r is distributed on the ground line GNDL. In the configuration shown in FIG. 21, when word line WL is selected and data reading is performed, the charge precharged to the bit line connected to the memory cell storing data "0" passes through these memory cell transistors. Ground line GN
Discharged to DL. As a result, a large amount of current transiently flows to the ground potential via the ground line GNDL, so that a change in the ground potential occurs as shown in FIG.

The change in the ground potential can be considered as noise, and is a great obstacle to stable and reliable operation of the ROM. In particular, during the high-speed operation of the ROM, the influence of this change in the ground potential becomes remarkable, causing an increase in access time and a decrease in operation margin. That is, when data on the bit line is read during the noise generation period (see FIG. 22), since noise is present on the ground potential, erroneous reading of data due to the noise occurs and the influence of the noise is prevented. Therefore, it is necessary to delay the data read timing, which causes a problem such as an increase in access time.

In addition, the resistance r is distributed on the ground potential line GNDL, and a different source potential is applied to each of the memory transistors M1 to M8 (see FIG. 23). Therefore, when the source potential of each memory transistor is different as shown in FIG. 23, the potential on the bit line is also affected by the rise of the source potential.
There arises a problem that accurate data reading cannot be performed.

Therefore, when the memory cell array arrangement shown in FIG. 19 is applied to the present invention, accurate data cannot be read, and the layout shown in FIG. 19 cannot be used.

FIG. 24 shows a ROM according to an embodiment of the present invention.
FIG. 3 is a diagram schematically showing a cell layout. In FIG. 24, active regions 100a and 100b each include two memory transistors. Active regions 100a and 100b are separated from each other by a cell isolation region.

Active regions 100a and 100b include impurity diffusion regions 400a, 400b and 400c, respectively. Channel regions are formed below word lines 2a and 2b in active regions 100a and 100b, respectively.

Bit lines 3a and 3b are arranged in a direction crossing word lines 2a and 2b. Reference potential transmission line 4
a, 5a, 5b and 4b are arranged in parallel with bit lines 3a and 3b. Each of reference potential transmission lines 4a, 5a, 5b and 4b is formed of a low-resistance metal wiring layer such as aluminum.

In active region 100a, impurity diffusion region 400a is connected to reference potential transmission line 5a through contact hole 3a.
00a. Impurity diffusion region 500c is connected to ground line 4a via contact hole 300c.

In active region 100b, impurity diffusion region 400a is connected to reference potential transmission line 5b through contact hole 300e, and impurity diffusion region 400c is not connected to any reference potential transmission line.

FIG. 25 is a diagram showing a cross-sectional structure along line BB 'shown in FIG. 24, and FIG. 26 is a diagram showing a cell arrangement electrically equivalent to the layout of FIG.

Referring to FIGS. 25 and 26, memory transistor M1 has a diffusion region 40 serving as a drain region connected to bit line 3a via contact hole 300b.
0b and the contact hole 300 to the reference potential transmission line 5a.
The semiconductor device includes an impurity diffusion region 400a serving as a source region connected through a, and a word line 2a serving as a gate.

The memory transistor M2 has an impurity diffusion region 400b as a drain and a contact hole 300
An impurity diffusion region 400c serving as a source connected to a reference potential transmission line (ground line) 4 via c, and a word line 2b serving as a gate are included.

Memory transistor M3 has impurity diffusion region 400a serving as a source connected to reference potential transmission line 5b through contact hole 300e, and impurity diffusion region serving as a drain connected to bit line 3b through contact hole 300d. A region 400b and a word line 2a as a gate are provided.

Memory transistor M4 has impurity diffusion region 400b serving as a drain connected to bit line 3b through contact hole 300d, word line 2b serving as a gate, and impurity diffusion region 400c serving as a source in a floating state. including.

In the arrangement shown in FIGS. 24 to 26, memory transistors M1 and M3 store data determined by voltages transmitted on reference potential transmitting lines 5a and 5b. The memory transistor M2 stores data “0”, and the memory transistor M4 stores data “1”.

The data read operation in the arrangement shown in FIGS. 24 to 26 is the same as the arrangement shown in FIG. 6 and the like, and the data read operation is omitted. FIG.
In the arrangement shown in FIGS. 4 to 26, reference potential transmission lines 4, 5a and 5b are arranged in a direction crossing word lines 2a and 2b. When the word line 2a or 2b is selected, a plurality of memory transistors are simultaneously selected (when one word has a multi-bit configuration). However, reference potential transmission line 4, 5a or 4b only receives a current flowing from a bit line via at most one memory transistor. Therefore, reference potential transmission lines 4, 5a, and 5b only allow a much smaller current to flow than the configuration shown in FIG. 19, and it is possible to reliably prevent a rise in ground potential due to the bit line discharge. it can.

Further, reference potential transmission lines 4a, 5a, 5b
And 4b are formed of a low-resistance metal wiring layer. Therefore, variation in the source potential of the memory transistor caused by the current flowing therethrough can be reliably prevented. That is, by making the reference potential transmission lines 4a, 4b, 5a and 5b low resistance, the distributed resistance r becomes extremely small, and even if current flows there, only a very small voltage drop occurs.

Reference potential transmission lines 4a, 4b, 5a and 5
b is constituted by a low-resistance wiring layer, and at the same time, a current flows into and out of each reference potential transmission line via at most one memory transistor at a time, thereby enabling stable, reliable and high-speed operation. ROM can be obtained.

In the arrangement shown in FIGS. 24 to 26, reference potential transmission lines 4, (4a, 4b), 5a and 5
The set b is used. However, a set of reference potential transmission lines 4, 5a, 5b and 20 may be used.

Further, the arrangement shown in FIG. 24 is also applicable to the arrangements shown in FIGS.

In the above-described embodiment, although one word line can represent a plurality of different addresses,
One memory cell cannot be accessed at the same time. Next, a configuration capable of simultaneously accessing one memory cell will be described below.

FIG. 27 schematically shows an entire structure of a read-only semiconductor memory device according to still another embodiment of the present invention. In FIG. 27, read-only semiconductor memory device 6
00 includes a memory cell array 106 in which memory cells are arranged in a matrix. The memory cell array 106 has a structure that allows one memory cell to be accessed simultaneously through a plurality of independent paths, as will be described later in detail. In FIG. 27, the memory cell array 10
A configuration is shown by way of example, in which 6 can be accessed via two independent paths.

The read-only semiconductor memory device 600 further comprises
First decoder 108 for decoding first address input ADA and selecting a corresponding row of memory cell array 106
a, a second decoder 108b for decoding the second address input ADB and selecting a corresponding row of the memory cell array 106, and outputting data of a memory cell selected by the decoder 108a of the memory cell array 106. And a second output circuit 109 for outputting the data of the memory cell selected by the decoder 108b in the memory cell array 106.
b. The first output circuit 109a outputs output data DA, and the second output circuit 109b outputs output data DB.

Read only semiconductor memory device 600 further responds to externally applied control signals / CE (chip enable signal) and / OE (output enable signal) to generate various internal control signals ATA 'and AT.
B ′, OEA, OEB, control circuit 120 for generating φpA and φpB, and for precharging the potential of a bit line, which is an internal data transmission line of memory cell array 106, to a predetermined transposition in response to internal control signals φpA and φpB. And a reference potential setting circuit 111 that generates a reference potential for setting information stored in each memory cell of the memory cell array 106 in response to an externally applied reference potential setting signal S. Including.

Control signals ATA 'and ATB' give operation timings of first and second decoders 108a and 108b. Control signals OEA and OEB are output data DA and DB of output circuits 109a and 109b.
Output timing.

As described above, control circuit 120 responds to control signals / CE and / OE to generate internal control signals φpA and φpB, ATA ', ATB', OEB and OEA.
Occurs. In the configuration shown in FIG.
08a and the decoder 108b operate at the same timing. Similarly, precharge circuit 110a and precharge circuit 110b operate at the same timing, and output circuit 109a and output circuit 109b.
b operates at the same timing. However, the operation timings of these circuits may be configured to be different. When the operation timings of these circuits are made different, two different types of external control signals / CE and / OE
(Ie / CEA, / CEB, / OEA and / OE
B) may be applied to the control circuit 120, and only one or both of the groups may be driven at respective timings in response to these control signals. In the following description, it is assumed that circuits related to the circuits of each group (group A and group B) operate at the same timing.

Address inputs ADA and ADB are applied to decoders 108a and 108b. To be precise, an address input (internal address input) from an address buffer which receives an external address and generates an internal address is applied to each of the decoders 108a and 108b. This address buffer is omitted in FIG. 27 to simplify the drawing.

FIG. 28 schematically shows a structure of a main portion of the semiconductor memory device shown in FIG. In FIG. 28,
Memory cell array 106 is arranged in the row direction and stores word lines (row selection signal transmission lines) WA1 and WB1 receiving row selection signals from decoders 108a and 108b, and memory cells 220 connected to the selected word line. Line for transmitting the transmitted information (internal data transmission line)
BA1, BB1, BA2, and BB2,..., BA
n and BBn.

A plurality of word lines are provided for receiving the outputs of decoders 108a and 108b, however, in the configuration shown in FIG. 28, a word receiving the output (row select signal) from decoder 108a is representative. Line W
A1 and only word line WB1 receiving an output signal (row selection signal) from decoder 108b are representatively shown.
Each memory cell 220 includes a first memory element 1a and a second memory element 1b. The memory element 1a is connected to the word line WA
1 in response to the selection signal on the corresponding bit line BAi (i = 1, 2,..., N).
Communicate to Memory element 1b enters a selected state in response to a selection signal on word line WB1, and transmits its stored information to corresponding bit line BBi (i = 1, 2,..., N).

Memory cell array 106 is further provided corresponding to each of bit lines BA1-BAn.
8a is turned on in response to a selection signal (column selection signal) from 8a, and is provided corresponding to each of column selection transistors STA1-STAn for connecting the corresponding bit line to output circuit 109a, and bit lines BB1-BBn. Are turned on in response to a selection signal (column selection signal) from decoder 108b, and include column selection transistors STB1-STBn for connecting a corresponding bit line to output circuit 109b.

The decoder 108a supplies a column selection signal to each of the column selection transistors STA1 to STAn.
The individual is turned on. Similarly, decoder 108b supplies a column selection signal to column selection transistors STB1-STBn, and turns on one of them. However, this is the case of one word and one bit. If one word is composed of eight bits, eight column selection transistors are simultaneously turned on, and the corresponding bit lines are respectively connected to the output circuit via different IO lines. Connecting.

As shown in FIG. 28, one memory cell 2
20 includes two independently selectable memory elements 1a and 1b, so that two types of data can be simultaneously stored in one memory cell, and the same memory cell data is output to two output circuits 109a. And 109
b.

FIG. 29 shows an example of a specific structure of memory cell 220 shown in FIG. In FIG. 29, memory cell 220 includes two memory transistors 1a and 1b. Memory transistor 1a has a gate coupled to word line 2a and a drain coupled to bit line 3a.
And its source is connected to the common node NA. Memory transistor 1b has its gate connected to word line 2b, its drain connected to bit line 3b, and its source connected to common node NA. Word lines 2a and 2b are connected to word lines WA shown in FIG.
1 and WB1. Further, bit lines 3a and 3b are connected to bit lines BAi and BBi (i = 1, 2,.
.., n).

Memory cell 220 further includes reference potential transmitting lines 5a, 5b and 4 to each of which a reference potential is transmitted. Reference potential transmission line 4 is set to, for example, a ground potential level of "L". Reference potential setting circuit 111
A reference potential is generated from (see FIG. 27) and transmitted to reference potential transmission lines 5a and 5b. The reference potential setting circuit 111 corresponds to the reference potential generation circuit 50 shown in FIG.

At one end of each of bit lines 3a and 3b, precharge transistors TPA and TPB are provided. The precharge transistors TPA and TP
B precharges corresponding bit lines 3a and 3b to an "H" level which is, for example, operating power supply voltage Vcc level, in response to precharge signals φpA and φpB, respectively. The other ends of bit lines 3a and 3b are connected to select transistors STAi and STBi, respectively.

Reference potential transmission lines 5a and 5b are supplied with the same reference potential as that shown above. Memory element 1
a and 1b store the same data. Word line WAi
And WBi each represent two addresses. The operation of reading data from one of memory elements 1a and 1b is performed in a manner similar to that described above with reference to FIG.

The information stored in memory transistors (memory elements) 1a and 1b is based on the fact that their source terminals are connected to reference potential transmission lines 4, 5a and 5b via node NA.
Is determined according to the connection status of whether or not the connection is made. Reference potential transmission line 5a
And 5b are provided with two kinds of reference potentials in the reference potential setting circuit 1.
11 is transmitted.

Reference potential setting circuit 111 sets reference potentials of reference potential transmission lines 5a and 5b in response to a reference potential setting signal S externally applied. As the reference potential setting signal S, any of an operation mode designation signal, a bank selection signal, and an address signal may be used. Therefore, by providing the reference potential transmission lines 5a and 5b and the ground potential transmission line 4 in common to all the memory cells 220, each memory cell 220 can store two types of data.

The memory transistor 1a included in the memory cell 220 receives the select signal WL on the word line 2a (WAi).
Is turned on in response to. The other memory transistor 1b is turned on in response to the selection signal WL on the word line 2b (WBi). Therefore, when word line 2a is selected, information stored in memory cell 220 is transmitted onto bit line 3a. Therefore, even if word line 2b is selected at the same time, memory cell 22
Information stored in "0" is transmitted to another bit line 3b via memory transistor 1b. As a result, one memory cell 220 is accessed at the same time,
It can be read independently via two paths. In other words, one memory cell 220 and another memory cell can be accessed simultaneously and their data can be read in parallel. Next, an operation of simultaneously accessing different addresses in the same memory cycle will be described.

FIG. 30 is a diagram showing an example of an arrangement of a memory array when two words (one word is one bit) are formed using the memory cells shown in FIG. In FIG.
Memory cell 220a is selected by either word line 2a or 2b. When word line 2a is selected, information stored in memory cell 220a is transmitted to bit line 3a. When word line 2b is selected, memory cell 220a transmits stored information to bit line 3b.

Memory cell 220b is selected by word line 2c or 2d. When word line 2c is selected, memory cell 220a transmits the stored information to bit line 3a. When word line 2d is selected, information stored in memory cell 220b is transmitted to bit line 3b. Word lines 2a and 2c are connected to decoder 108a.
(See FIG. 27). Word lines 2b and 2d are selected by decoder 108b.

Now, consider the case where word line 2a is selected for memory cell 220a. In this case, the information stored in memory cell 220a is transmitted to bit line 3a. For the memory cell 220b, the decoder 108b
Can set the word line 2d to the selected state. In this case, the information stored in memory cell 220b is transmitted to bit line 3b. Data on bit lines 3a and 3b are independently transmitted to output circuits 109a and 109b via column select transistors STAi and STBj. Therefore, in one memory cycle, memory cell 220
The information stored in a and the information stored in memory cell 220b can be read simultaneously.

In the above case, word lines 2b and 2c may be selected and information stored in memory cells 220a and 220b may be transmitted to bit lines 3b and 3a, respectively. In either case, the decoders 108a and 108b are driven simultaneously to select two memory cells at the same time and to read information of the selected memory cells at the same time.

In the structure of the memory cell shown in FIG. 30, the information stored in memory cells 220a and 220b is determined by the connection between common node NA and reference potential transmission lines 4, 5a and 5b.

In this case, memory cells 220a and 220a
Each of Ob can store multiple words. Therefore, one memory cell can store a plurality of words of information according to its operation mode and the like, and the chip occupation area can be greatly reduced as compared with the conventional ROM configuration.

In the structure of the memory cell shown in FIG.
As shown in FIG. 31, the structure of the reference potential transmission line is 4
The reference potential transmission lines 4, 5a, 5b and 70 are used, and the common node NA is connected to the four reference potential transmission lines 4, 5
a, 5b, and 70 may be used.

As shown in FIG. 31, each bit line 3a,
A configuration in which the precharge potential of 3b is precharged to an intermediate potential of Vcc / 1 may be used. FIG. 2
In the configuration shown in FIG. 7 and thereafter, a configuration in which the bit line 3 and the reference potential transmission lines 4, 5a, 5b, 70 are arranged in parallel may be used.

In the configuration shown in FIG.
Each memory cell includes two memory elements (memory transistors) and can read two types of data in parallel. The number of transistors constituting the memory cell may be three or more.

In the configuration of the semiconductor memory device shown in FIG. 27, control circuit 120 generates various internal control signals in response to control signals / CE and / OE. In this case, an address change detection circuit may be used to detect a change in externally applied address signals ADA and ADB, and the output of the address change detection circuit may be used as a control signal for determining internal operation timing.

Further, the decoding operation timing of decoders 108a and 108b is not determined by the control signal from control circuit 120, but a configuration in which address inputs ADA and ADB are decoded as they are may be used. In this case, the output states of the decoders 108a and 108b remain the same until the address inputs ADA and ADB change.

The structure using an address change detection signal as an internal clock signal (internal control signal) may be used in the configuration of the semiconductor memory device shown in FIG.

Further, reference potential transmission lines 4 and 70 may be configured to be externally supplied with a ground potential and a power supply potential.

Since the memory cell structure shown in FIGS. 29 and 31 can form the control system shown in FIG. 40 using one ROM chip, a control system having an extremely small occupied area can be constructed.

Further, the multiport R shown in FIG.
In the case of the memory cell structure for the OM configuration, the arrangement relationship between the reference potential transmission lines and the bit lines as shown in FIGS. 24 to 26 may be used.

Further, in a multiprocessor system for digital signal processing, if the ROM of the present invention is used as a common memory, such a system can be constructed with a small occupation area, and high-speed data processing can be realized. it can.

[0184]

As described above, according to the first aspect of the present invention, a plurality of reference potential transmission lines whose potentials can be changed are provided, and the connection relationship between the memory cell transistor and the plurality of reference potential transmission lines is determined. Since data is stored, a plurality of different word bits can be stored using one memory cell transistor.
Can be reduced in size. Thus, for example, for digital signal processing, the area occupied by the ROM integrated on the same chip as the signal processing circuit can be significantly reduced. In addition, the number of transistors in the memory cell array can be significantly reduced, and a sufficient area for forming a memory transistor can be secured if the array area is the same.

According to the configuration of the first aspect of the present invention, one word line can be associated with a plurality of addresses, so that the number of word lines is significantly reduced as compared with the conventional device, and the address decoder The circuit scale of the unit can also be significantly reduced. For example, if one memory cell represents two different word bits, one word line corresponds to two addresses, so that in this case the number of transistors in the memory cell array is １ ／ and the number of word lines is This is reduced to half that of the conventional device, and accordingly the device scale of the address decoder is also reduced to half or less.

According to the second aspect of the present invention, since the bit line and the reference potential transmission line are arranged in parallel, the amount of current flowing through the reference potential transmission line can be greatly reduced.
The reference potential can be stabilized, noise can be prevented, and memory cell data can be read stably and reliably at high speed.

As described above, according to the present invention, a stably operable ROM suitable for high integration with a small occupied area can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a configuration of a memory cell of a ROM according to an embodiment of the present invention.

FIG. 2 is a diagram schematically showing an entire configuration of a ROM according to an embodiment of the present invention.

FIG. 3 is a diagram showing a list of operations of the ROM memory cell shown in FIG. 1;

FIG. 4 is a diagram showing a configuration of a memory cell array unit when a ROM of 8 words × 1 bit is configured using the ROM memory cells shown in FIG. 1;

FIG. 5 is a diagram showing a list of operations of the ROM shown in FIG. 4;

FIG. 6 is a diagram showing an example of an arrangement of a memory cell array when a memory of plural words × multiple bits is formed using the ROM memory cells shown in FIG. 1;

FIG. 7 shows an RO having the memory cell array arrangement shown in FIG.
It is a figure which shows operation | movement of M as a list.

8 is a diagram showing another configuration example of the memory cell array arrangement shown in FIG. 6;

9 is a diagram showing an example of a specific configuration of the reference potential generation circuit shown in FIG.

FIG. 10 is a diagram showing another configuration example of the ROM memory cell.

FIG. 11 is a diagram showing a list of operations of the ROM memory cell shown in FIG. 10;

FIG. 12 is a diagram showing an example of a configuration when a bit line potential is precharged to Vcc / 2.

FIG. 13 shows one ROM according to the present invention with three banks.
FIG. 9 is a diagram showing a list of possible combinations of data that can be stored by one memory cell when expressed by.

14 is a diagram schematically showing a structure of a memory cell for realizing the storage data shown in FIG.

FIG. 15 is a diagram showing a list of operations of the memory cell shown in FIG. 14;

16 is a diagram showing a configuration of a reference potential generation circuit for the ROM memory cell structure shown in FIG.

17 is a diagram sequentially showing a correspondence relationship between the bank selection signal (reference potential setting signal) shown in FIG. 16 and a bank selected at that time.

FIG. 18 is a diagram conceptually showing a configuration of an array portion of a ROM according to still another embodiment of the present invention.

FIG. 19 is a diagram schematically showing a layout of a conventional ROM memory cell.

20 is a diagram showing a cross-sectional structure taken along line AA 'shown in FIG.

FIG. 21 is a diagram showing a correspondence relationship between one word line and a ground line in a conventional ROM memory cell array arrangement.

FIG. 22 is a diagram showing a potential change on a ground line when a word line is selected in the array arrangement shown in FIG. 21;

FIG. 23 is a diagram showing variations in source potential in the memory cell arrangement shown in FIG. 21;

FIG. 24 is a diagram schematically showing a layout of a ROM memory cell arrangement according to still another embodiment of the present invention;

25 is a drawing schematically showing a cross-sectional structure along a line BB ′ shown in FIG. 24.

FIG. 26 is a circuit diagram showing a memory cell arrangement electrically equivalent to the layout shown in FIG. 24;

FIG. 27 is a diagram schematically showing another entire configuration of a ROM according to still another embodiment of the present invention.

28 is a diagram schematically showing a configuration of a memory cell array section of the ROM shown in FIG. 27;

FIG. 29 is a diagram showing an example of the structure of the ROM memory cell shown in FIG. 28;

30 is a diagram schematically showing a configuration of a memory cell array when a plurality of memory cells shown in FIG. 29 are arranged.

FIG. 31 is a diagram showing another structure of the memory cell array shown in FIG. 28.

FIG. 32 is a diagram schematically showing an entire configuration of a conventional ROM.

FIG. 33 schematically shows a structure of a conventional ROM memory cell.

FIG. 34 is a signal waveform diagram showing an operation of a conventional ROM.

FIG. 35 is a diagram schematically showing a configuration of a memory cell array of a conventional ROM.

36 is a diagram showing a list of operations in the memory cell array shown in FIG. 35;

FIG. 37 is a diagram showing an example of a connection mode for performing a table look-up operation using a conventional ROM.

FIG. 38 is a diagram schematically showing a configuration example of a conventional system when a coefficient ROM is configured by banks.

FIG. 39 is a diagram illustrating an example of a system configuration when a ROM is used as a program ROM.

FIG. 40 is a diagram illustrating a configuration example when a control system is configured using a ROM of a table lookup system.

[Explanation of symbols]

 Reference Signs List 1 memory cell transistor M1 memory cell 2 word line 3 bit line 4 ground line (reference potential transmission line) 5a reference potential transmission line 5b reference potential transmission line 55a reference potential transmission line 55b reference potential transmission line 56a reference potential transmission line 56b reference potential Transmission line 57a Reference potential transmission line 57b Reference potential transmission line 58 Reference potential transmission line 70 Reference potential transmission line 6 Memory cell array 7 Address buffer 8 Address decoder 9 Output circuit 10 Control circuit 20 Reference potential transmission line 50 Reference potential generation circuit 108a First 108b Second decoder 110a Precharge circuit 110b Precharge circuit 111 Reference potential setting circuit 109a First output circuit 109b Second output circuit 220 Memory cell 1a Memory cell 1b Memory cell

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kazuya Ishihara 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSI Research Institute (56) References JP-A-58-137194 (JP, A) )

Claims (2)

(57) [Claims] At least one bit line for transmitting internal data, a plurality of word lines arranged to intersect with the bit line and to which a row selection signal is respectively transmitted, and the bit line and the plurality of bit lines A plurality of memory cells provided corresponding to the respective intersections of the word lines, each storing data, a plurality of reference potential transmission lines commonly and connectably arranged to the plurality of memory cells, and A potential setting means for setting a potential of each of the plurality of reference potential transmission lines in response to a potential instruction signal from the memory device, wherein each of the plurality of memory cells is selectively connected to any of the plurality of reference potential transmission lines. A memory transistor that stores data by being connected to or disconnected from all of the memory cells, wherein each of the memory cells has a row selection signal on a corresponding word line. When activated, the bit line and one of the plurality of reference potential transmission lines are electrically connected to the bit line, or all of the plurality of reference potential transmission lines are electrically separated from the bit line to store the data. A read-only semiconductor memory device from which data is read. 2. The read-only semiconductor memory device according to claim 1, wherein said plurality of reference potential transmission lines are arranged in parallel with said bit lines.