JP2641602B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device such as an EPPOM or an EPPROM.

[Conventional technology]

FIG. 2 is a circuit diagram showing a basic configuration of a conventional EPRMOM. As shown in the figure, memory cells (memory transistors) 1 are arranged in a matrix (only two rows and six columns are shown in the figure). The memory transistor 1 has a floating gate and can perform nonvolatile storage. The drain of the memory transistor 1 is commonly connected to the bit line 2 in column units, the control gate is commonly connected to the word line 3 in row units, and the source is a predetermined number of columns (3 in the figure).
The source 4 is commonly connected to each column.

Each bit line 2 is commonly connected to an I / O line 7 via a Y gate transistor 6 in units of a predetermined number of columns (three columns in the figure). The output of the column decoder 5 is applied to the gate of the Y gate transistor 6, and the word line 3 is connected to the row decoder 8. Column decoder 5 selectively sets its output to H level or high voltage _VPP level based on a column address signal obtained from address buffer 9. On the other hand, the row decoder 8 has an address buffer 9
Based on the obtained row address signal, word line 3 is selectively set to H level or high voltage _VPP level.

Each I / O line 7 is connected to a sense amplifier 11 via a read transistor 10 and to a high voltage power supply _VPP via a write transistor 12. The read signal R is applied to the gate of the read transistor 10, and the output of the booster circuit 13 is applied to the gate of the write transistor 12. The sense amplifier 11 outputs 1-bit output data S11 to be described later to the input / output buffer 14, and the booster circuit 13 receives the write signal W and the 1-bit write data S14. The booster circuit 13 is activated when the write signal W is H, and outputs a high voltage _VPP to the gate of the write transistor 12 when the 1-bit write data S14 is H.
When the 1-bit write data S14 is L, the L level is output to the gate of the write transistor 12. Note that the write signal W and the read signal R are supplied to the control signal generation circuit 15.
Output based on an external control signal (not shown).

The input / output buffer 14 simultaneously writes L / H 1-bit write data S14 to the respective booster circuits 13 in units of 1 byte (8 bits) in correspondence with external write data “1” / “0”.
At the time of reading, the 1-bit output data S11 latched by the sense amplifier 11 at the same time in a byte unit is taken in, and "0" /
The external read data of “1” is output. The number of the sense amplifiers 11 (booster circuits 13) is eight or more (8n (n ≧ n)
2)) is a general case, and in order to take in the bit data stored in all the sense amplifiers 11 at the time of reading, 1-bit output data S11 of 1 byte is divided into n times and sequentially sent to the input / output buffer 14. Need to capture.

An operation of writing data to the memory transistor of the EPROM having such a configuration will be described. Note that an erasing operation needs to be performed before performing a writing operation.

The erasing operation is performed by irradiating ultraviolet rays from above the EPROM chip. When the ultraviolet rays are irradiated, the electrons accumulated in the floating gates of all the memory transistors 1 are released, and the threshold voltage is lowered to about 1 V (the threshold voltage at this time is Vth1). This state corresponds to the “1” storage state.

After the erasing operation is performed, a writing operation is performed. During a write operation, the read signal R is set to L, and the write signal W
Is set to H, the sense up 11 and the I / O line 7 are electrically cut off, and the booster circuit 13 is activated. And source line 4
To the ground, and selectively output the output of the column decoder 5 to a high voltage.
While selecting a bit line 2 by raising the V _PP, selectively the word line 3 the high voltage by the row decoder 8
Launch to V _PP . With this setting, the 1-bit write data S14 fetched from the input / output buffer 14 becomes H
, The high voltage V _{PP is} applied to the gate of the write transistor 12.
Is applied, and in the case of L, L is applied to the gate of the writing transistor 12.

As a result, the selected memory transistor 1 at the intersection of the selected word line 3 and bit line 2
When the 1-bit write data S14 taken from 14 is H indicating "0" write, a high voltage _VPP is applied to its drain and control gate, and hot electrons generated by avalanche collapse near the drain are injected into the floating gate. As a result, the threshold voltage increases to 6 to 8 V (the threshold voltage at this time and Vth2 (> Vt
h1)). The state of the memory transistor 1 is "0"
This corresponds to the storage state. On the other hand, when the 1-bit write data S14 fetched from the input / output buffer 14 is L indicating "1" write, the drain becomes floating, so that avalanche collapse does not occur near the drain, the threshold voltage is maintained at Vth1, and " 1 "Keep the memory state. Thus, data writing to the memory transistor 1 is performed.

Next, an operation of reading stored data written in the memory transistor will be described.

At the time of the read operation, the read signal R is set to H, the write signal W is set to L, the sense amplifier 11 is electrically connected to the I / O line 7, and the booster circuit 13 is deactivated. Then, by grounding the source line 4 and selectively setting the output of the column decoder 5 to H, the bit line 2 is selected,
The row decoder 8 selectively applies a read voltage VR (Vth1 <VR <Vth2) of about 5 V to the word line 3. With this setting, when “0” is stored in the selected memory transistor 1, the current flows from the I / O line 7 to the source line 4 via the bit line 2 to maintain the off state of the selected memory transistor 1. Does not flow and the selected memory transistor 1
When "1" is stored in the memory transistor 1, since the memory transistor 1 is turned on, a current flows from the I / O line 7 to the source line 4 via the bit line 2. The presence or absence of this current flow is sensed by the sense amplifier 11, and 1-bit output data S11 which is L when current is detected and H when current is not detected is output to the input / output buffer 14. Then, the external read data is output to the outside from the input / output buffer 14 in 1-byte units, so that the content stored in the selected memory transistor 1 is read.

By the way, the pulse width (high voltage V _PP) necessary for writing even between EPROM memory transistors in the same chip
And the write characteristics vary. For this reason, it is difficult to accurately write all the memory transistors by one write operation, and it is necessary to detect the memory transistors that need to be rewritten. Therefore, after the writing, a verify operation is generally performed to confirm that the writing ("0") has been normally performed.

The verify operation reads out the data stored in the memory transistor to the outside each time the write operation is performed in 1-byte units during the execution of the write operation of the EPROM, and compares the read data with the write data to determine whether the data has been written normally. Is the operation to check. When a write error is detected by this verify operation, rewrite is performed. The write operation having such a verify function is performed by a dedicated external device called a PROM writer.

[Problems to be solved by the invention]

A conventional non-volatile semiconductor memory device such as an EPROM which needs to execute a write operation having a verify function is configured as described above, and only one bit in one byte is insufficiently written by the verify operation. Even if there is a rewrite operation, the rewrite operation is performed in units of 1 byte as in the case of the write operation.
There has been a problem that overwriting may occur and reliability is reduced.

The present invention has been made to solve the above problems, and has as its object to provide a nonvolatile semiconductor memory device capable of performing writing with a verify function without fear of overwriting.

[Means for solving the problem]

A nonvolatile semiconductor memory device according to the present invention includes a memory cell including a floating gate and a memory transistor that performs nonvolatile storage, and includes a plurality of memory cells selected in a predetermined number based on an external address signal in an active state. Writing means for performing non-volatile writing on the selected memory transistor in accordance with external write data, read means for outputting the storage contents of the plurality of selected memory transistors as internal read data in an active state, At the time, the external write data and the internal read data in each of the selected memory transistors are compared with each other, and a data comparing means for outputting a comparison signal indicating a match / mismatch thereof, respectively, and the write means is activated at the time of writing. , The plurality of selected memory tracks After writing the register, activating the readout means continues for internal reading of the contents of the plurality of selected memory transistors,
Subsequently, the data verifying unit is activated to perform a write verify operation of comparing the external write data and the internal read data in each of the selected memory transistors. Executing the write operation to the memory transistor, and if at least one of the comparison signals indicates a mismatch at this time, performing the write operation again only to the selected memory transistor in which the comparison signal indicating the mismatch is detected Control means.

[Action]

The write control means in the present invention activates the write means, writes data to the plurality of selected memory transistors, activates the read means to perform internal reading of the stored contents of the plurality of selected memory transistors, and thereafter performs data comparison. Activating the means to execute a write verify operation for comparing external write data and internal read data in each of the selected memory transistors,
When at least one comparison signal indicates a mismatch, the write operation is performed again only on the selected memory transistor on which the comparison signal indicating the mismatch is detected. Therefore, the selected memory transistor on which the comparison signal indicating the match is detected is performed. Is not rewritten.

〔Example〕

FIG. 1 is a circuit diagram showing a basic configuration of an EPROM according to an embodiment of the present invention. As shown in the figure, a write verify control circuit 21, a comparator 22, an OR gate 23, and a latch 24 are newly added. The write verify control circuit 21 receives the write signal W from the control signal generation circuit 15 and the output signal S23 of the OR gate 23, and outputs a write signal W2, a read signal R, and a verify signal C. More specifically, when an H-level write signal W is supplied, the write signal W is activated, and the L-level write signal W2, the read signal R and the verify signal C are sequentially raised to the H level, and the write operation with the verify function is performed. Control. The H-level output time of these signals W2, R, C is set to a predetermined time using an internal timer. The write verify control circuit 21 outputs the output signal S2 of the OR gate 23.
3, and when it is determined that rewriting is necessary based on this signal S23, a rewriting operation described later is executed.

The comparators 22 and the latches 24 are provided corresponding to the sense amplifiers 11, that is, the number of the comparators 22 and the latches 24 is generally 8n like the sense amplifier 11 (the booster circuit 13) (only two are shown in the figure). ) Is provided. The comparator 22 receives the verify signal C, the one-bit latch data S24 from the latch 24, and the one-bit output data S11 of the sense amplifier 11. When the verify signal C is H, the comparator 22 is activated and the one-bit output data S11 and the one-bit latch data are received. S24 is compared, and if they match, H is output, and if they do not match, the comparison result S22 of L is output to the corresponding latch 24.

The latch 24 latches the 1-bit write data S14 of the input / output buffer 14 as 1-bit latch data S24, and uses the 1-bit latch data S24 as the booster circuit 13 and the comparator 2
2 and output to the input of the OR gate 23. Further, the comparator 22 receives the comparison result S22 of the comparator 22, and is reset only when the comparison result S22 is at H, and the 1-bit latch data S24 becomes L
Fixed to When the comparison result S22 is L, the bit latch data S24 does not change.

The OR gate 23 takes in 1-bit latch data S24 of 1 byte (only two are shown in the figure), and outputs an output signal S23 which is a logical sum thereof to the write verify control circuit 21.
The other configuration is the same as that of the conventional example shown in FIG.

The data writing to the memory transistor of the EPROM having such a configuration is executed after the erasing operation is executed. The erasing operation is performed by irradiating ultraviolet rays from above the EPROM chip as in the conventional case, and setting the threshold voltages of all memory transistors 1 to Vth1
(“1” storage state).

The write operation is started by giving the write signal W of H to the write verify control circuit 21 from the control signal generation circuit 15. Then, the write verify control circuit 21 is activated, the write signal W2 rises to H, the read signal R and the verify signal C change to L,
The sense-up circuit 11 is electrically disconnected from the I / O line 7 to activate the booster circuit 13. The bit line 2 is selected by selectively raising the output of the column decoder 5 to the high voltage V _PP, and the word line 3 is selectively raised to the high voltage V _PP by the row decoder 8. Then, when the 1-bit write data S14 taken in from the input / output buffer 14 is H, that is, when the 1-bit latch data S24 latched by the latch 24 is H, the high voltage _VPP is applied to the gate of the write transistor 12. , L, the gate of the write transistor 12 is supplied with L.

As a result, the selected memory transistor 1 at the intersection of the selected word line 3 and bit line 2
When the 1-bit write data S14 taken in from the H is an H level indicating "0" write, a high voltage _VPP is applied to the drain and the control gate, and hot electrons generated by avalanche collapse near the drain are applied to the floating gate. And its threshold voltage is Vth2
(> Vth1). This state of the memory transistor 1 corresponds to the “0” storage state. On the other hand, 1-bit write data
When S14 is at the L level instructing "1" writing, the drain becomes floating, avalanche collapse does not occur near the drain, the threshold voltage is maintained at Vth1, and the "1" storage state is maintained. Thus, data writing to the selected memory transistor 1 is performed.

Thereafter, the write signal W2 falls to L, and the read signal R rises to H. Then, the sense amplifier 11 and I /
The O line 7 is electrically connected, and the booster circuit 13 is deactivated. Then, the output of the column decoder 5 is selectively set to H level.
, The bit line 2 is selected, and
A read voltage VR of about 5 V (Vth1 <VR <Vth2) is selectively applied to the word line 3 by the row decoder 8. Then, when writing to the selected memory transistor 1 is sufficient, the selected memory transistor 1 maintains the off state, so that no current flows from the I / O line 7 to the source line 4 via the bit line 2 and the selected memory transistor 1 If writing to 1 is insufficient, the memory transistor 1 is turned on, so that a current flows from the I / O line 7 to the source line 4 via the bit line 2. The sense amplifier 11 senses the presence or absence of this current flow, and outputs L when current is detected and H when current is not detected.
Is output to the input / output buffer 14 and the comparator 22 is output.

Thereafter, the read signal R falls to L, and the verify signal C rises to H. When the verify signal C becomes H, the comparator 22 becomes active and the sense amplifier
11 is compared with the 1-bit write data S14 output from the input / output buffer 14, and S11 = 14
To output a comparison result S22 of L and S11 ≠ 14. That is,
When the comparison result S22 is L, it means that writing to the selected memory transistor could not be performed normally. And H
The latch 24 given the comparison result S22 is reset,
The 1-bit latch data S24 becomes L. On the other hand, the 1-bit latch data S24 of the latch 24 to which the comparison result S22 of L is given does not change. The above steps are the write operation with the verify function executed in units of one byte.

1-bit latch data S24 captured by OR gate 23
Is H at any one point, that is, although the 1-bit write data S14 is at the H level instructing the writing of “0”, the L-level 1-bit output data S11 instructing the “1” storage state If at least one read memory transistor 1 exists, the output signal S23 of the OR gate 23 is output.
Becomes H. On the other hand, when all the one-bit latch data S24 is L, the output signal S23 of the OR gate 23 becomes L. When the output signal S23 is at L, the write verify control circuit 21 ends the write operation, and when it is at H, the write operation with verify function is executed again.

At the time of rewriting, all the latches 24 corresponding to the normally written memory transistors 1 have been reset. Therefore, since the output of the booster circuit 13 becomes L by outputting the L-bit latch data S24 to the booster circuit 13, rewriting is not performed on the normally written memory transistor 1, and a write failure is detected. Rewriting is performed only on the memory transistor 1.

Therefore, when "0" cannot be normally written in at least one of the memory transistors at the time of writing, rewriting can be performed only on the memory transistor for which defective writing has been detected. Therefore, when rewriting is performed, rewriting is not performed on the memory transistor that has been normally written, and there is no fear of overwriting. As a result, even if the writing characteristics of the memory transistors vary, writing can be performed without loss of reliability by using only the internal components of the EPROM without connecting to an external device such as a PROM writer. . Note that the reading operation is performed in the same manner as in the related art, and thus the description is omitted.

In this embodiment, the nonvolatile semiconductor memory device is
EPROM is shown, but not limited to flash EEPROM
Can be applied to all nonvolatile semiconductor memory devices that require a verify operation after writing.

〔The invention's effect〕

As described above, according to the present invention, the write control unit activates the write unit, writes data to the plurality of selected memory transistors, and then activates the read unit to store the contents of the plurality of selected memory transistors. An internal read operation is performed, and thereafter, a data verifying unit is activated to execute a write verify operation for comparing the external write data and the internal read data in each of the selected memory transistors. If at least one comparison signal indicates a mismatch, the write verify operation is performed again. The write operation is performed only on the selected memory transistor in which the comparison signal indicating the mismatch is detected, and is performed on the selected memory transistor in which the comparison signal indicating the match is detected, that is, the memory transistor that is normally written. Is not rewritten, Without fear of inclusive can, it is possible to write with verify function.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration of an EPROM according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a basic configuration of a conventional EPROM. In the figure, 1 is a memory transistor, 11 is a sense amplifier, 21 is a write verify control circuit, 22 is a comparator, 23 is an OR gate, and 24 is a latch. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinichi Kobayashi 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Machinery Co., Ltd. No. 1 Inside of Mitsubishi Electric Corp. LSI Laboratory (56) References JP-A-60-15896 (JP, A) JP-A-59-135698 (JP, A) JP-A-2-142000 (JP, A)

Claims (1)

(57) [Claims] 1. A non-volatile semiconductor memory device having a memory cell comprising a memory transistor having a floating gate and performing non-volatile storage, wherein the memory cell is selected in a predetermined number unit based on an external address signal in an active state. Writing means for performing non-volatile writing on a plurality of selected memory transistors in accordance with external write data; reading means for outputting stored contents of the plurality of selected memory transistors as internal read data in an active state; A data comparison unit that compares the external write data and the internal read data in each of the select transistors and outputs a comparison signal indicating match / mismatch thereof; and activating the write unit during writing. To multiple selected memory transistors After writing, the read means is successively activated to perform internal reading of the storage contents of the plurality of selected memory transistors, and subsequently, the data comparison means is subsequently activated to execute the external writing in each of the selected memory transistors. A write verify operation for comparing data with the internal read data is performed on the plurality of selected memory transistors selected by one external address signal, and at this time, at least one of the comparison signals indicates a mismatch. And a write control unit for performing a write operation again only on the selected memory transistor in which the comparison signal indicating the mismatch is detected.