JP2642295B2 - Clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a clock frequency-synchronized with a network in a terminal connectable to a basic interface of an integrated services digital network (ISDN).

[0002]

2. Description of the Related Art In a terminal connectable to an ISDN basic interface, generating a clock frequency-synchronized with a network clock is very important in processing a layer 1 signal. In particular, A / D and D of B channel
In the / A conversion processing, the MASH type of the oversampling method is often used in accordance with the high integration of digital circuits, and an oversampling clock frequency-synchronized with a network is required. The signal obtained as the network timing clock is the transmission speed of the layer 1 signal (ideal value is 192 kb / s), and the oversampling clock is the power of 2 of the B channel transmission speed (ideal value is 64 kb / s). A few times higher frequency is required. Conventionally, a clock that is an integral multiple of the layer 1 signal speed is created using an analog PLL circuit, and the necessary clock is created by dividing the frequency.

[0003]

By the way, from the viewpoint of miniaturization and economy of terminals, it is inevitable to integrate the basic functions into integrated parts. However, in the above-described conventional technique in which a clock frequency-synchronized with a network is created using an analog PLL circuit, the analog PLL circuit has difficulty in terms of integration.
Therefore, a technology for realizing such a clock generation function by a digital circuit has been required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to realize a clock required for a terminal connected to a basic interface of an ISDN by a digital circuit, thereby facilitating high integration. To provide a clock generation circuit.

[0005]

In order to achieve the above object, in the clock generation circuit of the present invention, m is an integer sufficiently larger than 1 and n = 2m, and layer 1 in the basic interface of the integrated digital service network is set. A first method for generating two types of clocks A and B having a half frequency and different phases by a half cycle from a basic clock having a frequency n times the ideal data transfer rate of a signal. A second frequency dividing circuit for generating three types of clocks C, D and E having a frequency of 1/3 thereof and different phases by 1/3 period from the basic clock at the same time as the frequency dividing circuit; A first switch circuit for switching and outputting the clock A and the clock B in response to an external control signal; and a first switch circuit. A phase correction clock generation circuit that generates a phase correction clock obtained by dividing the output signal of the above to a frequency of 1 / m, a timing signal generation circuit that generates a network clock timing signal from a layer 1 signal including jitter, A phase comparison circuit that compares the phase of the phase correction clock with the timing signal of the network clock to generate a phase delay signal or a phase advance signal, and corrects the phase using the phase delay signal or the phase advance signal. Switching signal generation circuit for generating a clock switching signal for switching, a second switch circuit for switching and outputting the clock C, the clock D and the clock E by an external control signal, and the second switch A third frequency divider for dividing an output signal of the circuit, the control of the first switch circuit; No. and as a control signal of said second switching circuit has a configuration of using the clock switching signal.

[0006]

In the clock generating circuit of the present invention, a clock for generating a clock for phase correction is generated by the first frequency divider and a clock for generating a target clock is generated by the second frequency divider. Here, the clocks generated by the first frequency divider are two clocks A and B having different phases, and the switching of the clocks can be controlled to correct the delay / advance of the phase of the phase correction clock. Also, the clocks generated by the second frequency divider are three clocks C, D, and E having different phases, and by switching these clocks, the phase of the target clock created by the third frequency divider is changed. Make correction possible. By providing these clocks A, B, C, D, and E with a predetermined frequency and phase relationship, a correction phase value when the clocks A and B are switched and a correction phase value when the clocks C, D, and E are switched. By making the correction phase values the same (one cycle of the basic clock), the phase correction can be commonly controlled. The phase correction signal is compared with a timing signal of a network clock generated from the layer 1 signal including jitter, and the clocks A and B are calculated from the phase delay signal or the phase advance signal.
By controlling the switching of the clocks C, D, and E, phase correction is performed, and a desired clock frequency-synchronized with the network is obtained by a digital circuit configuration.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of application in a terminal.

In FIG. 1, reference numeral 10 denotes a clock generation circuit according to the present embodiment, and 1 is an ideal data transfer rate of a layer 1 signal in a basic interface of an integrated services digital network (ISDN). From a basic clock having a frequency of n times 192 kb / s (n = 2 m, m is an integer sufficiently larger than 1), a half of that
The first frequency divider circuit 2 for generating two types of clocks A and B having a frequency of and having phases different by １ ／ cycle has a frequency of １ ／ of the basic clock and 1 / A second method for generating three types of clocks C, D and E having phases different from each other by three periods
The frequency divider circuit 3 has a clock switching signal,
A first switch circuit for switching and outputting the clock A and the clock B, and a phase correction clock generation circuit for generating a phase correction clock obtained by dividing the output signal of the first switch circuit to a frequency of 1 / m. A circuit 5, a timing signal generating circuit for generating a network clock timing signal from a layer 1 signal (AMI signal) including jitter; and 6, a phase comparing circuit for comparing the phase of the phase correction clock with the phase of the network clock timing signal. A phase comparison circuit for generating a delay or phase advance signal; 7, a clock switching signal generation circuit for generating the clock switching signal using the phase delay signal or phase advance signal; and 8, a clock switching signal based on the clock switching signal. C, clock D
And a second switch circuit 9 for switching and outputting the clock E, and a third frequency divider circuit 9 for dividing the output signal of the switch circuit 8 to create a target clock.

On the other hand, FIG.
An AMI code which is a layer 1 signal including 144 MHz ([32] times 192 kHz) and jitter (ideal value is 192 kHz
b / s), a clock having a frequency which is a power of 2 times the B-channel signal speed (ideal value: 64 kHz) synchronized with the network signal is generated and supplied to the processing unit of the terminal. It is. FIG. 2 shows that m =
16 corresponds to the case.

In FIG. 2, a first frequency divider 1
Is, as shown in the operation explanatory diagram of the first frequency divider circuit of FIG.
Two types of clocks (clock A and clock B) having MHz and being shifted by a half cycle phase are generated. As shown in the operation explanatory diagram of the second frequency divider circuit in FIG. 4, the second frequency divider circuit 2 has a frequency of 2.048 MHz that is 1/3 that of the basic clock and has a 1/3 period phase shift. The three types of clocks (clock C, clock D, and clock E) are created. The first switch circuit 3 switches and outputs the clock A and the clock B in order to correct the phase of the phase correction clock in accordance with the clock switching control signal. The clock generation circuit 4 for phase correction
The frequency of the output signal of the switch circuit 3 is divided by 1/16 to generate a clock for phase correction. The timing signal creation circuit 5 creates a network clock timing signal from the layer 1 signal including jitter. The phase comparison circuit 6 compares the phase of the phase correction clock created by the phase correction clock creation circuit 4 with the timing signal of the halftone clock created by the timing signal creation circuit 5 to generate a phase delay signal or a phase advance signal. create. The clock switching signal generation circuit 7 generates a clock switching signal for correcting the above-described phase using the phase delay signal or the phase advance signal generated by the phase comparison circuit 6. The second switch circuit 8 switches and outputs the clock C, the clock D, and the clock E according to the clock switching signal for correcting the phase. The third frequency divider 9 uses the output signal of the second switch circuit 8 to generate B
Create clocks required for channel processing. 10 is the above 1
It is a clock generation circuit composed of up to 9 blocks,
11 divides the frequency of the output signal of the first switch circuit 3,
This is a fourth frequency divider circuit that creates various clocks required for protocol processing. Reference numeral 12 denotes a B-channel processing unit that performs B-channel processing using the clock generated by the third frequency divider 9. 13 uses the clock generated by the fourth frequency divider circuit 11 to perform layer 1 (I.
430 recommendation) and a layer 2 (I.441 recommendation) process.

The operation and operation of the embodiment configured as described above will be described.

As an example of a method for implementing phase correction, the operation of the third switch circuit 1 will be specifically described with reference to the operation explanatory diagram of the first switch circuit in FIG.

First, when it is desired to correct the phase in the direction of advancing the phase, the clock (here, clock A) used to create the phase correction clock at that time is switched to the other clock (clock B in this case). . As the switching timing, when the phase is advanced, the clock which is not used at the time of detection (clock B in this case)
Is used. Conversely, when the phase is corrected so as to delay the phase, the clock A is similarly switched to the other clock (the clock B in this case), but the switching timing is determined by the clock used in the detection (the clock in this case). Use the falling edge of A).
By dividing the clock obtained as a result of this switching operation to a frequency of 1/16, a clock for phase correction is created.

On the other hand, as shown in the timing signal generation circuit operation explanatory diagram of FIG. 6, a layer 1 signal (AM
I code: Alternative Mark Inve
(Rsion Code), a digital signal indicating the presence of positive and negative pulses is created and differentiated to obtain a digital signal.
Create a network clock timing signal.

Next, the phase of the phase correction clock and the phase of the timing signal of the network clock are compared to generate a phase lag / lead signal. The clock switching signal generation circuit generates signals for switching between the clocks A and B and for switching between the clocks C, D and E using the phase delay and advance signals. When the phase of the phase correction clock is delayed from the timing signal of the halftone clock by the switching of the clocks A and B by the clock switching signal, the phase of the phase correction clock is advanced by one period of the basic clock, and To
If it is advanced, it operates so as to delay the phase of the phase correction clock by one cycle. The time interval at which this switching (phase correction) is performed is such that the phase difference between the network clock timing signal and the phase correction clock generated within that time is equal to or less than the absolute value (for one cycle of the basic clock) that can be phase corrected. It is decided as follows. This can be easily realized by designing a loop filter in consideration of the maximum value of the jitter of the AMI signal, the frequency deviation of the basic clock, and the definition of the bit pattern of the AMI signal.

It can be easily inferred from the operation explanatory diagram of the second switch circuit in FIG. 7 that the clock C, the clock D, and the clock E can be switched almost similarly to the case of the clock A and the clock B.

The phase correction by switching between the clocks A and B and the switching of the clocks C, D and E with respect to the phase lag and advance is completely equivalent since the phase correction values are the same (± 1/6 MHz). Therefore, it is possible to use the clock switching signal for switching between the clock C, the clock D, and the clock E.

By adopting the above configuration, a 2 MHz clock frequency-synchronized with the network can be obtained without causing loss of synchronization. In addition, a 3 MHz clock which is frequency-synchronized with the network which is an output signal of the first switch circuit 3 can be generated at the same time, and by dividing the two clocks, various networks required for protocol processing and B-channel processing can be generated. A clock which is frequency-synchronized with the above can be created with a digital circuit configuration.

[0020]

As is apparent from the above description, according to the clock generation circuit of the present invention, in the terminal which can be connected to the basic interface of the ISDN, the clock required mainly for the B channel processing can be easily and mainly used. It can be realized by a digital circuit. Of course, it is also possible to create a clock required for the layer 1 processing by dividing the clock output from the phase correction clock creating circuit at the same time.

By using this circuit, a terminal that can connect to the basic interface of ISDN
Almost all clocks required for processing can be created by a digital circuit, thereby further enhancing the integration of functions.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example in which the above embodiment is applied to a terminal;

FIG. 3 is an explanatory diagram of an operation of a first frequency divider in the embodiment.

FIG. 4 is an operation explanatory diagram of a second frequency divider circuit in the embodiment.

FIG. 5 is an explanatory diagram of an operation of the first switch circuit in the embodiment.

FIG. 6 is an explanatory diagram of an operation of the timing signal generation circuit in the embodiment.

FIG. 7 is an explanatory diagram of the operation of the second switch circuit in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st frequency divider circuit 2 ... 2nd frequency divider circuit 3 ... 1st switch circuit 4 ... Phase correction clock creation circuit 5 ... Timing signal creation circuit 6 ... Phase comparison circuit 7 ... Clock switching signal creation Circuit 8 Second switch circuit 9 Third frequency divider 10 Clock generation circuit 11 Fourth frequency divider 12 B channel processing unit 13 Protocol processing unit

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-58-46743 (JP, A) JP-A-62-56041 (JP, A) JP-A-2-65541 (JP, A) JP-A-5-654 308336 (JP, A) JP-A-4-319829 (JP, A)

Claims (1)

(57) [Claims] 1. m is an integer sufficiently larger than 1, and n = 2
m is a basic clock having a frequency which is n times the ideal data transfer rate of the layer 1 signal at the basic interface of the integrated digital service network. A first frequency divider circuit for generating clocks A and B of different types; and three types of clocks C and D having the same frequency as the basic clock and different in phase by 1/3 cycle. And a second frequency divider circuit for generating a clock E; a first switch circuit for switching and outputting the clock A and the clock B by an external control signal; and an output of the first switch circuit. A phase correction clock generation circuit for generating a phase correction clock obtained by dividing a signal to a frequency of 1 / m; and a layer 1 signal including jitter, A timing signal generating circuit for generating a timing signal of the network clock; a phase comparing circuit for comparing the phases of the phase correction clock and the timing signal of the network clock to generate a phase delay signal or a phase advance signal; A clock switching signal generation circuit for generating a clock switching signal for correcting a phase using a phase delay signal or a phase advance signal; and switching and outputting the clocks C, D and E by an external control signal And a third frequency divider for dividing the output signal of the second switch circuit. The control signal of the first switch circuit and the second A clock generation circuit using the clock switching signal as a control signal of a switch circuit.