JP2642375B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: Object of the Invention (Industrial Application Field) The present invention relates to a bipolar semiconductor integrated circuit device, and is particularly used to reduce the influence of the operation of a parasitic transistor in a lateral direction. Is what is done.

(Prior Art) In general, in a bipolar semiconductor integrated circuit device, an N-type vapor growth layer (VG layer) is formed on a P-type semiconductor substrate (substrate), and a P-type An isolation region is formed to form an element region.
Then, a bipolar transistor is formed in this element region.

By the way, in the above configuration, the P-type isolation region (or substrate) is used as a base, and the N-type element regions (VG layers) on both sides of the isolation region are used.
Parasitic NPN with the collector and emitter respectively
A transistor is formed. When the VG layer is set lower than the substrate potential, the parasitic transistor operates, which adversely affects normal circuit operation. In ordinary ICs, such a state is considered not to occur in application. That is, the junction between the isolation region (substrate) corresponding to the base and the emitter of the parasitic transistor and the VG layer is not biased in the forward direction.

However, in an IC that drives a reactive load,
The back electromotive force generated after driving causes the collector region to become a negative voltage, and the junction between the isolation region and the VG layer is biased in the forward direction, causing a state in which this junction frequently conducts. For this reason, the VG layer corresponding to the collector of the parasitic transistor is affected by the current at the time of conduction, which has a bad influence on the normal circuit operation.

Conventionally, in order to prevent the influence of the operation of the parasitic transistor, the width of the isolation region corresponding to the base of the parasitic transistor is widened and the current transmission α of the parasitic transistor characteristic is reduced. However, such a method has a drawback that the integration density is lowered and the cost is increased, and the effect is not sufficient and the application range of the IC is narrowed. In particular, in a circuit configuration in which amplification is performed in the next stage of the element affected by the parasitic transistor, even if the current transmission α is reduced, the amplification is performed in the next stage, so the effect of the parasitic transistor is ignored. It cannot be reduced sufficiently to the extent possible.

(Problems to be Solved by the Invention) As described above, in the IC having the PN isolation structure,
The formation of a lateral parasitic NPN transistor is unavoidable, and in order to avoid the effect of this parasitic transistor, the effect must be reduced sufficiently even though the current transfer of the parasitic transistor is set low. Was difficult.

Accordingly, it is an object of the present invention to provide an excellent semiconductor integrated circuit device capable of sufficiently reducing the influence of a parasitic transistor regardless of the circuit configuration of the next stage without lowering the integration density. It is.

[Configuration of the Invention] (Means and Actions for Solving the Problems) That is, in the present invention, in a semiconductor integrated circuit device having a PN isolation structure and driving a reactive load, the operation of a lateral parasitic NPN transistor is performed. Adjacent to the first element region that does not want to be affected by
A second element region having the same pattern area as that of the first element region and similarly affected by the parasitic NPN transistor in the lateral direction is provided, and the pattern of one PNP transistor is divided into two in the second element region. And a mirror circuit configured to supply a current corresponding to a current flowing out due to the influence of the lateral parasitic NPN transistor from the mirror circuit to the first element region. .

With this configuration, a current is supplied from the mirror circuit (the second element region) to the element region by the amount of the current flowing out of the first element region due to the operation of the lateral parasitic NPN transistor. The first element region is the same as the one where there is no relatively outflow of current, and the
The adverse effect due to the operation of the NPN transistor can be reduced.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, reference numeral 11 denotes a VG layer (parasitic source) in which the potential of the collector region is biased to a negative voltage by the operation of a lateral parasitic NPN transistor. Source 12 is considered connected. A VG layer (first element region) 14 separated by a P-type isolation region 13 is disposed adjacent to the VG layer 11, and the VG layer 14 is a VG layer serving as the parasitic source.
An element that does not want to be affected by 11 is formed. Also, the VG layer 11 is affected by the VG layer 11 similarly to the VG layer 14 so that the P-type isolation region 13
And a VG layer (second element region) 15 having the same pattern area as the VG layer 14 is arranged. The VG layer 15 is separated from the VG layer 14 by a P-type isolation region 16. VG above
In the layer 15, a mirror circuit composed of PNP transistors T ₁ and T ₂ is formed. The emitters of the transistors T ₁ and T ₂ are commonly connected and connected to power supply means, for example, Vcc, and the bases are commonly connected. The above transistor T ₁
The collector is connected to the VG layer 14 of the element do not want to affect the parasitic transistor, the collector of the transistor T ₂ is connected to the base common connection point of the transistors T _1, T _2. Thus, the input side of the mirror circuit has not been a circuit connection, is adapted to operate by receiving only the parasitic current I ₂ generated by the operation of the parasitic transistor.

In such a configuration, the VG layer 14 has V.
Affected by G layer 11, the parasitic current I ₁ flows, VG layer 15 forming a mirror circuit even under the same influence the parasitic current I ₁
When substantially the same parasitic current I ₂ flows. Thereby, the VG mirror circuit is operated from the collector of the transistors T ₁
Layer 14 is supplied with a mirror-inverted current I ₂ ′. Since the parasitic current I ₁ is equal to I _2, a and I ₂ = I ₂ ', VG
A current I ₂ ′ is supplied to the layer 14 from the mirror circuit by an amount corresponding to the current flowing out of the parasitic current I ₁ . Therefore,
It can be considered that the circuit is not affected by the parasitic current, and the influence of the parasitic transistor can be sufficiently reduced.

FIG. 2 shows an example of the pattern configuration of the mirror circuit. N-type VG surrounded by P-type isolation region
The layer 15 serves as a common base region for the _two transistors T ₁ and T ₂ . In the base region 15, collector regions 17-1 and 17-2 made of P-type impurity regions are formed. The collector region 17-2 is connected to the base region 15, and the collector region 17-1 is connected to the adjacent VG layer 14. In the base region 15 between the collector regions 17-1 and 17-2, P ⁺
An emitter region 18 formed of a type impurity region is formed, and this emitter region 18 is connected to a power supply Vcc.

As described above, the pattern configuration in FIG. 2 is a configuration in which the pattern of one normally used PNP transistor is divided into two. The VG layer 14 is activated by the parasitic current I ₂ flowing out of the base region 15 and the current I ₂
The same current I ₂ ′.

According to such a configuration, the current I ₂ ′ corresponding to the current flowing out by the parasitic current I ₁ is supplied from the mirror circuit to the VG layer 14 that is not likely to be affected by the parasitic transistor. it can be regarded as those that did not receive the influence of the I _1. Therefore, VG due to the operation of the parasitic transistor
The adverse effect on the layer 14 can be sufficiently reduced. In addition, since it is not necessary to set the width of the isolation region wide, the integration density does not decrease and the cost does not increase.
Further, even in a configuration in which amplification is performed in the next-stage circuit, there is no adverse effect due to the operation of the parasitic transistor.

[Effects of the Invention] As described above, according to the present invention, an excellent semiconductor integrated circuit that can sufficiently reduce the influence of a parasitic transistor even if the next stage has any circuit configuration without lowering the integration density. A device is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a pattern plan view showing an example of a pattern configuration of the mirror circuit in FIG. 11… VG layer (parasitic source), 12… Current source, 13,16…
Isolation region, 14 VG layer (first element region), 15 VG layer (second element region), I ₁ , T _2, parasitic current, T ₁ , T _2, PNP transistor.

Claims (1)

(57) [Claims] In a semiconductor integrated circuit device having a PN isolation structure and driving a reactance load, a semiconductor device which is not affected by the operation of a lateral parasitic NPN transistor is adjacent to a first element region. A second element region having the same pattern area as one element region and similarly affected by a lateral parasitic NPN transistor is provided.
A mirror circuit is formed by dividing the pattern of one PNP transistor into two in the element region of
A semiconductor integrated circuit device, wherein a current corresponding to a current flowing under the influence of an NPN transistor is supplied from the mirror circuit to the first element region.