JP2642377B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to a semiconductor integrated circuit designed by a master slice method, a standard cell method, and the like, and particularly to an improvement of a clock wiring method. Semiconductor integrated circuit device and a method of manufacturing the same.

(Prior Art) In recent years, as the scale of integrated circuits has increased, it has become necessary to pay careful attention to the design of clock systems. In a large-scale integrated circuit, many gates and flip-flops operate in synchronization with one clock signal. Therefore, a clock signal line is laid on the chip, and a number of fan-outs are connected to the clock signal line. At this time, the following two problems occur.

To drive a clock signal with a large load,
A clock driver having an extremely large current driving capability is required.

Clock skew occurs, causing an error in the timing operation of the integrated circuit.

Here, when one clock driver having a large current driving capability is provided in an integrated circuit, a large current change occurs in the clock driver portion, local switching noise occurs, a power supply potential fluctuates, and a large amount of substrate is generated. Electric current flows. As a result, malfunction of the integrated circuit may occur,
In a CMOS integrated circuit or the like, destruction due to latch-up may occur. Also, no matter how much the clock driver having a large driving capability is used, the effect of reducing the clock skew cannot be expected because the impedance itself of the transmission wiring path becomes high.

In order to solve such a problem, instead of supplying a clock signal to all flip-flops F in an integrated circuit by one clock driver D as shown in FIG. 11 (a),
As shown in FIG. 2B, the clock drivers are distributed,
Method for supplying a clock signal to the flip-flop Fi1~Fin addressed in a plurality of clock drivers D ₁ to D _N for decentralized had been taken conventionally. With this method, the problem caused by the above is solved in principle.

In the layout method of automatically arranging cells by the poly-cell method and the master slice method and automatically wiring between cells, as an example of implementing the above-described clock driver decentralization method, conventionally, for example, FIG. 12 and FIG. Such a method is adopted. In these two figures, 1 is a system clock driver, 2 is a clock driver cell, 3 is a clock signal line, and F is a flip-flop. Also,
The x mark of the clock driver cell 2 indicates a clock signal input terminal, and the circle mark indicates a clock signal output terminal.

The clock signal distribution method described above is mainly intended to reduce the resistance component of the clock line.
This purpose can be further enhanced by increasing the line width of the clock signal line, such as the horizontal line, the vertical line, or the periphery, and the processing can be easily performed by an automatic wiring program.
In such a clock distribution method, since the wiring resistance component between the system clock driver cell and each clock driver cell is reduced, skew is almost eliminated when observed at the input end of each clock driver cell. However, because the number of flip-flops connected to each driver, that is, the load is not always uniform,
A skew occurs in the clock signal supplied to each flip-flop.

In other words, simply arranging the clock drivers in a decentralized manner will cause clock skew due to variations in the load on the individual clock drivers when laying out with the automatic placement and wiring program, resulting in malfunctions such as incorrect data propagation. Occurs. To avoid this, in the automatic placement program, the placement processing must be performed under the constraint that the number of flip-flops connected to each clock driver cell is equal. Is not only very complicated, but also the performance of the placement program is degraded due to this constraint.

(Problems to be Solved by the Invention) As described above, the conventional method of dividing the system clock signal by using the plurality of clock driver cells and automatically laying out the system clock signal is based on the difference in the capacitive load component of each clock driver cell. There is a problem that clock skew occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device which can perform good clock distribution without deteriorating the performance of an automatic placement / wiring program and has no clock skew. An object of the present invention is to provide an integrated circuit device and a method for manufacturing the same.

[Configuration of the Invention] (Means for Solving the Problems) The gist of the present invention is to connect a virtual load to each of the plurality of clock drivers so that the load capacities of the clock drivers are uniform.

That is, the present invention provides a semiconductor integrated circuit device which supplies a system clock signal to a plurality of clock drivers, and supplies a clock signal from each clock driver to a main cell such as a flip-flop. A plurality of clock drivers to which a system clock signal is supplied; a main cell connected to at least one of these drivers, to which a clock signal is supplied from a corresponding clock driver; The driver is provided with field through cells connected in accordance with the number of main cells connected to the driver, and the number of connected field through cells is determined so that the load of each clock driver is equalized.

Further, according to the present invention, in the method of manufacturing a semiconductor integrated circuit device, a feed-through cell having a predetermined capacitance load is inserted at the time of automatic placement / wiring processing of the main cell, and the main cell in a region assigned to each clock driver is inserted. According to this method, the number of feedthrough cells to be connected to the clock driver is determined according to the number.

(Operation) According to the present invention, the capacity load of each clock driver can be made substantially equal by using a feed-through cell automatically inserted by automatic arrangement or schematic wiring as a load circuit of the clock driver. Therefore,
The clock skew in the semiconductor integrated circuit can be eliminated without inserting a new load cell and lowering the integration degree of the entire chip.

(Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples.

FIG. 1 is a diagram for explaining a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention, and is a diagram showing a state of clock wiring. In the figure, reference numeral 11 denotes a system clock generating driver cell, 12 denotes a clock signal line, F denotes a main cell that requires a clock signal such as a flip-flop, D (Di1 to DiN) denotes a clock driver cell, and 13 denotes a circle. Is the output terminal of the clock driver cell, indicated by a cross 14
Is an input terminal of the clock driver cell, C (Ci1 to CiN) is a clock signal line divided by the clock driver cell, and T is a feed-through cell with a load.

In the clock distribution system shown in FIG. 1, as shown in FIG. 8B, the load of each clock driver D is made equal by the use of the feedthrough cell T,
Clock skew is reduced.

Next, a specific procedure for realizing the configuration of FIG. 1 will be described. FIG. 2 is a flowchart showing one procedure for realizing the clock distribution system according to the standard cell system.

In step S1, the feed-through cell T is inserted at a position where the wiring efficiency is increased due to the arrangement of the main cell F and the net that passes through the cell column when the general signal line is roughly wired. An example of the feed-through cell T is shown in FIG. In the figure, 31 indicates a power supply line or ground line of the first metal layer, 32 indicates a polysilicon film, and 33 indicates a diffusion layer. This through cell T can be used without considering clock wiring.
Insert them in consideration of optimization of placement and wiring. In this step, the clock driver cells D are arranged so as to be arranged on the same straight line and in each cell column. The through cell T is formed simultaneously with the formation of the main cell F, and has substantially the same load capacity as the main cell F. In step S2, it is determined to which clock driver cell D flip-flops (main cells) F on the same cell row, which are arranged around each clock driver cell D, are connected. A region near the clock driver cell Di to be connected to the clock driver cell Di is represented by Ri. For example, as shown in FIG. 4, when two clock driver cells D (D _{1 to} D ₈ ) are inserted in each cell row, a region Ri for each clock driver cell Di is defined as:
The distribution is determined as shown in FIG. 5 in consideration of the distribution of flip-flops and the distribution of through cells. The flip-flop in the region Ri is connected to the clock driver cell Di. In the case of FIG. 1, the regions Ri1 to RiN are determined for the clock driver cells Di1 to DiN as shown in FIG.

Next, in step S3, a region (Rj) in which the number of flip-flops included in each region is the maximum is found, and the maximum number is set to M. The load of the clock driver cell Dj (the load for M flip-flops) in this region is maximized. In step S4, the insufficient load is used as a load cell by using a feed-through cell arranged in the region Ri so that the load of each of the other clock driver cells Di becomes M flip-flops. Generates a net Ci for connecting the clock signal to the feedthrough cell.

Through the above steps, the load of each clock driver cell can be made substantially uniform by using the inserted feed-through cell as a load. The reason is that in a large-scale integrated circuit, a large number of feedthrough cells are inserted, and these cells are distributed throughout the chip without being localized.

Although the height of the flip-flop cell is large, a load of about one feed-through cell can be used instead.

by.

In step S4, when the load of each clock driver cell cannot be equalized, the Ri of the region in charge of each clock driver cell is changed, or the feed is supplied to the region where the feedthrough cell used as the load is insufficient. By adding a new through cell, etc.
S5) The processes of steps S3 and S4 are executed again to equalize the load of all clock drivers.

In step S6, the input terminals of the clock driver cells arranged on the same straight line are connected to the output terminals of the system clock driver. These wirings can be performed in a straight line, and can be easily processed by an automatic wiring program. Therefore, by increasing the line width, it is possible to reduce clock skew between clock driver cells due to wiring resistance. Become.

The wiring in step S7 is vertically
The wiring is basically based on the use of the second metal layer in the horizontal direction. However, the clock signal wiring is subjected to wiring processing as shown in FIG. In the figure, reference numeral 71 denotes a metal second layer connecting clock driver cells, reference numerals 72 to 74 denote clock signals Cj supplied from the clock driver cell Dj, reference numeral 72 denotes a metal first layer, reference numeral 73 denotes a metal second layer, 74 is respectively wired with polysilicon. Reference numeral 75 denotes a via, and reference numeral 76 denotes a contact. With such a wiring method, the feed-through cell T allows a through wiring of the metal second layer, and the function as the feed-through cell is not lost.

Thus, according to the present embodiment, although the load of each clock driver cell becomes uneven as shown in FIG. 8A, the load of the clock driver cell is changed by the load feed-through cell as shown in FIG. 8B. Are equalized, and clock skew is reduced. Moreover, unlike the method of newly inserting a load dummy cell, it is extremely effective for the standard cell method without reducing the degree of integration and utility.

Next, a second embodiment of the present invention will be described. This embodiment relates to a master slice semiconductor integrated circuit device.

In the case of a master slice semiconductor integrated circuit, since the length of the gate row is determined, care must be taken in inserting through cells. However, when laying out a large-scale integrated circuit, the gate usage rate is about 70 to 85%. Therefore, a region of 15 to 30% of all the basic gates is not used as an element, but this region can be used as a feed-through cell. There are enough feedthrough cells that can be placed,
It can be freely inserted as long as it does not exceed the length of the gate row. The basic processing procedure is the same as the flowchart shown in FIG.

In order to implement the present invention in a master slice semiconductor integrated circuit, a cell as shown in FIG. 9, for example, may be inserted as a feed-through cell. The metal wiring as the cell pattern is a wiring connecting the power supply line 91 and the gates 94, and uses the first metal layer. 92 is a polysilicon gate, 93 is a diffusion layer, and these have already been processed as a master slice.

When personalizing a master slice, it is assumed that only the first metal layer and the second metal layer can be used. The first metal layer is used in the direction parallel to the cell row, the second metal layer is used in the direction perpendicular to the cell row, and the through wiring is performed in the second metal layer on the cell row. The clock signal wiring performed in step S7 is subjected to wiring processing as shown in FIG. 10, and the feedthrough cell is connected as a load. In the figure, reference numeral 101 denotes a second metal layer for connecting clock driver cells, and 102 to 104.
Is the clock signal supplied from the clock driver cell Dj
Cj, 102 is the first metal layer, 103 is the second metal layer, 10
4 is a first metal layer for wiring. Reference numeral 105 denotes a via. The segment 102 parallel to the cell row is assigned to the track closest to the cell row. The reason is,
This is to prevent the segment 104 from being short-circuited with other vertical signal lines of the metal first layer due to the exceptional wiring of the metal first layer.

With the above wiring method, the feed-through cell T can be a metal second-layer through wiring, and the function as the feed-through cell is not lost. Therefore, the load of the clock driver using the feed-through cell can be equalized, and the same effect as in the previous embodiment can be obtained.

Note that the present invention is not limited to the above-described embodiments. For example, the main cell is not limited to a flip-flop, but can be applied to various cells that require a clock signal. Further, the configuration of the feed-through cell is not limited to those shown in FIGS. 3 and 9 and can be appropriately changed according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

[Effects of the Invention] As described above, according to the present invention, a load dummy cell is newly inserted in order to insert a feedthrough cell in consideration of optimization of arrangement and wiring and to make the load of a clock driver equal. The clock skew can be reduced without reducing the degree of integration or utility.

[Brief description of the drawings]

1 to 8 are diagrams for explaining one embodiment of the present invention. FIG. 1 is a diagram showing a clock wiring state in a semiconductor integrated circuit device, and FIG. 2 is a diagram showing a procedure for realizing the above device. FIG. 3 is a diagram showing an example of a feed-through cell with a capacitive load, FIG. 4 is a diagram showing an example of arrangement of clock driver cells arranged in a distributed manner, and FIG. 5 is a sharing area of each clock driver cell. FIG.
FIG. 7 is a diagram showing a sharing area of each clock driver cell in obtaining the configuration of FIG. 1, FIG. 7 is a diagram showing a wiring scheme of divided clock signal lines, and FIG. 9 to 10 are diagrams for explaining another embodiment of the present invention. FIG. 9 is a diagram showing an example of a feed-through cell with a capacitive load in a master slice system. FIG. 11 is a diagram showing a clock signal wiring method in the case of the above feedthrough cell insertion, and FIGS. 11 to 13 are for explaining a conventional problem.
FIG. 11 is a diagram showing a method of supplying a system clock signal to a flip-flop, and FIGS. 12 and 13 are diagrams showing a clock wiring state in a conventional example. 11: System clock generation driver cell, 12: Clock signal line, 13: Output terminal, 14: Input terminal, 31, 91
...... Power supply lines, 32, 92 ... Polysilicon film, 33, 93 ... Diffusion layer, 71, 73, 101, 103 ... Metal second layer, 72, 102, 104 ...
Metal first layer, 74: polysilicon film, 75, 105: via, 76: contact, F: flip-flop (main cell), D: clock driver cell, T: feed-through cell.

Claims (4)

(57) [Claims] 1. A plurality of clock drivers, which are distributed on a semiconductor chip and are supplied with a system clock signal, and each of the clock drivers has at least one clock driver.
Connected, a main cell to which a clock signal is supplied from a corresponding clock driver, and a predetermined load capacity,
The clock driver includes a field-through cell in which main cells of the driver are connected according to the number of connected cells, and the number of connected field-through cells is determined so that the load of each clock driver is equalized. A semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein said feed-through cell is inserted during automatic placement and wiring of said main cell. 3. A method of manufacturing a semiconductor integrated circuit device for supplying a system clock signal to distributed clock drivers and supplying a clock signal from the driver to a main cell, the field-through circuit having a predetermined capacitive load. Insert cells during automatic placement and routing of the main cell,
A method of manufacturing a semiconductor integrated circuit device, wherein the number of feedthrough cells to be connected to the clock driver is determined according to the number of main cells in an area assigned to each clock driver. 4. The method according to claim 1, wherein when the number of feedthrough cells to be connected to said clock driver is insufficient, an area assigned to said clock driver is changed, or another feedthrough cell is inserted in an insufficient area. The method for manufacturing a semiconductor integrated circuit device according to claim 3.