JP2643095B2 - MOSFET element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to MOSFET devices, and more particularly to MOSFET devices that can be used in high power applications with a relatively high reverse voltage and very low on-resistance.

[0002]

2. Description of the Related Art A major feature of a bipolar transistor with respect to a MOSFET is that the bipolar transistor has a very low resistance during conduction per unit conductive region. M
OSFETs have a number of advantages over bipolar transistors: very fast switching speeds,
Very high gain and the absence of secondary breakdown characteristics represented by minority carrier elements. However, MOSFE
Since T has a high on-resistance, its use in high power switching applications is limited.

[0003]

It has a low forward resistance that can be used for high power switching applications of MOSFETs that could not be solved by the prior art and retains all of the many advantages over bipolar transistors. High-power MOSFETs more competitive with bipolar transistors in as-switched applications
Providing the device, in particular, the forward resistance per unit area of the device is reduced by half compared to the conventional limited resistance per unit region of the MOSFET device, and the M is suitable for high power.
It is an object of the present invention to provide an OSFET device.

[0004]

The specific means for solving the above-mentioned problems have the following construction as described in the claims.

In other words, it has a first surface and a second surface parallel to the first surface, has a main body of the first conductivity type, and the surface of the main body is the first surface. A semiconductor material wafer having a second conductivity type opposite to the first conductivity type, and symmetrically spaced from the first surface of the wafer in the main body portion. Extending from the first surface to the second surface between the base region having the polygonal shape formed and the base region adjacent to each other.
A common conductive region having a conductivity corresponding to a dose of phosphorus atoms of from × 10 ^{12 to} 1 × 10 ¹⁴ atoms / cm ² , and from the first surface inside the periphery of the first surface of the base region. A source region having a polygonal ring shape made of a material having the first conductivity type, disposed in the base region, formed between an outer peripheral edge of the source region and the peripheral edge of the base region; A channel region in which the channel of the first conductivity type is formed, a gate insulating layer extending over the common conductive region and the channel region on the first surface, and a gate electrode formed on the gate insulating layer And a source electrode connected to each of the source regions and their base regions; and a drain electrode coupled to the common conductive region.

[0006]

In MOSFET device of the operation and effect of the present invention, it said common conductive region extends from the first surface of the wafer toward the second surface at between the base region adjacent to each other, 1 × 10 ¹² It has a conductivity corresponding to a dose of about 1 × 10 ¹⁴ atoms / cm ² of phosphorus atoms.

Since the common conductive region has the above-described conductivity, the common conductive region is formed to have high conductivity n ( ⁺ ), and the resistance of the MOSFET element when conducting is reduced. Further, due to the high conductivity n ( ⁺ ), a depletion layer formed by the junction between the main body portion of the wafer having the first conductivity type and the base region having the second conductivity type opposite to the first conductivity type is formed. Spreading in the common conductive region is suppressed. Thus, the current flowing through the common conductive region can relatively flow in the common conductive region without being hindered by the depletion layer.

[0008] This reduces the resistance during conduction per unit area of the MOSFET element by half. In addition, the geometrical arrangement of the base region and the source region in the form of a polygon,
The high packing density created by this compartmentalized structure
In order to create a larger channel width per unit area than any of the previously known geometries of OSFETs, it is possible to improve the packing of the device on the chip surface and to lower the forward resistance of the device. .

The resulting MOS transistor of the present invention
FET devices have become comparable to conventional high power bipolar transistor devices. It is the MO of the present invention.
This is because while the SFET device retains all of the advantages of the MOSFET device over the bipolar device, it can also have a considerably lower forward resistance, which is the main advantage of the bipolar device.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, FIGS. 1 and 2 showing a reference example of a MOSFET device related to the present invention will be described. These figures show a silicon single crystal chip 20 (or some other suitable material) with device electrodes with serpentine passages 21 best shown in FIG. 1 to increase the current passage area of the device. ing. Note that the passage 21 may have another geometric shape. The device shown is approximately 400
Devices having a reverse voltage of 90 V to 400 V with a reverse voltage of V and a conduction resistance of less than about 0.4 Ω with a channel width of 50 cm were formed. 400V element is 30A
Pulse current. The 90V device has a forward conduction resistance of about 0.1Ω with a channel length of 50 cm, and a resistance of about 10Ω.
A pulse current of up to 0 A flows. By changing the channel width, a high voltage or constant voltage element is formed.

Currently known MOSFET devices have a higher on-resistance than those described above. For example, a 40 formed by the prior art that can be compared to that described below.
OVMOSFETs have a conduction resistance of greater than about 1.5Ω, while the conduction resistance of devices formed according to the present invention is less than about 0.4Ω. Furthermore, the MOSFET of the present invention as a high power switching device has all of the advantages desired for a MOSFET device since it operates as a majority carrier device. These advantages include high switching speed, high gain, and elimination of secondary breakdown characteristics present in minority carrier devices.

The device shown in FIG. 1 and FIG.
It has two source electrodes 22 and 23 divided by 4 and a metal gate electrode 24 is fixed to the surface of the semiconductor device by a silicon dioxide layer 25 but is separated therefrom. The tortuous path of the gate oxide 24 has a total length of 50 cm and has a number of 667 undulations, but is simplified in FIG. Other channel widths may be used. Source electrodes 22 and 23
Extends as shown and acts as an electric field plate to facilitate the expansion of the depletion region formed under reverse voltage conditions. Each of the source electrodes 22 and 23 supplies current to a common drain electrode 26 fixed to the bottom of the wafer. The relative dimensions, especially the thickness, of the device have been greatly enlarged in FIG. 2 for convenience of explanation. The silicon chip or wafer 20 is formed on an n ( ⁺ ) substrate having a thickness of about 0.36 mm. The n ( ^- ) epitaxial layer is provided on the chip (substrate) 20, and has a thickness and a resistivity according to a desired reverse voltage. All junctions formed in this epitaxial layer have a rather high resistivity. In the illustrated embodiment, the epitaxial layer has a thickness of about 35 microns and a resistivity of about 20 ohm-cm. For a 90V device, the epitaxial layer 20
Has a resistivity of about 2.5 Ω-cm at a thickness of 10 microns. A channel width of 50 cm is also used to provide the device with the desired current carrying capacity.

In the MOSFET device shown in FIGS. 1 and 2, there is an elongated serpentine p ( ⁺ ) region below each of the source electrodes 22 and 23, which surrounds the serpentine path shown in FIG. Extend to. These p ( ⁺ ) conductive regions are shown in FIG. 2 as p ( ⁺ ) regions 30, 31, respectively, and the maximum p ( ⁺ ) region depth is greatly exaggerated to form large diameter curvatures. It is similar to those of the prior art except that This allows the device to withstand higher reverse voltages. For example, region 3
The depth of 0 and 31 is about 4 microns at dimension x in FIG.
Is preferably about 3 microns in dimension y.

By using the D-MOS manufacturing technology,
Two n ( ⁺ ) regions 32 and 33 are formed below source electrodes 22 and 23, respectively, and together with p ( ⁺ ) regions 30 and 31, define n-type channel regions 34 and 35, respectively. Channel regions 34 and 35 are located below the gate oxide 25 and conduct from the sources 22 and 23 through the inversion layers 34 and 35 to the central region 40 located below the gate 24 and then to the drain electrode 26. It can be reversed by applying a suitable bias signal to gate 24 to do so. Channels 34 and 35 have a length of about 1 micron.

According to conventional thinking, channels 34 and 3
5 (and between p ( ⁺ ) regions 30 and 31)
The ( ^- ) region was said to have a high resistivity for the device to withstand high reverse voltages. However, the relatively high resistivity n ( ^- ) material is also a significant factor in increasing the forward conduction resistance of the device.

In accordance with a feature of the present invention, a significant portion of this common conductive region comprises an n ( ⁺ ) region 40 which is formed to be fairly highly conductive and is located immediately below the gate oxide 25. The n ( ⁺ ) region 40 is about 4 microns deep, but may be about 3 microns to about 6 microns deep. Its exact conductivity is unknown but varies with depth, and is a higher conductivity compared to the lower n ( ^- ) region. In particular, the n ( ⁺ ) region 40 has a temperature of 1150 ° C. to 1250 ° C. and a diffusion condition of 30 minutes to 240 minutes and a concentration of 1 × 10 ^{12 to} 1 × 10 ¹⁴ phosphorus atoms / 50 KV.
It has high conductivity determined by the total ion implantation dose of cm ² . It has been found that by making this region 40 a fairly highly conductive n ( ⁺ ) material by diffusion or other operations, the device characteristics are significantly improved and the forward conduction resistance of the device is halved. Further, it has been found that the provision of the n ( ⁺ ) region 40 having high conductivity does not impair the reverse voltage characteristics of the MOSFET element. Therefore, the gate oxide 2
5, the region 40 between the channels 34 and 35 is made more conductive, so that the forward conduction resistance of the intended high-power switching element is significantly reduced and the MOSF
ET devices surpass equivalent junction devices while retaining all of the benefits of MOSFET majority carrier operation.

In the above description of FIGS. 1 and 2, the conductive channels 34 and 35 are p ( ⁺ ) materials, so that, by applying an appropriate gate voltage,
It can be seen that the sources 22 and 23 are inverted to n-type conductivity to provide a multiple carrier conductive channel to the central region 40. However, obviously, all of these conductivity types may be reversed, as described above, such that the device can act as a p-channel device rather than as an n-channel device.

FIGS. 3 to 6 show one method of constructing the device shown in FIGS. 1 and 2 as a reference example. According to FIG. 3, the base wafer 20 is shown as an n ( ⁺ ) material having an n ( ^- ) epitaxial layer on top. A thick oxide layer 50 is formed on the wafer 20, where windows 51 and 52 are provided. These windows 51 and 52 are p (
⁺ ) Exposed to a boron atom beam in an ion implanter to form a region; The implanted boron atoms then
It is diffused deep into the wafer to form a semi-circular p ( ⁺ ) concentration region as shown in FIG. 3 having a depth of about 4 microns. During this diffusion operation, shallow oxide layers 53 and 54 grow on the windows 51 and 52.

Next, as shown in FIG. 4, windows 61 and 62 are cut in oxide layer 50, an n ( ⁺ ) implant is performed, and n ( ^- ) is implanted.
N ( ⁺ ) regions 63 and 64 are implanted into the epitaxial layer. This n ( ⁺ ) implantation is performed by a phosphorus beam. Then, the implanted region is moved to a diffusion step,
Working at 0 ° C. to 1250 ° C. for 30 minutes to 4 hours, the region 63 is at a concentration determined by the implantation dose of 1 × 10 ^{12 to} 1 × 10 ¹⁴ phosphorus atoms / cm ² until a depth of about 3.5 microns is reached. And 64 are expanded and deepened. As will be described later, regions 63 and 64 form a new n ( ⁺ ) region that reduces the on-resistance of the device.

The n ( ⁺ ) regions 63 and 64 may be provided epitaxially, if desired, and may not diffuse. Similarly, a device constructed as described above may be manufactured by any desired process apparent to those skilled in the art.

A particular step in the manufacturing method is the channel implantation and diffusion step shown in FIG. 5, where p ( ⁺ ) regions 71 and 72 are
( ⁺ ) Identical windows 61 and 62 used for injection
Is formed through. The p ( ⁺ ) regions 71 and 72 are 1
It is formed by implantation with a boron beam of about 5 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² with a diffusion process at 150 ° C. to 1250 ° C. for 30 minutes to 120 minutes.

Next, as shown in FIG. 6, a source pretreatment and a diffusion step of the source regions 32 and 33 are performed. This is accomplished by a conventional non-critical phosphorus diffusion step, in which diffusion occurs through windows 61 and 62 and source regions 32 and 33 are automatically relative to other preformed regions. Be aligned. Thus, the wafer is placed in a furnace and exposed to POCl ₃ in a carrier gas at 850 ° C. to 1000 ° C. for 10 to 50 minutes.

At the completion of this step, the basic junction structure required in FIG. 2 is formed below the oxide, which acts as a conductive channel for the device of interest. 35 and p (
^A filled n ( ⁺ ) region is formed in the portion between the ⁺ ) regions 30 and 31. The fabrication process continues from the process of FIG. 6 to the fabrication of the device shown in FIG. 2, where the oxide surface on the top of the chip is removed by a suitable method, and the metal patterns to be the source electrodes 22, 23 and gate electrode 24 are removed. Once formed, the electrodes to the device are completed. Then, the drain electrode 26 is provided on the device by the next metallization operation. Next, the entire device is coated with a suitable coating,
And 23 and the gate electrode 24 are connected to lead wires. This element is then mounted in a protective enclosure with any conductive support or drain electrode fixed to the enclosure that acts as a drain fitting.

In the MOSFET device shown in FIGS. 1 and 2, each of the source region, the gate region and the drain on the surface of the wafer opposite to the source electrode is formed in a meandering maze shape as shown in the figure. is there.
Such a shape may be another shape. For example, FIG.
As shown in FIG. 8 and FIG.
In this configuration, a simple rectangular configuration is formed in which the central source 82 is surrounded by a ring-shaped gate 80 and a ring-shaped first source electrode 81, and the outer periphery is formed in a planar shape surrounded by a drain electrode 85. . The element shown in FIG. 8 is included in a base wafer of p ( ^- ) silicon single crystal 83, and silicon single crystal 83 has buried n ( ⁺ ) region 84, and source 81 is formed by the presence of this region. The lateral resistance of the various current paths leading to the surrounding drain electrode 85 is reduced.

A ring-shaped n ( ⁺ ) region 86 is formed in the device as shown in FIG. 8 as a reference example. According to the present invention, the ring-shaped region 86 includes all junctions of the device. It has a significantly higher conductivity than the n ( ⁻ ) epitaxial region 87. The region 86 extends downwardly from a region immediately below the gate oxide 88, and ends of two conductive channels formed between a ring-shaped p ( ⁺ ) region 89 and a central p ( ⁺ ) region 91. Combine with The regions 89 and 91 are
Each is located below a ring-shaped source region 81 and a central source region 82.

FIG. 8 also shows that the outer periphery of the p ( ⁺ ) region 89 has a large diameter so that the element can withstand a high reverse voltage.

The n ( ⁺ ) region 95 in FIG. 8 is provided for making good contact with the drain electrode 85.
The drain electrode 85 is separated from the source 81 located inside by a considerable distance in the horizontal direction.
0 micron or more. Outside the drain electrode 85, a p ( ⁺ ) insulating diffusion portion 96 is provided to insulate the element from other elements on the same chip or wafer.

In the configuration of FIG. 8, the sources 81 and 82
Pass through the region 86 such that the current from the transistor passes through the epitaxial region 87. The current then flows laterally outward and further to the drain electrode 85. As in the embodiment of FIG. 2, the device resistance is greatly reduced by the highly conductive region 86.

In implementing the configuration of FIG. 8, it should be noted that any contact material can be used to form the source and gate electrodes. For example, aluminum can be used for the source electrode, and polysilicon material can be used for the conductive gate 80 of FIG. 8 or the conductive gate 24 of FIG.

A number of other geometries can be used for fabricating the devices of the present invention, one of which is a plurality of linear, parallel source elements and a gate disposed therebetween.

Although the source electrodes 22 and 23 have been described as separate electrodes connected to separate conductors in the above description, the source electrodes 22 and 23 are shown in FIG. Polysilicon layer 101 (in place of aluminum) provided on top of gate oxide 25. This gate electrode is covered by an oxide layer 102 and a conductive layer 103 connects the two sources 22 and 23 together to form a single source conductor insulated from the gate electrode 101. Connections to the gate electrode are made at any suitable edge of the wafer.

FIGS. 10 and 11 show the shape of the measurement curves showing that the forward resistance decreases when the MOSFET region 40 is configured as a highly conductive n ( ⁺ ). In FIG. 10, the device tested has a region 40 with n ( ^- ) resistivity of the epitaxial region. Thus, the forward resistance increases at different gate biases as shown in FIG.

The MOSFET whose region 40 has n ( ⁺ ) conductivity
In the device, the resistance during conduction decreases dramatically for all gate voltages before electron velocity saturation occurs, as shown in FIG.

The polygon configuration of the source region of the present invention is shown in FIG.
Or best shown in FIG.

FIGS. 14 and 15 show the element before the gate, source and drain electrodes are provided. The manufacturing method may be any type including the above-described method for optimally forming a junction and installing electrodes, such as a D-MOS manufacturing technique and an ion implantation technique.

Although the device of the present invention has been described as an n-channel enhancement type device, the present invention can be applied to a p-channel device and a depletion mode device.

In FIGS. 14 and 15, a hexagonal source region is formed in the base semiconductor body or wafer. The base semiconductor or wafer shown is shown as a silicon single crystal N-type wafer 120 provided with a thin N-epitaxial region 121 as shown in FIG.
All junctions are formed in the epitaxial region 121. 14 and 1 by using a suitable mask.
A plurality of P-type regions, such as five regions 122 and 123, are formed on one surface of semiconductor wafer region 121, and these regions are generally polygonal, preferably hexagonal in shape.

The above-mentioned polygonal area is formed in an extremely large number. For example, an element having a surface dimension of 2.54 mm × 3.556 mm forms about 6600 polygonal regions,
The total channel width is about 558.8 mm. The spacing between two opposing sides in each of the polygonal regions is about 0.0254 mm or less. In addition, the distance between the linear measuring portions of adjacent polygonal regions is about 0.015 mm. The above dimensions are one example.

The p ( ⁺ ) regions 122 and 123 have a depth d of about 5 microns, which is desirable for producing high and reliable electric field characteristics. Each of the p regions is a p region 122
And 123, respectively, having outer step regions shown as step regions 124 and 25, respectively, which are about 1.
It has a depth s of 5 microns. This distance should be as small as possible to reduce the capacitance of the device.

Each of the polygonal regions, including polygonal regions 122 and 123, receives N ⁺ polygonal ring regions 126 and 127, respectively. Steps 124 and 125 are located below regions 126 and 127, respectively. N ⁺ region 12
6 and 127 cooperate with the relatively conductive N ⁺ region 128. This region 128 is an N region disposed between adjacent p-type polygons, and defines various channels between a source region and a drain electrode described later.

The highly conductive N ⁺ region 128 is disclosed in US Pat.
376,286, and this region 128 is the subject of the patent and has the very low forward resistance characteristics of the device.

In FIGS. 14 and 15, the entire surface of the wafer is covered with oxide layers or combined conventional oxide and nitride layers, which are formed to form various junctions. You. This layer is shown as insulating layer 130. The insulating layer 130 has polygonal regions 122 and 12
A polygonal opening such as three directly above openings 131 and 132 is provided. Openings 131 and 132 partially overlap N ⁺ -type source rings 126 and 127 for regions 122 and 123, respectively. The insulating layer 130 as an oxide strip remaining after the formation of the polygonal opening becomes the gate oxide of the device.

Next, electrodes are provided as shown in FIG. These are polysilicon electrodes 140, 141, and 14 that overlap in a grid on the insulating layer (oxide portion) 130.
2.

Subsequently, a silicon dioxide film is provided on the polysilicon electrodes 140, 141, 142 of FIG. 16 with film portions 145, 146, 147, which comprise the polysilicon control electrode and subsequently the entire wafer. A source electrode and the like provided on the upper surface are insulated. In FIG. 16, the source electrode is shown as a conductive film 150 made of a desired material such as aluminum. Drain electrode 151
Is also provided on the element.

The device shown in FIG. 16 has an N-channel type in which a channel region is formed between each of the independent sources and the main body of the semiconductor material finally leading to the drain electrode 151. Element. Thus, the channel region 160 is formed between the source region 126 on the ring connected to the source electrode 150 and the N ⁺ region 128 leading to the drain electrode 151. Channel 160 is changed to N-type conductivity by applying an appropriate control voltage to gate 140. Similarly,
Channels 161 and 162 are formed between the source region 126 connected to the source electrode 150 and the surrounding N ⁺ region 128 leading to the drain electrode 151. When an appropriate control voltage is applied to the polysilicon gate electrode including the electrode 141 of FIG.
And 162 become conductive, allowing majority carrier conduction from source electrode 150 to drain electrode 151.

Each of the sources forms a parallel conductive path, for example, channels 163 and 1 below gate electrode 142.
64 enables conduction from the ring-shaped source region 127 and the N-type source region 170 to the N ⁺ region 128 and the drain electrode 151.

FIGS. 15 and 16 show a p-type end region 171 surrounding the edge of the wafer.

The electrode 150 in FIG. 16 is preferably an aluminum electrode. The contact region of the electrode 150 entirely covers and is aligned with the deeper depth of the p-type region 122. This is done because it has been found that the aluminum used for electrode 150 punches out very thin regions of the p-type material (spike through). Thus, one feature of the present invention is that the electrode 150 is
The point is that the deep portion of the p region such as 3 is mainly and surely covered. Accordingly, the active channel region formed by the steps 124 and 125 can be reduced in thickness to reduce the device capacitance.

FIG. 12 shows a MOSFET device which is completed using the polygonal source pattern shown in FIG. The device of FIG. 12 has four engraved areas 18
0,181,182,183. If the wafer is cut along these areas, the distance
A unit element having a size of mm × 0.3556 mm is cut out and separated.

The above-mentioned polygonal region is formed on one wafer in a plurality of rows and columns. For example, the range indicated by reference A is approximately 0.210 mm and includes 65 rows of polygons, and the range indicated by reference B is approximately 0.376 m
The polygonal region includes 100 rows of m polygons, and 82 rows of the polygonal region are formed in a range indicated by reference numeral C between the source connection pad 190 and the gate connection pad 191. The source pad 190 is made of heavy metal,
It is directly connected to the aluminum source electrode 150, and the conductor is connected.

The gate connection pad 191 is electrically connected to a plurality of fingers 192, 193, 194, and 195, which are formed symmetrically on the outer surface having the polygonal region, as shown in FIG. It is electrically connected to the polysilicon gate as described in the context.

In the final stage of the manufacturing process, the outer edge 2 of the device is
A ring-shaped deep P ⁺ diffusion portion 171 connected to electric field plate 201 shown in FIG. 12 is provided.

FIG. 13 shows a part of the gate pad 191 and the gate fingers 194 and 195 in cross section. To reduce the RC delay constant of the device, it is desirable to form a plurality of electrodes on the polysilicon gate. The polysilicon gate is provided in a plurality of regions 210, 211, 21.
2 having a number of regions, which extend outwardly,
Also, the extension of the gate pad and the gate finger 19
Accept 4 and 195. The polysilicon gate region is exposed during formation of the oxide films 145-146-147 of FIG. 16 and is not covered by the source electrode 50. In FIG. 13, the axis 220 is the symmetry axis 220 shown in FIG.

Although the present invention has been described in connection with a preferred embodiment, it will be apparent to those skilled in the art that many variations and modifications may be made. Therefore, the present invention should not be limited only to the description, drawings, and claims.

[Brief description of the drawings]

FIG. 1 is a plan view showing a reference example of a MOSFET device related to the present invention, particularly showing two source and gate metal patterns.

FIG. 2 is a sectional view taken along line 2-2 of FIG.

3 is a particular cross-sectional view similar to FIG. 2 showing the initial stages of the wafer fabrication in FIGS. 1 and 2 showing the implantation and diffusion process the P ⁺ contact.

FIG. 4 is an explanatory view of a second step in the manufacturing process showing an n ( ⁺ ) implantation and diffusion process.

FIG. 5 is an explanatory diagram of a manufacturing process of a channel implantation and diffusion process.

FIG. 6 illustrates the pre-deposition and diffusion steps of the source, which are performed prior to the final step in which the gate oxide is cut for the metallization step forming the device of FIG.

FIG. 7 is a plan view similar to FIG. 1;

FIG. 8 is a sectional view taken along line 8-8 in FIG. 7;

FIG. 9 is a sectional view similar to FIG. 2, showing another example of the source contact configuration.

10 is a forward current characteristic diagram of a device similar to the structure of FIG. 2 in which the region under the oxide is n ( ^- ) as a MOSFET device.

11 is a characteristic diagram of the same device as the structure of FIG. 2 in which the region 40 has a high n ( ⁺ ) conductivity.

FIG. 12 is a plan view of one MOSFET device formed on a wafer according to the present invention.

FIG. 13 is an enlarged detailed view of a gate pad showing a relationship between a gate electrode and a source region in the gate pad region.

FIG. 14 is a detailed plan view of a small portion of a source region at one stage of a device manufacturing process.

FIG. 15 is a sectional view taken in the direction of arrow 14-14 in FIG. 14;

FIG. 16 is a view similar to FIG. 15, in which a polysilicon gate, a source electrode, and a drain electrode are attached to a wafer.

[Explanation of symbols]

Reference Signs List 120 Wafer 121 Epitaxial region 122 P ( ⁺ ) region (base region) 123 p ( ⁺ ) region (base region) 126 Source region 127 Source region 128 N ⁺ region (common conductive region) 130 Gate oxide layer 140 Gate electrode 141 Gate Electrode 142 Gate electrode 150 Source electrode 151 Drain electrode 161 Channel 162 Channel

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Thomas Herman 1622 (72) Hyelin Drive, Redondo Beach, California, United States Inventor Vladimir Lumenic El Segundo Indiana Court, California, United States 717 (56) Reference Document JP-A-52-132684 (JP, A) JP-A-53-74385 (JP, A)

Claims (1)

(57) [Claims] A first body having a first surface, a second surface parallel to the first surface, and a main body of a first conductivity type;
A wafer of a semiconductor material having a surface of the main body part constituting the first surface, a second conductivity type opposite to the first conductivity type, and from the first surface of the wafer A base region having a polygonal shape symmetrically disposed in the main body portion and extending from the first surface to the second surface between base regions adjacent to each other; A common conductive region having a conductivity corresponding to a dose of ^{12 to} 1 × 10 ¹⁴ atoms / cm ² of phosphorus atoms; and a base region from the first surface inside the periphery of the first surface of the base region. A source region disposed in the region and having a polygonal ring shape made of the material having the first conductivity type; and a source region formed between an outer peripheral edge of the source region and the peripheral edge of the base region; A channel in which a channel of one conductivity type is formed A gate region formed on the common conductive region and the channel region on the first surface; a gate electrode formed on the gate insulating layer; each of the source regions and their base regions; A MOSFET device comprising: a connected source electrode; and a drain electrode coupled to the common conductive region.