JP2643776B2 - Arbiter device and arbiter method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbiter device and an arbiter method for a memory access request of a bus master (line control circuit), and more particularly to an arbiter in which a plurality of bus masters communicating with an external circuit share a single memory by memory access. An apparatus and an arbiter method.

[0002]

2. Description of the Related Art Conventionally, various arbiter devices have been proposed (for example, JP-A-2-44445 and JP-A-2-300955).

FIG. 2 shows a conventional arbiter for arbitrating memory access. The conventional arbiter device includes first to Nth (N is an integer of 2 or more) bus masters 201-1, 201-2,..., 201 communicating with an external circuit (not shown).
-N and the first to N-th bus masters 201-1 to 201-201
-N supplied from the memory access request signal BRQ1.
It has a priority arbitration circuit 202 that arbitrates BRQN and gives a memory access permission signal BAK (subscript omitted) to one bus master, and one memory 203 shared by memory access.

Next, the operation of the conventional arbiter will be described. Each bus master 201 (subscript omitted) is connected to an external circuit (not shown) to perform communication control. That is, when the bus master 201 receives data from the external circuit,
Data synchronized with the input clock CLK (subscript omitted) is taken in, and a memory access request signal is output to the priority arbitration circuit 202. Priority arbitration circuit 20
2 arbitrates a maximum of N memory access request signals and outputs only one memory access permission signal BAK to a certain bus master 20.
Give to 1. The bus master 201 to which the memory access permission signal BAK has been given sequentially writes the received data fetched from outside by the memory access into the shared memory 203.

At the time of transmission to an external circuit, the bus master 201 outputs a memory access request signal to the priority arbitration circuit 202. The priority arbitration circuit 202 arbitrates a maximum of N memory access request signals BRQ1 to BRQN and applies a unique memory access permission signal BAK to a certain bus master 201. Memory access permission signal BA
The bus master 201 given K receives the shared memory 203
From the memory by memory access, and reads the read data to an external circuit with an input clock CL.
Output in synchronization with K.

Here, the amount of data read and written in one memory access is a predetermined amount of data. For example, if the data to be transmitted / received is packet data, one direct memory access (DMA) transfer is performed for one packet of transmitted / received data.

[0007]

In the above-described conventional arbiter, the memory access request signal output from each bus master 201 is equally input to the priority arbitration circuit 202. Regardless of the interval, the priority arbitration circuit 202 arbitrates the memory access request signal and gives a memory access permission signal to only one bus master 201. Therefore, the bus master 201 that transmits and receives communication data with an external circuit in synchronization with the input clock CLK receives the input clock CLK.
The higher the speed, the greater the amount of communication data per unit time, and therefore the more memory access requests to the memory 203. However, the bus arbitration circuit 202 permits the bus master 201 to access the memory only at a rate equivalent to that of the bus master that transmits and receives data to and from an external circuit at a low speed clock. Therefore, when the memory access request from each bus master 201 increases, the input clock CL
As K is a high speed, since the time be output memory access request signal wait is not returned memory access permission signal from the priority arbitration circuit 202 is increased, transmitting and receiving data in the bus <br/> Sumasuta 201 Has a disadvantage that the probability of occurrence of overrun / underrun increases.

In addition, the priority of the memory access request signal output from the bus master transmitting and receiving data at a high speed clock is increased in the priority arbitration circuit 202 in advance, and the memory access request output from the priority arbitration circuit 202 is increased. There is also a method in which the permission signal is sent to a bus master that transmits and receives data at a low-speed clock, thereby shortening the waiting time of the memory access permission for the memory access request. However, also in this case, the priority in the priority arbitration circuit 202 is determined in advance, so that the input clock CLK
Once the priorities are determined according to, there is a disadvantage that the subsequent input clock cannot be changed. For example, it becomes impossible to accommodate a bus master having an input clock of 9.6 kbps for the bus master 201 having an input clock of 64 kbps.

It is an object of the present invention to convert the arbitration priority of memory access according to the speed of the line clock when transferring data read / written from / to the memory in synchronization with the line clock, thereby achieving overrun / underrun. To provide an arbiter apparatus and an arbiter method capable of reducing the probability of the arbiter.

[0010]

According to the present invention, first to n-th (n is an integer of 2 or more) lines capable of memory read / write and capable of communicating data synchronized with a line clock with an external circuit. A control circuit, one memory in which data communicated with the external circuit by the first to n-th line control circuits can be shared and accessed by memory read / write, and a first to n-th line control circuit. The first to n-th clocks which are provided and detect m (m is an integer of 2 or more) clock speed ranges by measuring the number of line clocks per unit time, and digitize the detection state and output to the outside. A speed detection circuit, a memory read / write request from the first to n-th line control circuits, and a numerical value from the first to n-th clock speed detection circuit, respectively. By inputting state, m
First to n-th memory access weighting circuits capable of outputting memory read / write requests, (n × m) input terminals capable of receiving memory read / write requests, and capable of outputting arbitration results (nxm) One priority arbitration circuit having a plurality of output terminals, arbitrating a plurality of memory read / write requests, and outputting a single memory read / write enable signal from the output terminals; and a first to n-th lines A first to an n-th memory access permission signal generation circuit that is provided corresponding to the control circuit and that ORs m arbitration results for each line control circuit output from the priority order arbitration circuit. An arbiter device is obtained.

According to the present invention, there is provided an arbiter method in which a plurality of line control circuits communicating with an external circuit share a single memory by memory access. Detected by measuring the number of clocks per time, digitizes and outputs m (m is an integer of 2 or more) status values according to the speed range of the line clock speed, and inputs a memory access request from the line control circuit to the arbitration circuit. Inputting a memory access request corresponding to the state value, thereby obtaining an arbiter method characterized in that the memory access request input can be changed according to the line clock speed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an arbiter device according to one embodiment of the present invention. The illustrated arbiter apparatus includes first to n-th (n is an integer of 2 or more) line control circuits 101-1, 101-2,..., 101-n, and first to n-th line clock speed detection circuits 102. -1,102-
, 102-n and first to n-th DMA transfer request weighting circuits 103-1, 103-2, ..., 103-n
, A priority arbitration circuit 104, and first to n-th DMAs
Transfer permission signal generation circuits 105-1, 105-2,..., 1
05-n and a memory 106.

The line control output circuit 101 (subscript omitted)
After outputting MA transfer request signal BRQ (subscript omitted),
When the A transfer permission signal BAK (subscript omitted) is input, D
Data can be written to / read from the memory 106 by MA transfer, and data synchronized with a line clock CLK (subscript omitted) input from an external circuit (not shown) is written to the memory 106 by DMA transfer. , Data read by DMA transfer can be output in synchronization with the line clock CLK.

The line clock speed detection circuit 102 (subscript omitted) can input the input line clock CLK and output a number determined by the speed range of the line clock CLK.

Referring to FIG. 3, line clock speed detection circuit 102 includes an oscillator 301, a counter 302, a latch circuit 303, and a comparator 304.

The oscillator 301 generates a local clock that is sufficiently slower than the line clock. Counter 302
Indicates that the local clock generated by the oscillator 301 has a logic “H”.
Line clock CLK input from outside only during level
And sends the measurement result to the latch circuit 303. The latch circuit 303 holds the output value (measurement result) of the counter 302 every time the local clock generated by the oscillator 301 changes from the logic “H” level to the logic “L” level. The comparator 304 compares the value held by the latch circuit 303 with a predetermined value, and outputs the range of the value held by the latch circuit 303 as a number. For example, the comparator 304 determines the number “1” if the held value is less than 10, the number “2” if it is 10 or more and less than 50, and the number “3” if it is 50 or more and less than 100.
If it is 0 or more, "4" is output.

Returning to FIG. 1, the DMA transfer request weighting circuit 103 (subscript omitted) uses the number m supplied from the line clock speed detection circuit 102 to convert the DMA transfer request supplied from the line control circuit 101 to m. It is a circuit to multiply.

FIG. 4 shows a circuit configuration of the DMA transfer request weighting circuit 103 when the maximum value of m is 3. The DMA transfer request weighting circuit 103 includes a decoder 401 and OR gates 402 and 403. The decoder 401 has an input terminal A for inputting a speed detection result from the line clock speed detection circuit 102, an input terminal X for inputting a DMA transfer request signal BRQ from the line control circuit 101, and first to third decoder output terminals. Y1, Y2 and Y3.
The DMA transfer request weighting circuit 103 has first to third circuit output terminals Z1, Z2 and Z3. The first circuit output terminal Z1 is connected via an OR gate 402 to first to third decoder output terminals Y1 to Y3. The second circuit output terminal Z2 is connected via an OR gate 403 to the second and third decoder output terminals Y2 and Y3. The third circuit output terminal Z3 is connected to the third decoder output terminal Y3.

In such a configuration, when m = 1, a DMA transfer request signal is output only to the first circuit output terminal Z1. When m = 2, the first and second circuit output terminals Z
DMA transfer request signals are output to 1 and Z2. m =
3, when the first to third circuit output terminals Z1 to Z3 are DM
An A transfer request signal is output.

Returning to FIG. 1, the priority arbitration circuit 104
Is a plurality of D from the (m × n) DMA transfer request input terminals.
An MA transfer request signal is input, and a DMA transfer permission signal is output to an output terminal corresponding to the input terminal one-to-one with respect to the input with the highest priority.

The DMA transfer permission signal generation circuit 105 (subscript omitted) performs a logical sum of the output terminal of the priority arbitration circuit 104 corresponding to each line control circuit 101, and outputs the logical sum to the corresponding line control circuit 101. Output to

Therefore, the line clock speed detection circuit 102
The line control circuit 101 to which “x” has been output at
X times the priority of the transfer request signal BRQ,
By receiving the A transfer permission signal BAK, the DMA
The transfer enables communication with an external circuit.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes / modifications can be made without departing from the spirit of the present invention. .

[0025]

As described above, according to the present invention, the priority of memory access permission can be changed depending on the input clock speed at which the line control circuit communicates with the external circuit. The priority of memory access permission with the line control circuit that communicates with the external circuit using the high-speed clock is not fixed, and the priority automatically changes when the line clock speed changes. Therefore, in particular, in a line control circuit accommodating a line changed from a low-speed clock to a high-speed clock, there is an effect that the possibility of occurrence of overrun / underrun of transfer data can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arbiter device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional arbiter device.

FIG. 3 is a block diagram showing a configuration of a line clock speed detection circuit in FIG. 1;

FIG. 4 is a block diagram showing the configuration of a DMA transfer request weighting circuit in FIG. 1 when the maximum value of m is 3.

[Explanation of symbols]

101-1 to 101-n line control circuit 102-1 to 102-n line clock speed detection circuit 103-1 to 103-n DMA transfer request weighting circuit 104 priority arbitration circuit (m × n input arbitration) 105-1 105-n DMA transfer permission signal generation circuit 106 memory 201-1 to 201-N bus master 202 priority arbitration circuit (N input arbitration) 203 memory 301 oscillator 302 counter 303 latch circuit 304 comparator 401 decoder 402, 403 or gate

Claims (3)

(57) [Claims] A first to an n-th (n is an integer of 2 or more) line control circuits capable of performing memory read / write and communicating data synchronized with a line clock with an external circuit; one memory in which n line control circuits can access data shared with the external circuit by memory read / write, and one memory corresponding to the first to n-th line control circuits; By measuring the number of line clocks per one block, m (m is an integer of 2 or more) clock speed ranges are detected, and the detection state is digitized and output to the outside.
To a n-th clock speed detection circuit; and a memory read / write request from the first to the n-th line control circuits. A first to an n-th memory access weighting circuit capable of outputting m number of memory read / write requests by inputting the digitized state from the n-th clock speed detection circuit; It has (n × m) input terminals capable of inputting and (n × m) output terminals capable of outputting arbitration results, and arbitrates a plurality of memory read / write requests.
One priority arbitration circuit capable of outputting only one memory read / write permission signal from the output terminal; and a priority arbitration circuit provided corresponding to the first to n-th line control circuits and output from the priority arbitration circuit. And a first to n-th memory access permission signal generation circuit for performing a logical sum of m arbitration results for each line control circuit. 2. An oscillator in which each of the first to n-th clock speed detecting circuits generates a local clock sufficiently lower than the line clock, and wherein the local clock generated by the oscillator is a first clock. A counter for measuring the number of the line clocks CLK only during the logical level of the counter, and measuring the counter each time the local clock generated by the oscillator changes from the first logical level to the second logical level. A latch circuit that holds a result, and a comparator that compares a value held by the latch circuit with a predetermined value to output a range of values held by the latch circuit as a number. The arbiter device according to claim 1, wherein 3. An arbiter method in which a plurality of line control circuits communicating with an external circuit share a single memory by memory access, wherein the line clock speed for communicating with the external circuit is controlled by a clock per unit time for each of the line control circuits. When the number is detected by counting the number, m (m is an integer of 2 or more) state values are quantified and output according to the speed range of the line clock speed, and a memory access request is input from the line control circuit to the arbitration circuit. Inputting a memory access request corresponding to the state value, whereby the memory access request input can be changed in accordance with the line clock speed.