JP2643789B2 - Scan path circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path circuit, and more particularly to a scan path circuit having two types of output signals, one of which is used to control a data circuit and the other is used to transmit scan data. Scan path circuit.

[0002]

2. Description of the Related Art Conventionally, as this kind of scan path circuit, as shown in FIG.
There is a circuit in which the output signals O of the SLHB 13 are connected in series as a scan chain, and the output signals O control the tristate buffers TBF1 to TBF3.

The scan latches SLHB11-SLH
In the HB 13, a common operation clock (hereinafter, referred to as a master clock) CLK is input to the clock signal CK and a scan clock (hereinafter, referred to as a test clock) TCK is input to the clock signal TK as common input signals.

Further, scan latches SLHB11-SLHB
In the HB 13, a signal (hereinafter, referred to as a scan select signal) SSEL for selecting a normal operation and a shift register operation (hereinafter, referred to as a scan operation) is input to the selection signal SE.

In the scan latch SLHB11, the output signal DC11 of the control circuit DEC1 is input to the input signal D as input data, and the scan input signal SIN is input to the input signal S.
Input to I.

The output signal O of the scan latch SLHB11 is the control signal C of the tristate buffer TBF1.
NT11 and the scan chain SC11, and the scan chain SC11 is connected to the next-stage scan latch SLHB1.
2 input signal SI.

In the scan latch SLHB12, the output signal DC12 of the control circuit DEC2 is input to the input signal D as input data, and the output signal O of the preceding scan latch SLHB11 is input to the input signal SI via the scan chain SC11.

The output signal O of the scan latch SLHB12 is the control signal C of the tristate buffer TBF2.
NT12 and the scan chain SC12, and the scan chain SC12 is connected to the next-stage scan latch SLHB1.
3 is input to the input signal SI.

In the scan latch SLHB13, the output signal DC13 of the control circuit DEC3 is input to the input signal D as input data, and the output signal O of the preceding scan latch SLHB12 is input to the input signal SI via the scan chain SC12.

The output signal O of the scan latch SLHB13 is the control signal C of the tristate buffer TBF3.
NT13 and the scan output signal SOUT.

FIG. 8 shows the operation of the scan path circuit shown in FIG.
This will be described below with reference to the timing chart of FIG.

When a normal operation is performed as a first operation,
The scan select signal SSEL is at logic “0”, the test clock TCK is at logic “1” and the control circuit DEC1
DEC3 output signals DC11 to DC13 are logic "10".
The operation when the value is "0" will be described.

Scan latches SLHB11-SLHB1
3 latches the logic "100" at the rising edge of the master clock CLK and outputs it from the output signal O. Therefore, the control signals CNT11 to CNT13, the scan chains SC11 and SC12, and the scan output signal SOUT
Are logical "100" respectively.

Here, when the 4-bit data signal DI1 is logic "0000", the 4-bit data signal DI2 is logic "0101", and the 4-bit data signal DI3 is logic "1111", Control signals CNT11 to CN
Since T13 is logic "100", the tristate buffer TBF1 conducts, and the value on the bus BUS is
It becomes the logic "0000" of I1.

When the scan operation is performed as the second operation, the scan select signal SSEL is at logic "1", the master clock CLK is fixed at logic "1", and the serial data is logic "1" as the scan input signal SIN.
Input in the order of “0” and “1”, and scan latch SLH
The operation when B11 to SLHB13 hold the logic “100” latched in the first operation will be described.

At the first rising edge of the test clock TCK, the scan latch SLHB11 latches the logic "1" of the scan input signal SIN from the input signal SI, and outputs the logic "1" from the output signal O.

The scan latch SLHB12 latches the logic "1", which is the value held by the scan latch SLHB11, from the scan chain SC11, and outputs this logic "1" from the output signal O.

The scan latch SLHB13 latches the logic "0" held by the scan latch SLHB12 from the scan chain SC12, and outputs the logic "0" from the output signal O.

Thus, the control signals CNT11-CNT
T13, the scan chains SC11 and SC12, and the scan output signal SOUT each have a logic “110”.
Therefore, tristate buffers TBF1 and TBF2 conduct, respectively.

Here, the data signal DI1 has a logic "000".
0 ", the data signal DI2 is logic" 0101 "and the data signal DI3 is logic" 1111 ".
In the above, the first bit data and the third bit data collide.

At the second rising edge of the test clock TCK, the scan latch SLHB11 latches the logic "0" of the scan input signal SIN from the input signal SI, and outputs the logic "0" from the output signal O.

The scan latch SLHB12 latches the logic "1" held by the scan latch SLHB11 from the scan chain SC11, and outputs the logic "1" from the output signal O.

The scan latch SLHB13 latches the logic "1", which is the value held by the scan latch SLHB12, from the scan chain SC12, and outputs the logic "1" from the output signal O.

Thus, the control signals CNT11-CNT
T13, the scan chains SC11 and SC12, and the scan output signal SOUT each have a logic “011”.
Therefore, the tristate buffers TBF2 and TBF3 conduct.

Here, the data signal DI1 has a logic "000".
0 ", the data signal DI2 is logic" 0101 "and the data signal DI3 is logic" 1111 ".
In the above, the data of the second bit and the data of the fourth bit collide.

At the third rising edge of the test clock TCK, the scan latch SLHB11 latches the logic "1" of the scan input signal SIN from the input signal SI, and outputs the logic "1" from the output signal O.

The scan latch SLHB12 latches the logic "0" which is the value held by the scan latch SLHB11 from the scan chain SC11, and outputs the logic "0" from the output signal O.

The scan latch SLHB13 latches the logic "1", which is the value held by the scan latch SLHB12, from the scan chain SC12, and outputs the logic "1" from the output signal O.

Thus, the control signals CNT11-CNT
T13, the scan chains SC11 and SC12, and the scan output signal SOUT each have a logic “101”.
When the scan operation ends at the third rising of the test clock TCK, the tristate buffers TBF1 and TBF1
BF3 remains conductive.

At this time, the data signal DI1 changes to logic "00".
00, the data signal DI2 is logic “0101” and the data signal DI3 is logic “1111”, the bus BU
On S, all bits collide and a huge current flows.

The above-described scan path circuit is a circuit that uses the output signal O of the scan latches SLHB11 to SLHB13 for the control signals of the tristate buffers TBF1 to TBF3, the scan chains SC11 and SC12, and the scan output signal SOUT.

This scan path circuit is described in "Fault-Tolerant System Theory; Chapter 3 Hardware Testing" (edited by Yoshihiro Toma, IEICE, 1990, 6, p. 9).
The same operation is performed as when the latch used in the scan path circuit described in 3) is used.

As other scan path circuits, as shown in FIG. 9, scan latches SLHB14 to SLHB14 to SLH
There is a circuit that connects the output signal O of B16 in series as a scan chain, inputs the output signal O to the data collision prevention circuit DFPC, and controls the selection circuit MUX with the output of the data collision prevention circuit DFPC.

Scan latches SLHB14 to SLHB1
6, the master clock CLK is input to the clock signal CK, the test clock TCK is input to the clock signal TK as common input signals, and the scan select signal S
SEL is input to the selection signal SE.

In the scan latch SLHB14, the output signal DC14 of the control circuit DEC4 is input to the input signal D as input data, and the scan input signal SIN is input to the input signal S.
Input to I.

The output signal O of the scan latch SLHB14 is connected to the control signal CNT14 and the scan chain SC1.
4, which are the input of the data collision prevention circuit DFPC and the input signal SI of the next-stage scan latch SLHB15.
Respectively. The output signal MCNT4 of the data collision prevention circuit DFPC becomes a control signal of the selection circuit MUX.

In the scan latch SLHB15, the output signal DC15 of the control circuit DEC5 is input to the input signal D as input data, and the output signal O of the preceding scan latch SLHB14 is input to the input signal SI via the scan chain SC14.

The output signal O of the scan latch SLHB15 is connected to the control signal CNT15 and the scan chain SC1.
5, which are the input of the data collision prevention circuit DFPC and the input signal SI of the next-stage scan latch SLHB16.
Respectively. The output signal MCNT5 of the data collision prevention circuit DFPC becomes a control signal of the selection circuit MUX.

In the scan latch SLHB16, the output signal DC16 of the control circuit DEC6 is input to the input signal D as input data, and the output signal O of the preceding scan latch SLHB15 is input to the input signal SI via the scan chain SC15.

The output signal O of the scan latch SLHB16 is the input signal CNT of the data collision prevention circuit DFPC.
16 and the scan output signal SOUT. The output signal MCNT6 of the data collision prevention circuit DFPC is selected by the selection circuit MU.
X control signal.

The operation of the scan path circuit shown in FIG.
This will be described below with reference to the timing chart of FIG.

When the normal operation is performed as the first operation,
The scan select signal SSEL is logic “0”, the test clock TCK is logic “1”, and the control circuit DEC4
DEC6 output signals DC14 to DC16 are logic "10".
The operation when the value is "0" will be described.

Scan latches SLHB14 to SLHB1
6 latches the logic “100” at the rising edge of the master clock CLK and outputs the latched output from the output signal O. Therefore, the control signals CNT14 to CNT16, the scan chains SC14 and SC15, and the scan output signal SOUT
Becomes logic "100".

At this time, the scan select signal SSEL
Is a logical "0", the data collision prevention circuit DFPC
Output signals MCNT4 to MCNT6 are control signals CNT1
4 to propagate the logic “100” of CNT16.

Here, the 4-bit data signal DI4 has a logic "1000", the 4-bit data signal DI5 has a logic "0101", and the 4-bit data signal DI6 has a logic "0110". When the long data signal DI7 is at logic "0001", the output signals MCNT4 to MCNT4 to MC
Since NT6 is logic "100", the data signal DI4 is selected.

Then, the arithmetic circuit ALU performs the addition operation to make the logic "1000" of the data signal DI4 and the data signal DI
7 is added to the logic "0001", so that the operation result SU
M becomes logic “1001”.

At this time, in the selection circuit MUX, the output signals MCNT4 to MCNT from the data collision prevention circuit DFPC are output.
6 to perform the selection operation, the scan latch SLHB14
To control signals CNT14 to CNT16 from SLHB16
In this case, the delay is delayed by the delay time t1 as compared with the case where the direct selection operation is performed.

When the scan operation is performed as the second operation, the scan select signal SSEL is logic "1", the master clock CLK is fixed at logic "1", and the serial data is logic "1" as the scan input signal SIN.
Input in the order of “0” and “1”, and scan latch SLH
The operation when B14 to SLHB16 hold the logic “100” latched in the first operation will be described.

At the first rising edge of the test clock TCK, the scan latch SLHB14 latches the logic "1" of the scan input signal SIN from the input signal SI, and outputs this logic "1" from the output signal O.

The scan latch SLHB15 latches the logic "1", which is the value held by the scan latch SLHB14, from the scan chain SC14, and outputs this logic "1" from the output signal O.

The scan latch SLHB16 latches the logic "0" held by the scan latch SLHB15 from the scan chain SC15, and outputs the logic "0" from the output signal O.

Thus, the control signals CNT14 to CNT
T16, the scan chains SC14 and SC15, and the scan output signal SOUT each have a logic "110".
At this time, the scan select signal SSEL becomes logic “1”.
Therefore, the logic “110” of the control signals CNT14 to CNT16 is not propagated to the output signals MCNT4 to MCNT6 from the data collision prevention circuit DFPC to the selection circuit MUX, and the logic “001” which is a fixed value is output. Therefore, the data signal DI6 is always selected by the selection circuit MUX during the scan operation.

At the second rising edge of the test clock TCK, the scan latch SLHB14 latches the logic "0" of the scan input signal SIN from the input signal SI and outputs it from the output signal O.

The scan latch SLHB15 latches the value, logic "1", held by the scan latch SLHB14 from the scan chain SC14 and outputs it from the output signal O.

The scan latch SLHB16 latches the logic value "1" held by the scan latch SLHB15 from the scan chain SC15 and outputs it from the output signal O.

Thus, the control signals CNT14-CNT
T16, the scan chains SC14 and SC15, and the scan output signal SOUT each have a logic “011”.
At this time, the scan select signal SSEL becomes logic “1”.
Therefore, the logic “011” of the control signals CNT14 to CNT16 is not propagated to the output signals MCNT4 to MCNT6 from the data collision prevention circuit DFPC to the selection circuit MUX, and the logic “001” which is a fixed value is output. Therefore, the data signal DI6 is always selected by the selection circuit MUX during the scan operation.

At the third rising edge of the test clock TCK, the scan latch SLHB14 latches the logic "1" of the scan input signal SIN from the input signal SI and outputs the same from the output signal O.

Scan latch SLHB15 latches logic "0", which is the value held by scan latch SLHB14, from scan chain SC14, and outputs this logic "0" from output signal O.

The scan latch SLHB16 latches the logic "1" which is the value held by the scan latch SLHB15 from the scan chain SC15, and outputs the logic "1" from the output signal O.

Thus, the control signals CNT14 to CNT
T16, the scan chains SC14 and SC15, and the scan output signal SOUT each have a logic “101”.
At this time, the scan select signal SSEL becomes logic “1”.
Therefore, the logic “101” of the control signals CNT14 to CNT16 is not propagated to the output signals MCNT4 to MCNT6 from the data collision prevention circuit DFPC to the selection circuit MUX, and the logic “001” which is a fixed value is output. Therefore, the data signal DI6 is always selected by the selection circuit MUX during the scan operation.

The above-described scan path circuit outputs the output signals O of the scan latches SLHB14 to SLHB16 to the scan chains SC14 and SC15 and the scan output signal S
OUT and the input signal of the data collision prevention circuit DFPC,
This circuit controls the selection circuit MUX with the output of the data collision prevention circuit DFPC.

This data collision prevention circuit is called “synops
ys (a trademark of Nippon Synops Corporation) Test Com
The same operation as the three-state invalidation circuit described in FIG. 5-2 of “Piler Reference Manual (Japanese version) Version 2.0; Chapter 5 Addition of Scan Test Circuit” (published by Nippon Synops Co., Ltd., 1.91.8). I do.

[0063]

In the above-described conventional scan path circuit, the output of the scan latch is used for both control of the data circuit and transmission of the scan data. Become. Therefore, depending on the combination of data to be scanned, data in the data circuit may collide with each other and destroy the IC.

If a data collision prevention circuit is provided to prevent this problem, control of the data circuit is delayed by the data collision prevention circuit, and the operating frequency is affected.

Accordingly, it is an object of the present invention to provide a scan path circuit which solves the above-mentioned problems and can prevent IC destruction due to data collision during a scan operation without affecting the operation frequency.

[0066]

Scan path circuits of the present invention According to an aspect of the saw including a plurality of scan latches operate as cascaded and shift register by a signal line for propagating the scan data, typically to the plurality of scan latches each
Clock signal for operation and clock signal for scan operation
Is a scan path circuit to which is input, an output terminal for outputting data in a normal operation , a scan output terminal connected to the signal line and outputting data in a scan operation, and a clock for the normal operation. Signal and said scan
The plurality of scan latches together with an operation clock signal are provided.
And a means for suppressing output of the held data to the output terminal in response to the scan select signal input to each of the scan latches and permitting the output of the held data to the scan output terminal. Provided inside.

Another scan path circuit according to the present invention includes a plurality of scan latches cascaded by signal lines for transmitting scan data and operating as shift registers.
Only, the plurality of scan latches each have a clock for normal operation.
Clock signal and a clock signal for scan operation are input.
That a scan path circuit, an input terminal for inputting the data in the normal operation, a scan input terminal for inputting data when connected and scanning operation to the signal line, input from the input terminal and the scan input terminal means for holding the data in common, and an output terminal for outputting the data during the normal operation, and the scan output terminal for outputting the data at the time connected and the scanning operation to the signal line, before
The clock signal for the normal operation and the clock signal for the scan operation
A clock signal is applied to each of the plurality of scan latches.
Means for suppressing output of the held data to the output terminal in response to the input scan select signal and permitting the output of the held data to the scan output terminal are provided in each of the plurality of scan latches. doing.

[0068]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, a scan path circuit according to an embodiment of the present invention includes scan latches SLHA1 to SLHA.
3 each output signal SO is connected in series as a scan chain, and the tristate buffer TBF1
To TBF3.

In scan latches SLHA1 to SLHA3, master clock CLK is input to clock signal CK, test clock TCK is input to clock signal TK, and scan select signal SSE is input as common input signals.
L is input to the selection signal SE.

In scan latch SLHA1, output signal DC1 of control circuit DEC1 is input signal D as input data.
, And the scan input signal SIN is input to the input signal SI.

The output signal O of the scan latch SLHA1 is the control signal CN of the tristate buffer TBF1.
The output signal SO becomes the scan chain SC1 and the input signal SI of the next-stage scan latch SLHA2 becomes T1.
Is input to

In scan latch SLHA2, output signal DC2 of control circuit DEC2 is input signal D as input data.
And the output signal SO of the preceding scan latch SLHA1 is input to the input signal SI via the scan chain SC1.
Is input to

The output signal O of the scan latch SLHA2 is the control signal CN of the tristate buffer TBF2.
T2, the output signal SO becomes the scan chain SC2, and the input signal SI of the next-stage scan latch SLHA3
Is input to

In scan latch SLHA3, output signal DC3 of control circuit DEC3 is input signal D as input data.
, And the output signal SO of the preceding scan latch SLHA2 is input to the input signal SI via the scan chain SC2.
Is input to

The output signal O of the scan latch SLHA3 is the control signal CN of the tristate buffer TBF3.
T3, the output signal SO becomes the scan output signal SOUT
Becomes

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. The operation of the scan path circuit according to one embodiment of the present invention will be described with reference to FIGS.

When the normal operation is performed as the first operation,
The scan select signal SSEL is at logic “0”, the test clock TCK is at logic “1” and the control circuit DEC1
Ｄ DEC3 output signals DC1 to DC3 are logic “100”
The operation at the time of is described.

Scan latches SLHA1 to SLHA3 latch logic "100" at the rising edge of master clock CLK and output from output signal O and output signal SO. Therefore, the control signals CNT1 to CNT3, the scan chains SC1 and SC2, and the scan output signal S
OUT becomes logic "100", respectively, and the tristate buffer TBF1 is selected.

When the 4-bit data signal DI1 is logic "0000", the 4-bit data signal DI2 is logic "0101" and the 4-bit data signal DI3 is logic "1111", Is the logic "0000" of the data signal DI1.

When the scan operation is performed as the second operation, the scan select signal SSEL is at logic "1", the master clock CLK is fixed at logic "1", and the serial data is logic "1" as the scan input signal SIN.
Input in the order of “0” and “1”, and scan latch SLH
The operation when A1 to SLHA3 hold the logic “100” latched in the first operation will be described.

At the first rising edge of the test clock TCK, the scan latch SLHA1 latches the logic of the scan input signal SIN from the input signal SI to "1", and does not output this logic "1" from the output signal O. Output signal S
Output from O.

The scan latch SLHA2 latches the logic "1" which is the value held by the scan latch SLHA1 from the scan chain SC1, and outputs the logic "1" from the output signal SO without outputting from the output signal O. I do.

Scan latch SLHA3 latches logic "0", which is the value held by scan latch SLHA2, from scan chain SC2, and outputs this logic "1" from output signal SO without outputting from output signal O. I do.

At the second rising edge of test clock TCK, scan latch SLHA1 latches logic "0" of scan input signal SIN from input signal SI, and outputs this logic "0" without output signal O. Output signal S
Output from O.

Scan latch SLHA2 latches logic "1", which is the value held by scan latch SLHA1 from scan chain SC1, and outputs this logic "1" from output signal SO without output from output signal O. I do.

The scan latch SLHA3 latches the logic “1”, which is the value held by the scan latch SLHA2, from the scan chain SC2, and outputs the logic “1” from the output signal SO without outputting the output signal O. I do.

At the third rising edge of test clock TCK, scan latch SLHA1 latches logic "1" of scan input signal SIN from input signal SI, and outputs this logic "1" without output signal O. Output signal SO
Output from

Scan latch SLHA2 latches logic "0", which is the value held by scan latch SLHA1 from scan chain SC1, and outputs this logic "0" from output signal SO without output from output signal O. I do.

The scan latch SLHA3 latches the logic "1", which is the value held by the scan latch SLHA2, from the scan chain SC2, and outputs the logic "1" from the output signal SO without outputting from the output signal O. I do.

At this time, scan latches SLHA1-SLHA
Since the output signal O of the LHA 3 holds the logic “100” which is the value latched during the normal operation, the control signal CN
T1 to CNT3 become logic "100", the tristate buffer TBF1 becomes conductive, and the value on the bus BUS becomes logic "0000" of the data signal DI1.

The scan path circuit described above converts the output signals O of the scan latches SLHA1 to SLHA3 to the control signals CNT1 to CNT of the tristate buffers TBF1 to TBF3.
This circuit is used for NT3 and uses the output signal SO for a scan chain.

FIG. 3 is a block diagram showing another embodiment of the present invention. In the figure, a scan path circuit according to another embodiment of the present invention includes scan latches SLHA4 to SLHA6.
Are connected in series as a scan chain, and the output signal O is connected to the control signals CNT4 to CNT4 of the selection circuit MUX.
This is a circuit to be CNT6.

In scan latches SLHA4 to SLHA6, master clock CLK is input to clock signal CK, test clock TCK is input to clock signal TK, and scan select signal SSE is input as common input signals.
L is input to the selection signal SE.

In the scan latch SLHA4, the output signal DC4 of the control circuit DEC4 is used as the input data as the input signal D.
, And the scan input signal SIN is input to the input signal SI.

The output signal O of the scan latch SLHA4 becomes the control signal CNT4 of the selection circuit MUX, and the output signal SO becomes the scan chain SC4 and is input to the input signal SI of the next-stage scan latch SLHA5.

In scan latch SLHA5, output signal DC5 of control circuit DEC5 is input signal D as input data.
And the output signal SO of the preceding scan latch SLHA4 is input to the input signal SI via the scan chain SC4.
Is input to

The output signal O of the scan latch SLHA5 becomes the control signal CNT5 of the selection circuit MUX, and the output signal SO becomes the scan chain SC5 and is input to the input signal SI of the next-stage scan latch SLHA6.

In the scan latch SLHA6, the output signal DC6 of the control circuit DEC6 is used as the input data as the input data.
And the output signal SO of the preceding scan latch SLHA5 is input to the input signal SI via the scan chain SC5.
Is input to

The output signal O of the scan latch SLHA6 becomes the control signal CNT6 of the selection circuit MUX, and the output signal SO becomes the scan output signal SOUT.

FIG. 4 is a timing chart showing the operation of another embodiment of the present invention. The operation of the scan circuit according to another embodiment of the present invention will be described with reference to FIGS.

When the normal operation is performed as the first operation,
The scan select signal SSEL is logic “0”, the test clock TCK is logic “1”, and the control circuit DEC4
出力 Output signals DC4 to DC6 of DEC6 are logic “100”
The operation at the time of is described.

Each of the scan latches SLHA4 to SLHA6 latches the logic "100" at the rising edge of the master clock CLK and outputs it from the output signal O and the output signal SO. Therefore, the control signals CNT4 to CNT6, the scan chains SC4 and SC5, and the scan output signal S
OUT is logic "100", respectively.

As a result, the selection circuit MUX selects the data signal DI4, and the arithmetic circuit ALU adds the logic "1000" of the data signal DI4 and the logic "0001" of the data signal DI7 by the addition operation. The result SUM is logic "1001".

When the scan operation is performed as the second operation, the scan select signal SSEL is logic "1", the master clock CLK is fixed at logic "1", and the serial data is logic "1" as the scan input signal SIN.
Input in the order of “0” and “1”, and scan latch SLH
The operation when A4 to SLHA6 hold the logic "100" latched in the first operation will be described.

At the first rising edge of the test clock TCK, the scan latch SLHA4 latches the logic of the scan input signal SIN from the input signal SI to "1", and outputs this logic "1" from the output signal O without outputting it. Output signal SO
Output from

The scan latch SLHA5 latches the logic "1", which is the value held by the scan latch SLHA4, from the scan chain SC4, and outputs the logic "1" from the output signal SO without outputting the output signal O. I do.

Scan latch SLHA6 latches logic "0", which is the value held by scan latch SLHA5, from scan chain SC5, and outputs this logic "0" from output signal SO without outputting from output signal O. .

At the second rising edge of test clock TCK, scan latch SLHA4 latches logic "0" of scan input signal SIN from input signal SI and outputs this logic "0" without outputting from output signal O. Output from the signal SO.

The scan latch SLHA5 latches the logic "1" which is the value held by the scan latch SLHA4 from the scan chain SC4, and outputs the logic "1" from the output signal SO without outputting the logic "1" from the output signal O. Output.

The scan latch SLHA6 latches the logic "1" which is the value held by the scan latch SLHA5 from the scan chain SC5, and outputs the logic "1" from the output signal SO without outputting the output signal O. .

At the third rising edge of test clock TCK, scan latch SLHA4 latches logic "1" of scan input signal SIN from input signal SI, and outputs this logic "1" without output signal O. Output signal SO
Output from

The scan latch SLHA5 latches the logic "0" held by the scan latch SLHA4 from the scan chain SC4, and outputs the logic "0" from the output signal SO without outputting the logic "0" from the output signal O. I do.

The scan latch SLHA6 latches the logic "1" which is the value held by the scan latch SLHA5 from the scan chain SC5, and outputs the logic "1" from the output signal SO without outputting the logic "1" from the output signal O. .

At this time, the scan latches SLHA4 to SLHA
Since the output signal O of the LHA 6 holds the logic “100” which is the value latched during the normal operation, the control signal CNT
4 to CNT6 become logic "100" and select circuit MUX
Selects the data signal DI4.

The above-described scan path circuit outputs the output signals O of the scan latches SLHA4 to SLHA6 to the selection circuit MU.
X for the control signals CNT4 to CNT6 and the output signal SO
Is a circuit used for the scan chain.

FIG. 5 shows the scan latch SL of FIGS. 1 and 3.
It is a figure showing the example of composition of HA1-SLHA6. In the drawing, a clock signal CK for normal operation and a clock signal TK for scan operation are input as clock inputs to scan latches SLHA1 to SLHA6.

The clock signal CK is input to the gate input of the inverter I2, the gate input of the P-channel MOS transistor of the clocked inverter CI1, and the gate input of the N-channel MOS transistor of the two-input clocked inverter DCI1. .

The output of the inverter I2 is input to the gate input of the N-channel MOS transistor of the clocked inverter CI1 and the gate input of the P-channel MOS transistor of the two-input clocked inverter DCI1.

On the other hand, clock signal TK is supplied to inverter I3
, The gate input of the P-channel MOS transistor of the clocked inverter CI2, and the gate input of the N-channel MOS transistor of the clocked inverter CI3.

The output of the inverter I3 is the gate input of the N-channel MOS transistor of the clocked inverter CI2 and the P-channel MOS transistor of the clocked inverter CI3.
The signal is input to the gate input of the OS transistor.

The selection signal SE is supplied to the gate input of the inverter I1 and the P input of the two-input clocked inverter DCI1.
These are input to the gate input of the channel type MOS transistor, respectively.

The output of inverter I1 is input to the gate input of an N-channel MOS transistor of two-input clocked inverter DCI1.

The input signal D to which the control data is input is input to the gate input of the clocked inverter CI1, and the control data input from the input signal D is output from the output signal O.

Input signal SI to which scan data is input
Is input to the gate input of the clocked inverter CI2, and the scan data input from the input signal SI is output from the output signal SO.

When the normal operation is performed as the first operation,
The operation of scan latches SLHA1-SLHA6 when selection signal SE is at logic "0", clock signal CK is at logic "0", and clock signal TK is at logic "1" will be described.

If the input signal D is logic "1", the clocked inverter CI to which the input signal D is gated is input.
1 outputs a logic "0" and this clocked inverter C
The logic "0" of the output signal DATA of I1 is held by the feedback inverters I4 and I5. At this time, the input signal S
Clocked inverter CI2 to which I is gated
Is in a high impedance state.

Next, only the clock signal CK has the logic "1".
, The output of the two-input clocked inverter DCI1 to which the signal DATA1 is input becomes logic "1". The output signal DATA2 of the two-input clocked inverter DCI1 is held at logic "1" by the feedback inverters I6 and I7.

This output signal DATA2 is connected to the inverter I1
Since the signal propagates through 0 and I11 and is output to the output signal O, the value of the output signal O becomes logic "1". At this time, the clocked inverter CI to which the output signal DATA1 is input is
3 becomes logic "1", the output signal DATA3 of the clocked inverter CI3 is
9 holds a logic “1”. This output signal DA
TA3 propagates through inverters I8 and I12 to output signal S
Since the signal is output to O, the value of the output signal SO becomes logic “1”.

When the scan operation is performed as a second operation, the scan latches SLHA1 to SLHA6 when the selection signal SE is at logic "1", the clock signal TK is at logic "0", and the clock signal CK is at logic "1" are fixed. The operation will be described.

If input signal SI is logic "0", clocked inverter CI2 to which input signal SI is gate-inputted outputs logic "1", and output signal DATA1 of clocked inverter CI2 is fed back to feedback inverter I4. ,
The logic "1" is held by I5. At this time, the clocked inverter C to which the input signal D is gated is input.
The output of I1 is in a high impedance state.

Next, only the clock signal TK has the logic "1".
, The output of the clocked inverter CI3 to which the signal DATA1 is input becomes logic “0”. The output signal DATA3 of the clocked inverter CI3 is maintained at logic "0" by the feedback inverter I9.

This output signal DATA3 is supplied to the inverter I
8, I12 and output to the output signal SO.
The value of the output signal SO becomes logic “0”. At this time, the output of the two-input clocked inverter DCI1 to which the output signal DATA1 is input is in a high impedance state.

FIG. 6 is a circuit diagram showing a configuration of two-input clocked inverter DCI1 of FIG. In the figure, a two-input clocked inverter DCI1 is a P-channel type MO.
S transistors C1, T1, C2 and N-channel type MO
It comprises S transistors C3, T2 and C4.

The source of the P-channel MOS transistor C1 is a power supply, and the gate is a selection signal SE. The P-channel MOS transistor T1 uses the drain of the P-channel MOS transistor C1 as a source and the gate as an input signal I1. P-channel MOS transistor C2
Uses the drain of the P-channel MOS transistor T1 as a source and the gate as a clock inversion signal CKB. These P-channel MOS transistors C1, T1, C2
Are connected in series.

The N-channel MOS transistor C
Reference numeral 4 designates the source as ground (GND) and the gate as the selection inversion signal SEB. N-channel type MOS transistor T2
Uses the drain of the N-channel MOS transistor C4 as a source and the gate as an input signal I1. The N-channel MOS transistor C3 uses the drain of the N-channel MOS transistor T2 as the source and the gate as the clock signal CK. These N-channel MOS transistors C3, C4 and T2 are connected in series, and the drain of the P-channel MOS transistor C2 and the N-channel
The drain of the OS transistor C3 is connected to the output signal O1.

As a first operation, an operation when the selection signal SE is at logic "1" and the selection inversion signal SEB is at logic "0" will be described. At this time, the P-channel MOS transistor C1 and the N-channel MOS transistor C4 are turned off, so that the output signal O1 is in a high impedance state.

As a second operation, the operation when the selection signal SE is logic “0”, the selection inversion signal SEB is logic “1”, the clock signal CK is logic “0”, and the clock inversion signal CKB is logic “1” Will be described.

At this time, the P-channel MOS transistor C1 and the N-channel MOS transistor C4 conduct. However, since the P-channel type MOS transistor C2 and the N-channel type MOS transistor C3 are non-conductive, the output signal O1 is in a high impedance state.

As a third operation, the selection signal SE is logic "0", the selection inversion signal SEB is logic "1", the clock signal CK is logic "1", the clock inversion signal CKB is logic "0", and the input signal I1 The operation when is "1" is described. At this time, the P-channel MOS transistor T1 becomes non-conductive, and the P-channel MOS transistors C1 and C2 and the N-channel MOS transistors C3 and T3
2 and C4 conduct, the output signal O1 becomes logic "0".
Becomes

In this state, when the input signal I1 becomes logic "0", the N-channel MOS transistor T2 becomes non-conductive, and the P-channel MOS transistors C1, T2,
Since C2 and the N-channel MOS transistors C3 and C4 conduct, the output signal O1 becomes logic "1".

As described above, the scan select signal SSE
L prevents the scan data SIN input from each of the input signals SI of the scan latches SLHA1 to SLHA6 from being output to each output signal O, and outputs the output of the scan latches SLHA1 to SLHA6 to the output signal O for controlling the data circuit and the scan. By dividing the data into two types of outputs, that is, the output signal SO for data propagation, it is possible to prevent data collision in a data circuit due to data to be scanned, and to prevent IC destruction.

Further, since a data collision prevention circuit for preventing data collision in the selection circuit MUX or the like becomes unnecessary, control of the data circuit is not delayed during normal operation, and the operation frequency is not affected.

[0144]

As described above, according to the present invention, an output terminal for outputting data in a normal operation to a scan latch constituting a scan path circuit and a scan terminal for outputting data in a scan operation are provided. By arranging an output terminal and suppressing output of the data to the output terminal during the scanning operation, it is possible to prevent IC destruction due to data collision during the scanning operation without affecting the operating frequency. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a scan latch of FIGS. 1 and 3;

FIG. 6 is a circuit diagram showing a configuration of a two-input clocked inverter of FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional example.

FIG. 8 is a timing chart showing the operation of the conventional example.

FIG. 9 is a block diagram showing a configuration of another conventional example.

FIG. 10 is a timing chart showing the operation of another conventional example.

[Explanation of symbols]

 SLHA1 to SLHA6 Scan latch CK, TK Clock signal D, SI input signal O, SO output signal SE Scan selection signal

Claims (2)

(57) [Claims] 1. A saw including a plurality of scan latches operate as cascaded and shift register by a signal line for propagating the scan data, the plurality of scan latches each
A clock signal for normal operation and a clock signal for scan operation
A scan path circuit to which a scan signal is input, an output terminal for outputting data in a normal operation , a scan output terminal connected to the signal line and outputting data in a scan operation, Clock signal for said and said
The plurality of scans together with a clock signal for a scan operation.
Means for suppressing output of held data to the output terminal in response to a scan select signal input to each of the scan latches, and permitting output of the held data to the scan output terminal. A scan path circuit, which is internally provided. 2. A saw including a plurality of scan latches operate as cascaded and shift register by a signal line for propagating the scan data, the plurality of scan latches each
A clock signal for normal operation and a clock signal for scan operation
A scan signal to which a scan signal is input, an input terminal for inputting data during a normal operation, a scan input terminal connected to the signal line and inputting data during a scan operation, and the input terminal. Means for commonly holding data input from the scan input terminal, an output terminal for outputting the data in the normal operation, and a scan output terminal connected to the signal line and outputting the data in the scan operation A clock signal for the normal operation;
The plurality of clock signals for the scan operation and the plurality of
Means for suppressing output of held data to the output terminal in response to a scan select signal input to each scan latch and permitting output of the held data to the scan output terminal. A scan path circuit having the scan path circuit.