JP2644028B2 - Silicon carbide MOSFET - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a metal oxide semiconductor field effect transistor (MOSFET), and particularly to a silicon carbide metal oxide semiconductor field effect transistor.

BACKGROUND OF THE INVENTION Developments in using semiconductor devices for electrical applications have resulted in many devices having individual uses in creating circuits and electrical components. One type of device is known as a metal oxide semiconductor field effect transistor (MOSFET), named after its three main components. Such a device can be more generally referred to as a metal-insulator-semiconductor field-effect transistor (MISFET), but in many common applications, an oxide is used as the insulating layer, and as such is described herein. Throughout, the term metal oxide semiconductor field effect transistor (MOSFET) is used. However, it should be understood that other insulating materials may be used and referred to as appropriate.

Field effect transistors are somewhat different from junction transistors. Historically the first developed junction transistor was formed by placing two pn junctions very close to each other and sharing a small portion of semiconductor material known as the base. Junction transistors flow from a portion of the semiconductor material adjacent one junction (collector) through the base to the other junction (emitter), and determine the amount of current emanating from the voltage applied to the base. Control by controlling.

Field effect transistors operate on a somewhat different principle. Typically, current passes into a field-effect transistor through a region of semiconductor material known as a source and exits through another region of semiconductor material known as a drain. The source and the drain are separated from each other by a further semiconductor region known as a gate. An appropriate bias voltage, either positive or negative, (depending on the type of transistor) can be applied to the active region via the gate to control the current. In particular, if the semiconductor material of the gate is an n-type material through which current normally flows, applying a negative bias to the gate will reduce the electrons from the active region and narrow the conduction channel, thereby causing the electrons to flow from the source to the drain. Flow is obstructed. Such a device is called a depletion layer type MOSFET. Alternatively, if the semiconductor material of the gate is a p-type material, which is normally non-conductive, applying a positive bias to the gate reduces holes from the active region and creates an excess of electrical carriers. The area becomes more conductive.

An insulating material is located between each of the source and drain surfaces to passivate the surface and to insulate the gate contact from the gate semiconductor portion. Silicon is MOSF
Since it is currently the most commonly used material in ET, it is most common to form this insulating portion with silicon oxide. A gate contact, which can be a metal or other conductive material; an insulator (typically silicon dioxide);
Semiconductor materials and the method of operation of the device derive the name MOSFET.

(Problems to be Solved by the Invention) MOSFETs have been widely adopted as suitable devices since their introduction. However, as with all other semiconductor devices, some characteristics of the MOSFET are limited by the characteristics of the semiconductor material from which it is formed. Since silicon has some inherent limitations for certain applications,
MOSFETs formed from the corresponding silicon also have inherent limitations.

Accordingly, it has long been recognized that one way to improve device performance is to attempt to form the device with materials having better properties. One material with many excellent properties is silicon carbide (SiC). Silicon carbide has some excellent semiconductor properties: wide bandgap, high thermal conductivity, high breakdown field strength, and high saturation electron drift velocity. Wide bandgap silicon carbide has advantages over narrow bandgap semiconductor materials. In addition, due to its high thermal conductivity and better temperature stability, silicon carbide devices can be packed more tightly without risking mutual destruction due to the dissipated thermal energy, as well as carbonization. Devices formed by silicon can operate at significantly higher temperatures than devices made of narrow band gap semiconductors.

Therefore, many attempts have been made to form devices, especially MOSFETs, from silicon carbide. However, it is very difficult to produce a silicon carbide crystal having a suitable chemical purity and a low defect level, and it has been difficult to grow a single crystal thin film or a large crystal. In addition, it has been similarly difficult to introduce and activate dopant ions necessary for manufacturing the device into silicon carbide.

Recently, these problems have been successfully addressed, as described in several U.S. patent applications assigned to the assignee of the present invention. These are `` growth of beta SiC thin film and semiconductor device manufactured thereon '' of No. 113921 filed on Oct. 26, 1987 and `` No. 113573 '' filed on Oct. 26, 1987. Homoepitaxial growth of alpha SiC thin film and semiconductor device manufactured on it '' and No. 113561 filed on October 26, 1987, `` Implantation of dopant into silicon carbide single crystal and electrical activation '' Including. Advances in the formation of silicon carbide thin films and silicon carbide single crystals, and in the successful doping of silicon carbide according to these methods, have led to an interest in producing commercial quality devices, including transistors, with silicon carbide. Lighted again.

Various junctions, diodes, rectifiers,
Many attempts have been made to manufacture and other contacts.
More specifically, Wallace is disclosed in US Pat.
No. 254280 describes a method for forming a silicon carbide junction transistor. According to Huaraz, single crystal silicon carbide can be grown by any suitable method known to those skilled in the art, and can be doped using any suitable method known to those skilled in the art. Although the production of doped silicon carbide single crystals is not described by Wallace, in practice it is very difficult to form a doped single crystal with suitable purity and low defect level, and Commercial devices based on this have not yet emerged.

Hall also describes a method for forming a silicon carbide junction transistor in US Pat. No. 2,918,396. The main technology disclosed here is that an alloy of silicon is arranged on an active component (dopant) on the surface of a single crystal of silicon carbide, and the silicon carbide is melted at a temperature equal to or lower than its melting point, and silicon carbide is melted. This is a technique of heating to a temperature at which the surface melts. When the material has cooled, hopefully a pn junction has been formed. According to Hull, a suitable crystal was obtained using the Lely techniq
ue). However, as known to those skilled in the art of silicon carbide, the Rayleigh technique is an immature technique that cannot largely overcome the inherent difficulties in producing device quality silicon carbide single crystals. .

Other researchers have made specific attempts to fabricate MOSFETs on silicon carbide. For example, Jap.J.Appl.Phys.23.L862
(1984) "Inverted MOS field-effect transistor using SiC cube grown by CVD on Si"
describe their attempt to fabricate an inverted n-channel MOSFET on a silicon carbide cube grown on a (100) plane of silicon by chemical vapor deposition (CVD). Shibahara's achievements are described in T. Aselag
e), Minutes of the Materials Research Society Sympsium Proc compiled by D. Emin and C. Wood
Noed Refractory Semiconductor, vol. 97, p. 247 of Pedberg, Pennsylvania, 1978.
s) ”.

Despite the methods described, it is not disclosed that the device by Jibahara et al. Operates successfully at temperatures above room temperature. As mentioned above, operation of the device at very high temperatures is one of the reasons for trying to form the device on silicon carbide. If the device formed on silicon carbide cannot operate at a temperature different from the temperature at which the device formed on silicon operates, no particular advantage will be obtained.

Kondo et al. Also commented on “Experimental 3C-SiC MOSFET”
IEEE Electronics Lett. EDL-7,404 (1986) describes an experimental MOSFET fabricated on beta silicon carbide. According to this description, Kondo first epitaxially grown a beta silicon carbide film on a p-type silicon (100) substrate using CVD. Kondo has manufactured depletion layer MOSFETs. Nevertheless, the resulting device did not show current saturation, threshold cutoff, and high temperature operability. Therefore, the method disclosed in Kondo's paper must be considered a failure.

Accordingly, an object of the present invention is to provide a metal oxide semiconductor field effect transistor (MOSFET) manufactured from silicon carbide.
It is to provide.

Another object of the present invention is to provide both inversion type and depletion layer type silicon carbide MOSFETs.

Yet another object of the present invention is to provide a MOSFET formed on silicon carbide that can operate at a temperature of at least 650 ° C.

(Means for Solving the Problems) Still another object of the present invention is to oxidize a silicon carbide substrate of the first conductivity type to form a silicon dioxide surface layer, and selectively gate the silicon dioxide surface layer. Depositing a contact material, forming a doped source (doped source) and a doped drain (doped drain) of a desired conductivity type by high-temperature implantation of doping ions, and further depositing a source contact and a drain contact At least 650 ° C
It is an object of the present invention to provide a method for forming a metal oxide semiconductor field effect transistor having a high radiation density and capable of operating at a predetermined temperature.

Still another object of the present invention is to perform high-temperature implantation of doping ions into the source and the drain to form a first conductivity type doped source and a doped drain in the doped portion of the second conductivity type silicon carbide. At least 650 ° C
It is an object of the present invention to provide an inversion mode metal insulating film semiconductor field effect transistor which can operate at a high temperature and has high radiation density.

Still another object of the present invention is to perform high-temperature implantation of doping ions into a source and a drain so that a silicon carbide semiconductor portion having the same conductivity type as the doped source and the doped drain is more heavily doped and the source is more heavily doped. At least by forming a drain
An object of the present invention is to provide a depletion layer type metal insulating film semiconductor field effect transistor which can operate at a temperature of 650 ° C. and has a high radiation density.

Other objects and advantages of the present invention are described below with reference to the figures.

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for forming a metal oxide semiconductor field effect transistor capable of operating at a temperature of at least 650 ° C. and at a high radiation density and a high power level.
The method includes the steps of oxidizing a silicon carbide substrate of a first conductivity type to form a silicon dioxide surface layer and selectively depositing a gate contact material on the silicon dioxide surface layer. Doped sources and drains of the desired conductivity type are formed by hot implantation of doping ions, followed by deposition of source and drain contacts.

As an example of the present invention, n-type beta silicon carbide (111) grown epitaxially by chemically distilling a depletion layer type n-channel metal oxide semiconductor field effect transistor on the (0001) plane of 6H alpha silicon carbide single crystal. Fabricated on a thin film. Gate oxide was thermally grown on silicon carbide and the source and drain were n + doped by nitrogen implantation at 823K. Stable saturation and sub-threshold were achieved at drain voltages (V _DS ) greater than 25V. High transconductance of 11.9ms / mm was achieved. Stable transistor operation was observed at a high temperature of 923K. That temperature was the highest temperature ever reported for the fabricated transistor, regardless of the material.

Historically, research on electrical devices formed on silicon carbide has been severely limited, mainly due to the difficulty in obtaining high quality silicon carbide.
However, as described in the previously-assigned patent applications assigned to the same successor, in recent years, growing alpha and beta silicon carbide thin films on silicon carbide substrates and growing large single crystals of silicon carbide. Success has provided a better substrate for device research than ever before.
The MOSFET devices described herein have been formed by using these successful new techniques.

In addition, as noted above, new and successful methods of adding dopant ions to silicon carbide have recently been developed. Attempts to dope silicon carbide at both room temperature (eg, 298 K) as well as low temperatures (eg, 77 K) with ion plantation techniques have been found to be unsuccessful, even following annealing. . However, as described in the application above, ion implantation is performed at relatively high temperatures (eg, 623K, 823K, 1023).
When run at K), initial damage to the grid is minimized, and temperatures that are generally milder than normally required (1200
The annealing step in K) activates the dopant ions.

1 to 5 illustrate several steps used to form an n-channel inversion mode MOSFET according to the present invention and the resulting structure. FIG. 5 is a cross-sectional view of a completed device having the concentric ring structure described further herein. In FIG. 5, the source is indicated by 10 and is of n-type. The drain is indicated by 11, which is also n-type. Both are formed by high-temperature implantation into p-type silicon carbide substrate 12. The gate is shown at 13. The insulator layer of silicon dioxide is denoted by 14, the source contact is denoted by 15, the drain contact is denoted by 16, and the source and drain contacts are tantalum silicide (Ta).
Si ₂ ). This is a new use for this material. As already revealed, the gate 13 has a gate contact 17 made of polysilicon. In a preferred embodiment of the invention, the concentric gate ring has a 20 micrometer (μm) wide connecting strip that extends to a pad of 100 μm × 100 μm contacts. The source contact 15 is an outer concentric semicircle surrounding the gate ring 13 and the gate contact except for the gate connecting strip.
The source ring has a connecting strip that connects to contact pads 15 also 100 micrometers in diameter.

FIG. 1 shows some of the first steps in forming a MOSFET according to the present invention. The silicon dioxide layer 14 is
Is laminated on silicon carbide substrate 12 by a normal oxidation procedure. A layer 17 of phosphorus-doped polysilicon is deposited over the oxide layer 14. A photoresist material 20 is applied and patterned as shown. After etching away the exposed polysilicon and removing the photoresist, the silicon carbide substrate 12 and the oxide layer 14 are then combined with the remaining polysilicon to form the gate contact 17 in FIG. It has the appearance shown. Nitrogen is added to the p-type silicon carbide substrate 12 through high-temperature ion implantation (823K) through the oxide layer 14 to form an n-type well for the source 10 and the drain 11.

In FIG. 3, an additional photoresist 20 is deposited and patterned to etch windows in the exposed oxide layer 14 over the source and drain. In FIG. 4, tantalum silicide 15 is sputter deposited over the photoresist and over the exposed silicon carbide surface exposed through the oxide openings. When the photoresist 20 is removed, only the remaining tantalum silicide is present on the previously exposed silicon carbide surface adjacent to the source and drain (FIG. 5).

FIG. 6 shows a depletion layer type MOSFET formed according to the present invention. In FIG. 6, p-type alpha silicon carbide substrate 21
It holds type beta silicon carbide layer 22 and n type beta silicon carbide layer. 6, a more heavily n-doped source 24 and a more heavily n-doped drain 25 are shown along a channel 26, as shown in FIG. Similarly, in the previously described inversion mode MOSFET, the source contact 27 and the drain contact 30 are formed of tantalum silicide, while the gate contact 31 is formed of polysilicon and overlaid on the oxide layer 32.

In a specific embodiment, the silicon carbide film is first polished using a 0.1 μm diamond paste, oxidized to remove the scuffed portions, and then etched with hydrofluoric acid to remove the oxide film. The gate oxide is subsequently grown, hot concentrated sulfuric acid (H ₂ SO ₄ ) for 5 minutes, 1: 1 mixture of aqueous ammonia (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) for 5 minutes, A three-step cleaning process using hydrofluoric acid (HF) is performed for one minute, followed by a rinse with deionized water.

Doping by phosphorous (P) diffusion at 1173K for 5 minutes, then patterning to form gate contacts as shown in the drawing to form a 500 nm polysilicon over oxide.
Thick films are deposited at 893K by low pressure chemical distillation.

High-temperature ion implantation of nitrogen through an oxide forms an n-type doped source region and an n-type doped source region. The ion implantation is performed at a dose of 5.0 × 10 ¹⁴ cm ₋₂ at 70 KeV,
Perform at 773K.

FIG. 7 shows drain current versus drain voltage characteristics measured at a temperature of 296 K for a beta silicon carbide MOSFET according to the present invention. The particular device measured has a gate length of 7.2 μm, a gate width of 390 μm, and a 24 μm source to drain contact distance. As shown in FIG.
This device showed very stable drain current saturation for a drain-source voltage of 25V. This trend has indeed continued at a source-drain voltage of 30V where the oxides begin to break down. Therefore, this is the first case in which stable saturation has been reported at a drain-source voltage of 5 V or more for a field effect transistor formed of beta silicon carbide.

The threshold voltage was a gate voltage (V _G ) of −12.9 V, as determined from a plot of the square root of the drain-source voltage versus V _G (gate voltage). 25V leakage current at V _DS of the device was in the OFF state (V _G = -15V) 3.75 microamperes (.mu.A). The transconductance of this device at V _DS fixed at 20 V and room temperature is 5.32 ms at V _G = 2.5 V
/ mm.

FIG. 8 is another plot of the drain voltage for the same device, but heated to 573K and stable at that temperature for 15 minutes. Despite the rise in temperature, the drain current saturation was very stable up to 25V. Leakage current at 25V drain-source voltage and -15V gate voltage is 25
A .mu.A, the threshold voltage is shifted to V _G = -13.3V opposite.

FIG. 9 is another plot of drain current versus drain voltage measured at a temperature of 923 K for the same device. The transconductance decreased with this further increase in temperature. In FIG. 9, the low transconductance of the device measured at 923K is indicated by the low current at zero gate voltage compared to FIGS. Transconductance at 923K became irregular above 1V gate voltage, but transconductance was 8V gate voltage and 20V
At a drain-source voltage of about 4.8 ms / mm. This decrease in transconductance at higher temperatures results from an increase in lattice scattering at higher temperatures.

In FIG. 9, the threshold voltage is -14.8V at 923K.
To the gate voltage. The leakage current increased to 128 μA at a gate voltage of −15 V and a drain-source voltage of 25 V.
At 973K, the device showed similar current saturation, but the gate oxide was destroyed. Therefore, current was injected into the gate and the device could not be shut off.

The invention is not limited only to the embodiments described above, but without departing from the scope described in the claims.
Many other embodiments are possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating the steps and resulting structure of an n-channel inversion metal-insulator semiconductor field effect transistor formed according to the present invention.

FIG. 2 is a diagram illustrating the steps and resulting structure of an n-channel inversion metal-insulator semiconductor field effect transistor formed according to the present invention.

FIG. 3 is a diagram illustrating the steps and resulting structure of an n-channel inversion metal-insulator semiconductor field-effect transistor formed according to the present invention.

FIG. 4 is a diagram illustrating the steps and resulting structure of an n-channel inversion metal-insulator semiconductor field effect transistor formed according to the present invention.

FIG. 5 is a diagram illustrating the steps and resulting structure of an n-channel inversion metal-insulator semiconductor field effect transistor formed according to the present invention.

FIG. 6 is a sectional view of an n-channel depletion layer type metal insulating film semiconductor field effect transistor according to the present invention.

FIG. 7 is a graph of drain current versus drain voltage at a temperature of 296 K for an n-channel MOSFET according to the present invention.

FIG. 8 is a graph of drain current versus drain voltage at a temperature of 573 K for a MOSFET similar to FIG. 7 according to the present invention.

FIG. 9 shows a MOSFET similar to FIGS. 7 and 8 according to the invention.
3 is a graph of drain current versus drain voltage at a temperature of 3K.

(Description of Signs) 10 Source 11 Drain 12 P-type silicon carbide substrate 13 Gate 14 Insulator layer 15 Source contact 16 Drain contact 17 Gate contact 20 Photoresist 21 p-type alpha silicon carbide substrate 22 p-type beta silicon carbide layer 24 source 25 Drain 26 Gate 27 Source contact 30 Drain contact 31 Gate contact 32 Oxide layer

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Davis Robert F. Raleigh Runemead Road, 807-35001, North Carolina, USA (56) Reference JP-A-62-181764 (JP, A) JP-A-62-136077 (JP, A)

Claims (24)

(57) [Claims] 1. A method for forming a metal oxide semiconductor field effect transistor operable at a temperature of at least 650 ° C. and a high radiation density, comprising the steps of: a) forming a silicon carbide single crystal substrate having a first conductivity type; Oxidizing to form a silicon dioxide surface layer; b) selectively depositing a gate contact material on said silicon dioxide surface layer; c) heating to a temperature between about 600K and about 1100K. Directing an ion beam of dopant ions to the maintained silicon carbide single crystal substrate to form desired doped sources and drains; and d) depositing source and drain contacts. A method for forming a metal oxide semiconductor field effect transistor, comprising: 2. A method for forming a metal oxide semiconductor field effect transistor according to claim 1, wherein the step of polishing said silicon carbide substrate and the step of oxidizing a damaged portion of said silicon carbide substrate by said polishing step. Performing a step of oxidizing the silicon carbide surface layer and removing an oxidized damaged portion of the silicon carbide substrate before forming the silicon dioxide surface layer, whereby the surface is oxidized. Characterized by further comprising a step of adjusting,
A method for forming a metal oxide semiconductor field effect transistor. 3. A method of forming a metal oxide semiconductor field effect transistor according to claim 1, wherein said step of depositing a gate contact material comprises: forming a conductive polysilicon gate on said silicon dioxide surface layer. A method for forming a metal oxide semiconductor field effect transistor, comprising a step of adding a contact material. 4. A method for forming a metal oxide semiconductor field effect transistor according to claim 1, wherein said step of depositing a source contact and a drain contact comprises forming a tantalum silicide source contact and a tantalum silicide drain contact. A method for forming a metal oxide semiconductor field effect transistor, comprising a step of attaching. 5. A method for forming an inversion mode metal-insulator semiconductor field-effect transistor operable at a temperature of at least 650 ° C. and a high radiation density, the method comprising maintaining the temperature between about 650K and about 1100K. Forming a doping source and a drain of the first conductivity type in a doped portion of silicon carbide of the opposite conductivity type by directing an ion beam of dopant ions to the silicon carbide substrate. Method of forming inversion mode metal insulating film semiconductor field effect transistor. 6. The method of claim 5, wherein the step of forming a doped source and a doped drain includes the steps of: forming a doped source and a doped drain; Forming an inversion-mode metal-insulating-film semiconductor field-effect transistor. 7. The method of claim 5, wherein the step of forming a doped source and a doped drain includes the steps of: forming a doped source and a doped drain; Forming an inverted mode metal insulating film semiconductor field effect transistor in an n-doped portion of silicon carbide. 8. A method for forming a depletion layer type metal insulating semiconductor field effect transistor operable at a temperature of at least 650 ° C. and a high radiation density, the method comprising maintaining the temperature between about 600K and about 1100K. Forming a doped source and a doped drain in a silicon carbide semiconductor portion of the same conductivity type as the doped source and the doped drain by directing an ion beam of dopant ions to the silicon carbide substrate that is being provided. Forming a depletion layer type metal insulating film semiconductor field effect transistor. 9. A method for forming a depletion layer type metal insulating film semiconductor field effect transistor according to claim 8, wherein said step of forming a doped source and a doped drain includes an n-type doped source and an n-type doped source. Forming a doped drain in the n-type silicon carbide semiconductor portion, wherein the source has a higher carrier concentration than the semiconductor portion, and the drain has a higher carrier concentration than the semiconductor portion. Forming a depletion layer type metal insulating film semiconductor field effect transistor. 10. A method for forming a depletion layer type metal insulating film semiconductor field effect transistor according to claim 8, wherein said step of forming a doped source and a doped drain comprises a p-type doped source and a p-type doped source. Dope drain and p
Forming a depletion layer type metal on the silicon carbide semiconductor portion, wherein the source has a higher carrier concentration than the semiconductor portion, and the drain has a higher carrier concentration than the semiconductor portion. A method for forming an insulating film semiconductor field effect transistor. 11. A p-type silicon carbide single crystal substrate, a source formed of an n-type silicon carbide well on said p-type silicon carbide single crystal substrate, and said p-type silicon carbide single crystal substrate A drain formed of a well of n-type silicon carbide separated from the source by a region of a single-crystal silicon carbide single crystal substrate; and the p separating the source and the drain.
Forming an active channel in a region of the p-type silicon carbide single crystal substrate separating the source and the drain; and forming an active channel on the region of the p-type silicon carbide single crystal substrate separating the source and the drain. In an inversion mode metal insulating film semiconductor field effect transistor having a gate contact, a source ohmic contact and a drain ohmic contact, the n-type silicon carbide well forming the source and the drain is formed on the p-type silicon carbide single crystal substrate. Characterized by comprising a region formed by ion beam doping with said insulator layer and gate contact formed thereon. 12. The inversion mode metal-insulator semiconductor field effect transistor according to claim 11, further comprising a gate contact formed of conductive polycrystalline silicon. Metal insulating semiconductor field effect transistor. 13. The inversion mode metal insulating semiconductor field effect transistor according to claim 11, wherein said drain is surrounded by said gate, and said gate is surrounded by said source. Inverting mode metal insulating film semiconductor field effect transistor. 14. The inversion mode metal insulating film semiconductor field effect transistor according to claim 13, wherein said source and said gate form a concentric circle surrounding said drain. Metal insulating semiconductor field effect transistor. 15. A p-type alpha silicon carbide single crystal substrate, a p-type beta silicon carbide layer on the p-type alpha silicon carbide single crystal substrate, and an n-type beta silicon carbide on the p-type beta silicon carbide layer An n-type source region in the n-type beta silicon carbide active layer defined by a carrier concentration higher than the remaining carrier concentration of the n-type beta silicon carbide active layer; An n-type drain region in the n-type beta silicon carbide active layer defined by a carrier concentration higher than the remaining carrier concentration of the active layer; and an n-type drain region between the source region portion and the drain region portion; a channel region in the active layer of the n-type beta silicon carbide bounded by the p-type beta silicon carbide layer, wherein the p-type beta silicon carbide layer has an active layer of the n-type beta silicon carbide. Forming a boundary for electronically bordering the layer with respect to the active layer of the n-type beta silicon carbide, wherein the source region and the drain region are separated from each other in the active layer of the n-type beta silicon carbide. And applying a negative bias to the channel region depletes the channel region of the n-type carrier and causes a current flow in the active layer of the n-type beta silicon carbide between the source region and the drain region. A depletion layer type metal oxide semiconductor field effect transistor, characterized by obstructing the field effect. 16. The depletion layer type metal oxide semiconductor field effect transistor according to claim 15, further comprising a gate contact formed of conductive polysilicon. Metal oxide semiconductor field effect transistor. 17. The depletion layer metal oxide semiconductor field effect transistor according to claim 15, wherein said drain region is surrounded by said gate region, and said gate region is surrounded by said source region. A depletion layer type metal oxide semiconductor field effect transistor, characterized in that: 18. The depletion layer type metal oxide semiconductor field effect transistor according to claim 17, wherein the source region and the gate region form a concentric circle surrounding the drain region. , Depletion layer type metal oxide semiconductor field effect transistor. 19. A p-type silicon carbide single crystal substrate, an n-type beta silicon carbide active layer on the p-type silicon carbide single crystal substrate, and an n-type beta silicon carbide on the n-type beta silicon carbide active layer A source region; and an n-type beta silicon carbide drain region in the n-type beta silicon carbide active layer. The n-type beta silicon carbide active layer portion forms a gate region and a depletion layer region. A depletion layer metal oxide semiconductor field effect transistor having the following operating characteristics at a temperature of 296 K, wherein the following characteristics are at least a drain-source voltage of 25 V and a stable drain-gate voltage at a gate voltage of -15 V. Current saturation, leakage current of less than 4 microamps at drain-source voltage up to 25V, transconductance of at least 5.32ms / mm at 2.5V gate voltage and 20V drain-source voltage And characterized in that, the depletion-type metal oxide semiconductor field effect transistor. 20. A p-type silicon carbide single crystal substrate, an active layer of n-type beta silicon carbide on the p-type silicon carbide single crystal substrate, and an n-type beta silicon carbide on the active layer of n-type beta silicon carbide A source region; and an n-type beta silicon carbide drain region in the n-type beta silicon carbide active layer. The n-type beta silicon carbide active layer portion forms a gate region and a depletion layer region. A depletion layer metal oxide semiconductor field effect transistor having the following operating characteristics at a temperature of 573K, wherein the following characteristics are at least a drain-source voltage of 25V and a stable drain-gate voltage at a gate voltage of -15V. With current saturation, leakage current of less than 23 microamps at drain-source voltage up to 25V, at 5.5V gate voltage and 20V drain-source voltage with at least 6.00ms / mm transconductance A depletion layer type metal oxide semiconductor field effect transistor, characterized in that: 21. A p-type silicon carbide single crystal substrate, an n-type beta silicon carbide active layer on the p-type silicon carbide single crystal substrate, and an n-type beta silicon carbide on the n-type beta silicon carbide active layer A source region; and an n-type beta silicon carbide drain region in the n-type beta silicon carbide active layer. The n-type beta silicon carbide active layer portion forms a gate region and a depletion layer region. A depletion layer metal oxide semiconductor field effect transistor having the following operating characteristics at a temperature of 923 K, wherein the following characteristics are at least a drain-source voltage of 25 V, and a stable drain at a gate voltage of -15 V. With current saturation, a leakage current of less than 130 microamps at drain-source voltages up to 25V, and a gate-voltage of 8V and a drain-source voltage of 20V,
A depletion layer type metal oxide semiconductor field effect transistor having a transconductance of at least 4.8 ms / mm. 22. A method of forming a metal oxide semiconductor field effect transistor operable at a temperature of at least 650 ° C. and a high radiation density, comprising: a) an insulator surface on a silicon carbide single crystal substrate. Forming a layer; b) selectively depositing a gate contact material on said insulator surface layer; c) applying said silicon carbide substrate maintained at a temperature between about 600K and about 1100K. Forming a doped source and a tope drain of a desired conductivity type on the silicon carbide substrate by directing an ion beam of dopant ions; and d) depositing a source contact and a drain contact. A method for forming a metal oxide semiconductor field effect transistor, comprising: 23. A method for forming a metal oxide semiconductor field effect transistor according to claim 22, wherein said step of forming an insulator surface includes forming a layer of silicon nitride on said silicon carbide substrate. Characterized by having a process
A method for forming a metal oxide semiconductor field effect transistor. 24. The method for forming a metal oxide semiconductor field effect transistor according to claim 22, wherein said step of forming an insulator layer includes forming a silicon dioxide surface layer on said silicon carbide substrate. A method for forming a metal oxide semiconductor field-effect transistor, comprising a step of forming.